CN104037208A - 一种双模式绝缘栅晶体管 - Google Patents

一种双模式绝缘栅晶体管 Download PDF

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CN104037208A
CN104037208A CN201410287757.3A CN201410287757A CN104037208A CN 104037208 A CN104037208 A CN 104037208A CN 201410287757 A CN201410287757 A CN 201410287757A CN 104037208 A CN104037208 A CN 104037208A
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张文亮
朱阳军
高君宇
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Jiangsu CAS IGBT Technology Co Ltd
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Abstract

本发明公开了一种双模式绝缘栅晶体管，属于IGBT技术领域。该双模式绝缘栅晶体管包括逆导区和引导区；逆导区和引导区均包括P+集电区，漂移区和MOS元胞区，漂移区均在P+集电区的上方，MOS元胞区均在漂移区的上方；逆导区还包括N+集电区，N+集电区与P+集电区相间分布；引导区还包括分离区或低掺杂区，分离区将引导区的P+集电区与逆导区的P+集电区和N+集电区隔离，低掺杂区在引导区的P+集电区上方。本发明通过增加器件在VDMOS模式时引导区上方电子电流通道的电阻或引导区集电极PN结内建电势，缩小双模式绝缘栅晶体管的引导区尺寸，从而提高了器件工作时内部电流密度的均匀性，近而提高器件的整体可靠性。

Description

一种双模式绝缘栅晶体管
技术领域
本发明属于IGBT技术领域，特别涉及一种双模式绝缘栅晶体管。
背景技术
RC-IGBT是将传统IGBT背面集电区中引入N+掺杂区域(N+集电区)，从而使器件增加了一个反向电流通道。RC-IGBT具有成本和性能上的优势，在一些领域可以替代传统IGBT。RC-IGBT最大的问题是导通时电压会出现snap-back(以后简称“回跳”)，极大的限制了器件的应用。为了抑制回跳现象，RC-IGBT通常需要保证相邻的N+集电区的间距足够大，但这样也造成芯片内部电流分布不均匀，影响器件的可靠性。为此，人们提出了BIGT(双模式绝缘栅晶体管)结构，将RC-IGBT和传统IGBT结构集成在同一芯片。根据器件工作原理，将芯片内部传统IGBT区域称为引导区(Pilot IGBT区)。引导区主要作用是在导通初期引导器件进入IGBT模式，从而避免了回跳的出现，这使得RC-IGBT的设计更加自由，可以为改善电流均匀性将相邻的N+集电区间距缩小。
引导区的引入，使得RC-IGBT区的设计更加自由，N+集电区间距的设计不要考虑抑制回跳的问题。这使得设计自由度增加，也有利于更充分地优化RC-IGBT的整体性能。所以双模式绝缘栅晶体管芯片中的RC-IGBT区，N+集电区间距可以适当减小以改善芯片内部的电流均匀性问题。但双模式绝缘栅晶体管并没有彻底改善芯片内部的电流均匀性，实事上只有RC-IGBT区的电流分布较为均匀，而引导区及附近N+集电区电流均匀性仍然较差。比如，当双模式绝缘栅晶体管工作于IGBT模式时，引导区中间区域电流密度比引导区边缘及逆导区的电流密度要大很多。当双模式绝缘栅晶体管工作于二极管模式时，与引导区相邻的N+集电区的电流密度较其它N+集电区的电流密度大很多。因此双模式绝缘栅晶体管的器件结构仍然存在可靠性风险。
双模式绝缘栅晶体管可以使得RC-IGBT的设计更加自由，在一定程度上改善了芯片内部电流的均匀性，但双模式绝缘栅晶体管的引导区附近仍会出较严重的电流集中问题，导致芯片的可靠性较差，主要表面为以下几个方面：
第一、芯片内部不同区域温度差较大，芯片内部由于温度梯度引入了较大的应力导致器件的功率循环能力较差。
第二、由于电流会集中在某些特点区域，当器件承受电流过冲时会导致芯片某些薄弱区域烧毁，导致器件的抗电流过冲能力较差。
第三、由于电流可会集中在某些特点区域，导致器件的抗短路能力较差。
以上三个方面均会造成器件可靠性较差，不利于器件长期安全工作。
发明内容
本发明所要解决的技术问题是提供一种双模式绝缘栅晶体管，解决了现有技术中双模式绝缘栅晶体管引导区尺寸太大，导致引导区及其附近区域电流集中较严重的技术问题。
为解决上述技术问题，本发明提供了一种双模式绝缘栅晶体管，包括逆导区和引导区；
所述逆导区和所述引导区均包括P+集电区，漂移区和MOS元胞区，所述漂移区均在所述P+集电区的上方，所述MOS元胞区均在所述漂移区的上方；
所述逆导区还包括N+集电区，所述N+集电区与所述P+集电区相间分布；
所述引导区还包括分离区或低掺杂区，所述分离区将所述引导区的P+集电区与所述逆导区的P+集电区和所述N+集电区隔离，所述低掺杂区在所述引导区的P+集电区的上方。
进一步地，所述逆导区和所述引导区均还可以设置N+缓冲层，所述逆导区的N+缓冲层在所述逆导区的P+集电区或N+集电区和所述逆导区的漂移区之间，所述引导区的N+缓冲层在所述引导区的P+集电区和所述引导区的漂移区之间，所述引导区的分离区将所述逆导区的N+缓冲层和所述引导区的N+缓冲层隔离。
进一步地，所述分离区的下方还有一绝缘体区，所述绝缘体区位于硅衬底与集电极金属层之间，通过调整所述绝缘体区的宽度使所述引导区的N+缓冲层与集电极金属电位隔离。
进一步地，所述分离区为填充有绝缘体的沟槽。
进一步地，所述引导区的N+缓冲层掺杂浓度小于所述逆导区N+缓冲层掺杂浓度。
进一步地，所述低掺杂区的掺杂浓度均小于所述引导区的N+缓冲层和所述引导区的P+集电区的掺杂浓度。
本发明提供的双模式绝缘栅晶体管，通过设置分离区或绝缘体沟槽，增加器件在VDMOS模式时电子电流通道的电阻，缩小双模式绝缘栅晶体管的引导区尺寸。使器件工作时电流在芯片内分布更均匀，从而提高了器件整体的可靠性。另外，通过设置低掺杂区，降低引导区集电极PN的开启电压，从而缩小双模式绝缘栅晶体管的引导区尺寸。使器件工作时电流在芯片内分布更均匀，从而提高了器件整体的可靠性。
附图说明
图1为本发明实施例1提供的一种绝缘体逆导区一侧上方为P+集电区的双模式绝缘栅晶体管；
图2为本发明实施例1提供的一种绝缘体逆导区一侧上方为N+集电区的双模式绝缘栅晶体管；
图3为本发明实施例1提供的一种具有条形N+集电区的双模式绝缘栅晶体管的背面版图布局；
图4为本发明实施例1提供的一种具有圆形N+集电区的双模式绝缘栅晶体管的背面版图布局；
图5为本发明实施例2提供的一种绝缘体沟槽逆导区一侧为P+集电区，并且分离区为沟槽的双模式绝缘栅晶体管；
图6为本发明实施例2提供的一种绝缘体沟槽逆导区一侧为N+集电区，并且分离区为沟槽的双模式绝缘栅晶体管；
图7为本发明实施例3提供的一种没有N+缓冲层，且绝缘体沟槽逆导区一侧为P+集电区的双模式绝缘栅晶体管；
图8为本发明实施例3提供的一种没有N+缓冲层，绝缘体沟槽逆导区一侧为N+集电区的双模式绝缘栅晶体管；
图9为本发明实施例4提供的一种引导区的缓冲层掺杂浓度小于逆导区的缓冲层掺杂浓度，且低浓度缓冲层部分覆盖P+集电区的双模式绝缘栅晶体管；
图10为本发明实施例4提供的一种引导区的缓冲层掺杂浓度小于逆导区的缓冲层掺杂浓度，且低浓度缓冲层完全覆盖P+集电区的双模式绝缘栅晶体管；
图11为本发明实施例5提供的一种引导区包含完全覆盖P+集电区，且具有低掺杂区的双模式绝缘栅晶体管；
图12为本发明实施例5提供的一种引导区包含部分覆盖P+集电区，且具有低掺杂区的双模式绝缘栅晶体管。
具体实施方式
参见图1，本发明实施例提供的一种双模式绝缘栅晶体管，包括逆导区和引导区；
逆导区和引导区均包括P+集电区，漂移区和MOS元胞区，漂移区均在P+集电区的上方，MOS元胞区均在漂移区的上方；
逆导区还包括N+集电区，N+集电区与P+集电区相间分布；
引导区还包括分离区或低掺杂区，分离区将引导区的P+集电区与逆导区的P+集电区和N+集电区隔离，低掺杂区在引导区的P+集电区的上方。
本发明提供的双模式绝缘栅晶体管，通过设置分离区或绝缘体沟槽，增加器件在VDMOS模式时电子电流通道的电阻，缩小双模式绝缘栅晶体管的引导区尺寸。使器件工作时电流在芯片内分布更均匀，从而提高了器件整体的可靠性。另外，通过设置低掺杂区，降低引导区集电极PN的开启电压，从而缩小双模式绝缘栅晶体管的引导区尺寸。使器件工作时电流在芯片内分布更均匀，从而提高了器件整体的可靠性。
实施例1：
参见图1、图2、图3和图4，在本实施例中，引导区包括分离区，其基本思路是将引导区的N+缓冲层与逆导区的N+缓冲层分离，这也就是说让这两部分缓冲层结构相互隔离，如图1和图2所示。分离区为未引入缓冲层掺杂的半导体衬底，通常与N-漂移区掺杂浓度相同，当然也可以适当引入少量杂质或者将此区域加工成为电阻率大于N-漂移区的半导体结构。
为了保证器件耐压，在分离区下方制造一定尺寸的绝缘体区，绝缘体区位于半导体衬底与集电极金属层之间。绝缘体的宽度要保证可以将所述N+缓冲层与集电极金属电位隔离，绝缘体区的作用是防止器件耐压时耗尽区边界与集电极金属接触而发生穿通击穿。
本实施例中，绝缘体靠近逆导区一侧上方可以设置一段P+集电区(如图1)，也可直接设置为N+集电区(如图2)。
背面版图布局以图3和图4为例，通过将引导区的缓冲层隔离，可以使引导区两侧或四周的N+集电区间距减小为与逆导区N+集电区间距相当的水平。这样可以使N+集电区在整个芯片范围内均匀且规律地分布，很大程度地改善了电流均匀性。这样当器件处于VDMOS模式时，引导区上方的电子电流必须流过引导区的缓冲层(分布电阻为Rb1)、分离区处的低掺杂区(分布电阻为Rd)以及逆导区的缓冲层(分布电阻为Rb2)。由于缓冲层之间为低掺杂区，故Rd>>Rb1+Rb2。Rd的引入可以使得引导区不必拉大P+集电区的宽度就足以抑制器件的回跳，从而使引导区的两侧或四周的N+集电区间距缩小。通过调整缓冲层不连续处的低掺杂区宽度及掺杂浓度可以控制Rd的大小，使得引导区的宽度可以降低到同逆导区P+集电区宽度相当的水平，很大程度地改善了电流均匀性问题。通常缓冲层之间低掺杂区宽度越大，掺杂浓度越低，Rd就会越大，引导区的宽度可以降得越小。但Rd的阻值并不是越大越好，只要能够保证器件不会出现回跳即可。
实施例2：
本实施例提供的双模式绝缘栅晶体管与实施例1的结构相似。两者的不同之处是，实施例2的分离区为填充有绝缘体的沟槽，N+缓冲层和集电区被一个填充有绝缘体的沟槽所分离(如图5和图6)。图示沟槽左侧缓冲层为引导区缓冲层，沟槽右侧缓冲层为逆导区缓冲层。
本实施例中，绝缘体靠近逆导区一侧可以设置一段P+集电区(如图5)，也可直接设置为N+集电区(如图6)。
当器件处于VDMOS模式时，引导区上方的电子电流必须流过引导区的缓冲层(分布电阻为Rb1)、沟槽两侧及上方的低掺杂区(总分布电阻为Rd)以及逆导区的缓冲层(分布电阻为Rb2)。由于沟槽两侧及上方为低掺杂区，故Rd>>Rb1+Rb2。Rd的引入可以使得引导区不必拉大P+集电区的宽度就足以抑制器件的回跳，从而使引导区的两侧或四周的N+集电区间距缩小。通过调整沟槽的宽度及深度可以控制Rd的大小，使得引导区的宽度可以降低到同逆导区P+集电区宽度相当的水平，很大程度地改善了电流均匀性问题。通常沟槽的宽度及深度越大，Rd越大，引导区的宽度可以降得越小。但Rd的阻值并不是越大越好，只要能够保证器件不会出现回跳即可。
实施例3：
事实上，不光FS结构的双模式绝缘栅晶体管可以采用此方案，NPT结构的双模式绝缘栅晶体管也可以改善电流均匀性。实施例3提出的逆导区的结构与实施例2的结构相似。两者的不同之处是，实施例3的结构中没有N+缓冲层结构。
本实施例中，绝缘体靠近逆导区一侧可以设置一段P+集电区(如图7)，也可直接设置为N+集电区(如图8)。
当器件处于VDMOS模式时，引导区上方的电子电流必须流过引导区的漂移区(分布电阻为Rd1)、沟槽两侧及上方的低掺杂区(总分布电阻为Rd)以及逆导区N+集电区上方的漂移区(分布电阻为Rd2)。Rd的引入可以使得引导区不必拉大P+集电区的宽度就足以抑制器件的回跳，从而使引导区的两侧或四周的N+集电区间距缩小。通过调整沟槽的宽度及深度可以控制Rd的大小，使得引导区的宽度可以降低到同逆导区P+集电区宽度相当的水平，很大程度地改善了电流均匀性问题。通常沟槽的宽度及深度越大，Rd越大，引导区的宽度可以降得越小。但Rd的阻值并不是越大越好，只要能够保证器件不会出现回跳即可。
实施例4：
本实施例中将引导区N+缓冲层的掺杂浓度在保证器件耐压足够的前提下作适当减小。也就是说引导区的缓冲层掺杂浓度小于逆导区的缓冲层掺杂浓度。
本实施例中，引导区上方的低掺杂缓冲层可以部分覆盖P+集电区(如图9)，也可以全部覆盖P+集电区(如图10)，甚至将相邻的N+集电区也全部或部分覆盖。
当器件处于VDMOS模式时，引导区上方的电子电流必须流过引导区的低掺杂缓冲层(分布电阻为Rb1，且阻值较大)和引导区的高掺杂缓冲层(分布电阻为Rb2)。由于低掺杂缓冲层的引入，使得Rb1+Rb2达到较大的水平。另外，由于低掺杂缓冲层引入，使得P+集电区和N+缓冲层所组成的PN结开启电压降低。以上两方面的因素使得引导区不必拉大P+集电区的宽度就足以抑制器件的回跳，从而使引导区的两侧或四周的N+集电区间距缩小。通过调整低掺杂缓冲层的长度可以控制Rb1的大小，使得引导区的宽度可以降低到同逆导区P+集电区宽度相当的水平，很大程度地改善了电流均匀性问题。通常低掺杂缓冲层的长度越大，Rb1越大，引导区的宽度可以降得越小。但Rb1的阻值并不是越大越好，只要能够保证器件不会出现回跳即可。
实施例5：
在本实施例中，低掺杂区的掺杂浓度均小于引导区的N+缓冲层和引导区的P+集电区的掺杂浓度。
此低掺杂区可以为P型，也可以为N型，还可以既有P区又有N区。对于既有P区又有N区的情况，需要保证P型低掺杂区位于P+集电区上方，而N型低掺杂区位于P型低掺杂区及N+缓冲层之间。
本实施例中，引导区的低掺杂区可以部分覆盖P+集电区(如图11)，也可以全部覆盖P+集电区(如图12)，甚至将相邻的N+集电区也全部或部分覆盖。
在器件引导区的N+缓冲层及P+集电区之间引入低掺杂区，使得集电极PN结一侧或两侧有低掺杂半导体，很大程度地降低了PN结的开启电压。使得引导区不必拉大P+集电区的宽度就足以抑制器件的回跳，从而使引导区的两侧或四周的N+集电区间距缩小。通过调整低掺杂区的浓度可以控制PN结开启的大小，使得引导区的宽度可以降低到同逆导区P+集电区宽度相当的水平，很大程度地改善了电流均匀性问题。通常低掺杂区掺杂浓度较小，集电结开启所需的电压越小，引导区的宽度可以降得越小。
本发明实施例提供的双模式绝缘栅晶体管，可以使双模式绝缘栅晶体管的引导区宽度从几百微米减小为几十微米，极大地改善了双模式绝缘栅晶体管芯片的电流均匀性，提高了器件的可靠性。具体可以改善器件的功率循环能力、抗电流过冲能力和抗短路能力等。
在实际工程中的版图方案可以有多种图形组成，但均可以根据本发明实施例提供的结构，将部分P+集电区隔离出来，形成一个小尺寸引导区结构。
对于可以使得引导区P+集电区宽度可以减小的方案本专利不再一一列举,凡是采用特定技术方案使得引导区P+集电区宽度减小以改善电流均匀性的方案均属本专利的保护范围。
因此，双模式绝缘栅晶体管的缺点在于引导区两侧或四周的N+集电区间距太大，导致电流集中。本专利的思想就是通过各种方法减小引导区的宽度，也就是减小引导区两侧或四周N+集电区间距，这样能近一步改善双模式绝缘栅晶体管的引导区的电流分布，近而提高器件的可靠性。
最后所应说明的是，以上具体实施方式仅用以说明本发明的技术方案而非限制，尽管参照实例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (6)

1.一种双模式绝缘栅晶体管，其特征在于，包括逆导区和引导区；
所述逆导区和所述引导区均包括P+集电区，漂移区和MOS元胞区，所述漂移区均在所述P+集电区的上方，所述MOS元胞区均在所述漂移区的上方；
所述逆导区还包括N+集电区，所述N+集电区与所述P+集电区相间分布；
所述引导区还包括分离区或低掺杂区，所述分离区将所述引导区的P+集电区与所述逆导区的P+集电区和所述N+集电区隔离，所述低掺杂区在所述引导区的P+集电区的上方。
2.根据权利要求1所述的双模式绝缘栅晶体管，其特征在于，所述逆导区和所述引导区均还可以设置N+缓冲层，所述逆导区的N+缓冲层在所述逆导区的P+集电区或N+集电区和所述逆导区的漂移区之间，所述引导区的N+缓冲层在所述引导区的P+集电区和所述引导区的漂移区之间，所述引导区的分离区将所述逆导区的N+缓冲层和所述引导区的N+缓冲层隔离。
3.根据权利要求2所述的双模式绝缘栅晶体管，其特征在于，所述分离区的下方还有一绝缘体区，所述绝缘体区位于硅衬底与集电极金属层之间，通过调整所述绝缘体区的宽度使所述引导区的N+缓冲层与集电极金属电位隔离。
4.根据权利要求1所述的双模式绝缘栅晶体管，其特征在于，所述分离区为填充有绝缘体的沟槽。
5.根据权利要求2所述的双模式绝缘栅晶体管，其特征在于，所述引导区的N+缓冲层掺杂浓度小于所述逆导区N+缓冲层掺杂浓度。
6.根据权利要求2所述的双模式绝缘栅晶体管，其特征在于，所述低掺杂区的掺杂浓度均小于所述引导区的N+缓冲层和所述引导区的P+集电区的掺杂浓度。
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