WO2015196534A1 - 一种双模式绝缘栅晶体管 - Google Patents

一种双模式绝缘栅晶体管 Download PDF

Info

Publication number
WO2015196534A1
WO2015196534A1 PCT/CN2014/084086 CN2014084086W WO2015196534A1 WO 2015196534 A1 WO2015196534 A1 WO 2015196534A1 CN 2014084086 W CN2014084086 W CN 2014084086W WO 2015196534 A1 WO2015196534 A1 WO 2015196534A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
collector
guiding
buffer layer
insulated gate
Prior art date
Application number
PCT/CN2014/084086
Other languages
English (en)
French (fr)
Inventor
张文亮
朱阳军
高君宇
Original Assignee
江苏中科君芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏中科君芯科技有限公司 filed Critical 江苏中科君芯科技有限公司
Priority to US15/321,688 priority Critical patent/US20170148878A1/en
Publication of WO2015196534A1 publication Critical patent/WO2015196534A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the invention belongs to the technical field of I GBT, and particularly relates to a dual mode insulated gate transistor. Background technique
  • the RC-I GBT introduces the N+ doped region (N+ collector region) into the backside of the conventional IGBT, which adds a reverse current path to the device.
  • RC-IGBTs have cost and performance advantages and can replace traditional I GBT in some areas.
  • the biggest problem with RC-IGBTs is that the voltage will appear snap-back (hereinafter referred to as "rebound"), which greatly limits the application of the device.
  • the RC-IGBT usually needs to ensure that the spacing between adjacent N+ collector regions is large enough, but this also causes uneven current distribution inside the chip, which affects the reliability of the device.
  • a BIGT (Double Mode Insulated Gate) structure has been proposed to integrate the RC-I GBT and the conventional IGBT structure on the same chip.
  • the traditional IGBT area inside the chip is called the lead-in area (P i lo t IGBT area).
  • the main function of the guiding area is to guide the device into the IGBT mode at the initial stage of conduction, thus avoiding the occurrence of rebound, which makes the design of the RC-IGBT more free, and can narrow the adjacent N+ collector spacing for improving the current uniformity. .
  • the introduction of the lead-in area makes the design of the RC-I GBT area more free, and the design of the N+ collector area spacing should not consider the problem of suppressing the rebound. This increases the freedom of design and also helps to optimize the overall performance of the RC-I GBT more fully. Therefore, in the RC-I GBT region of the dual mode insulated gate transistor chip, the N+ collector pitch can be appropriately reduced to improve the current uniformity inside the chip. However, the dual-mode insulated gate transistor does not completely improve the current uniformity inside the chip. In fact, only the current distribution in the RC-IGBT region is relatively uniform, and the current uniformity in the lead region and the nearby N+ collector region is still poor.
  • the dual mode insulated gate transistor when the dual mode insulated gate transistor operates in the I GBT mode, the current density in the middle region of the lead region is much larger than the current density at the edge of the lead region and the reverse conducting region.
  • the dual mode insulated gate transistor operates in diode mode, the current density of the N+ collector region adjacent to the lead region is much greater than the current density of other N+ collector regions. Therefore, the device structure of the dual mode insulated gate transistor still has a reliability risk.
  • the dual-mode insulated gate transistor can make the design of the RC-IGBT more free, and improve the uniformity of the current inside the chip to a certain extent.
  • the current concentration problem of the dual-mode insulated gate transistor still has a serious current concentration problem, resulting in the chip.
  • the reliability is poor, the main surface is the following aspects: First, the temperature difference between different parts of the chip is large, and the internal stress of the chip introduces a large stress, which leads to poor power cycle capability of the device.
  • the technical problem to be solved by the present invention is to provide a dual-mode insulated gate transistor, which solves the technical problem that the size of the guiding region of the dual-mode insulated gate transistor is too large in the prior art, resulting in a serious current concentration in the guiding region and its vicinity.
  • the present invention provides a dual mode insulated gate transistor including a reverse conducting region and a guiding region;
  • the reverse conducting region and the guiding region each include a P+ collector region, a drift region and a MOS cell region, wherein the drift region is above the P+ collector region, and the MOS cell region is in the Above the drift region; the reverse conducting region further includes an N+ collector region, wherein the N+ collector region is distributed between the P+ collector region; the guiding region further includes a separation region or a low-doping region, and the separating The region isolates the P+ collector region of the lead region from the P+ collector region of the reverse conducting region and the N+ collector region, the low doped region being above the P+ collector region of the lead region.
  • each of the reverse conducting region and the guiding region may further be provided with an N+ buffer layer, and the N+ buffer layer of the reverse conducting region is in a P+ collector region or an N+ collector region of the reverse conducting region.
  • the N+ buffer layer of the guiding region is between the P+ collecting region of the guiding region and the drift region of the guiding region, and the separating region of the guiding region will be The N+ buffer layer of the reverse conducting region is isolated from the N+ buffer layer of the guiding region.
  • the insulator region is located between the silicon substrate and the collector metal layer, and the N+ buffer layer and the set of the guiding region are adjusted by adjusting the width of the insulator region.
  • the electrode metal potential is isolated.
  • the separation region is a trench filled with an insulator.
  • the N+ buffer layer doping concentration of the guiding region is smaller than the reverse conducting region N+ buffer layer doping concentration.
  • the doping concentration of the low doped region is smaller than the doping concentration of the N+ buffer layer of the lead region and the P+ collector region of the lead region.
  • the dual mode insulated gate transistor increases the resistance of the electronic current channel of the device in the VDM0S mode by setting a separation region or an insulator trench, and reduces the size of the guiding region of the dual mode insulated gate transistor.
  • the current is distributed more evenly within the chip while the device is operating, thereby increasing the overall reliability of the device.
  • the turn-on voltage of the collector region collector PN is lowered, thereby reducing the size of the lead region of the dual mode insulated gate transistor.
  • the current is distributed more evenly within the chip while the device is operating, thereby increasing the overall reliability of the device.
  • DRAWINGS 1 is a dual-mode insulated gate transistor with a P+ collector region on one side of a reverse conducting region of an insulator according to Embodiment 1 of the present invention;
  • FIG. 2 is a dual mode insulated gate transistor with an N+ collector region on one side of a reverse conducting region of an insulator according to Embodiment 1 of the present invention
  • FIG. 3 is a rear layout layout of a dual mode insulated gate transistor having a strip-shaped N+ collector region according to Embodiment 1 of the present invention
  • FIG. 4 is a rear layout layout of a dual mode insulated gate transistor having a circular N+ collector region according to Embodiment 1 of the present invention
  • FIG. 5 is a dual-mode insulated gate transistor with a P+ collector region on one side of the trench back-conducting region and a trench in the isolation region according to Embodiment 2 of the present invention
  • FIG. 6 is a dual-mode insulated gate transistor with a N+ collector region on one side of an insulator trench reverse conducting region and a trench in the isolation region according to Embodiment 2 of the present invention
  • FIG. 9 is a schematic diagram of a dual-mode insulated gate in which a buffer layer doping concentration of a guiding region is smaller than a buffer layer doping concentration of a reverse conducting region, and a low-concentration buffer layer partially covers a P+ collector region according to Embodiment 4 of the present invention.
  • Transistor FIG. 10 is a dual mode of a buffer layer doping concentration of a guiding region is smaller than a buffer layer doping concentration of a reverse conducting region, and a low concentration buffer layer completely covers a P+ collector region according to Embodiment 4 of the present invention; Insulated gate transistor
  • FIG. 11 is a schematic diagram of a dual-mode insulated gate transistor including a low-doped region and a lead-in region completely covering a P+ collector region according to Embodiment 5 of the present invention
  • FIG. 12 is a schematic diagram of a dual mode insulated gate transistor including a partially covered P+ collector region and having a low doped region, according to Embodiment 5 of the present invention. detailed description
  • a dual mode insulated gate transistor includes a reverse conducting region and a guiding region
  • Both the reverse conducting region and the guiding region include a P+ collector region, a drift region and a M0S cell region, and the drift region is above the P+ collector region, and the M0S cell region is above the drift region;
  • the reverse conducting region further includes an N+ collector region, and the N+ collector region and the P+ collector region are inter-phased;
  • the guiding region further comprises a separating region or a low doping region, wherein the separating region separates the P+ collecting region of the guiding region from the P+ collecting region and the N+ collecting region of the reverse conducting region, and the P+ collecting region of the germanium doping region in the guiding region Above.
  • the dual mode insulated gate transistor provided by the invention increases the resistance of the electronic current channel of the device in the VDM0S mode by setting a separation region or an insulator trench, and reduces the size of the guiding region of the dual mode insulated gate transistor. The current is distributed more evenly within the chip while the device is operating, thereby increasing the overall reliability of the device.
  • the turn-on voltage of the collector region collector PN is lowered, thereby reducing the size of the lead region of the dual mode insulated gate transistor.
  • the current is distributed more evenly within the chip while the device is operating, thereby increasing the overall reliability of the device.
  • the guiding area includes a separating area, and the basic idea is to separate the N+ buffer layer of the guiding area from the N+ buffer layer of the reverse conducting area, which is also That is to say, the two parts of the buffer layer structure are isolated from each other, as shown in FIGS. 1 and 2.
  • the separation region is a semiconductor substrate doped without a buffer layer, and is usually doped to the same concentration as the N-drift region.
  • impurities may be appropriately introduced or the region may be processed into a semiconductor structure having a resistivity greater than the N-drift region.
  • a certain size of the insulator region is formed under the separation region, and the insulator region is located between the semiconductor substrate and the collector metal layer.
  • the width of the insulator is such that the N+ buffer layer can be isolated from the collector metal potential, and the insulator region serves to prevent punch-through breakdown of the depletion region boundary from contact with the collector metal when the device withstands voltage.
  • a P+ collector region (as shown in Fig. 1) may be disposed above the side of the insulator near the reverse conducting region, or may be directly set as an N+ collector region (Fig. 2 ).
  • the rear layout layout is illustrated by taking FIG. 3 and FIG. 4 as an example.
  • the spacing of the N+ collector regions on both sides or around the guiding area can be reduced to be equivalent to the spacing of the reverse conducting area N+ collecting area.
  • Level. This allows the N+ collector region to be evenly and regularly distributed throughout the chip, greatly improving current uniformity.
  • the electron current above the guiding region must flow through the buffer layer of the guiding region (distribution resistance is Rbl), the low doping region at the separation region (distribution resistance is Rd), and the retardation region is slow.
  • Punching layer distributed resistance is Rb2).
  • the introduction of Rd»Rbl + Rb2 0 Rd can make the lead region not have to widen the width of the P+ collector region to suppress the rebound of the device, thereby making both sides of the guiding region Or the surrounding N+ collector area is reduced in pitch.
  • the size of Rd can be controlled by adjusting the width of the low doping region and the doping concentration at the discontinuity of the buffer layer, so that the width of the guiding region can be reduced to a level equivalent to the width of the reverse conducting region P+ collecting region, which is greatly improved. Current uniformity problem.
  • the larger the width of the low doping region between the buffer layers, the lower the doping concentration, the larger Rd, and the smaller the width of the guiding region can be reduced.
  • the resistance of Rd is not as large as possible, as long as it can guarantee that the device will not rebound.
  • the dual mode insulated gate transistor provided in this embodiment is similar in structure to the first embodiment.
  • the difference between the two is that the separation region of Embodiment 2 is a trench filled with an insulator, and the N+ buffer layer and the collector region are one.
  • the trench filled with insulator is separated (see Figures 5 and 6).
  • the buffer layer on the left side of the trench is the buffer layer of the lead region, and the buffer layer on the right side of the trench is the buffer layer of the reverse conducting region.
  • a P+ collector region (Fig. 5) may be disposed on the side of the insulator near the reverse conducting region, or may be directly set as an N+ collector region (Fig. 6).
  • the electron current above the lead-in region must flow through the buffer layer of the lead-in region (distribution resistance is Rbl), the low-doped region on both sides and above the trench (total distributed resistance is Rd), and the reverse conductance
  • the buffer layer of the zone (distribution resistance is Rb2). Since the two sides of the trench and the upper side are low doped regions, the introduction of Rd»Rbl + Rb2 0 Rd can make the lead region not have to widen the width of the P+ collector region to suppress the rebound of the device, thereby making the two of the guiding regions The side or surrounding N+ collector area is reduced in pitch.
  • the size of Rd can be controlled by adjusting the width and depth of the trench so that the width of the guiding region can be reduced to a level equivalent to the width of the reverse conducting region P+ collector region, greatly improving the current uniformity problem.
  • the resistance of Rd is not as large as possible, as long as it can guarantee that the device will not rebound.
  • a dual-mode insulated gate transistor of the FS structure can be used for this scheme, and the NPT structure of the dual-mode insulated gate transistor can also improve current uniformity.
  • the structure of the retroreflective zone proposed in Example 3 is similar to that of Embodiment 2. The difference between the two is that the structure of Embodiment 3 does not have an N+ buffer layer structure.
  • a side of the insulator close to the reverse conducting region may be provided with a P+ collector region (as shown in Fig. 7), or may be directly set as an N+ collector region (Fig. 8).
  • the electron current above the lead-in region must flow through the drift region of the lead-in region (distributed resistance is Rdl), the low-doped region on both sides and above the trench (total distributed resistance is Rd), and the reverse conducting region
  • the drift region above the N+ collector region (distribution resistance is Rd2).
  • the introduction of Rd can make it unnecessary for the lead-in area to be widened.
  • the width of the P+ collector area is sufficient to suppress the rebound of the device, thereby narrowing the spacing of the N+ collector regions on both sides or four weeks of the lead-in area.
  • the size of Rd can be controlled so that the width of the guiding region can be as low as the width of the P+ collector region of the reverse conducting region, which greatly improves the current uniformity problem.
  • the larger the width and depth of the trench the larger Rd is, and the smaller the width of the guiding region can be. But the resistance of Rd is not as large as possible, as long as it can guarantee that the device will not return to ii.
  • the doping concentration of the buffer region N+ buffer layer is appropriately reduced under the premise that the withstand voltage of the device is sufficient. That is to say, the buffer layer doping concentration of the guiding region is smaller than the buffer layer doping concentration of the reverse conducting region.
  • the low-doped buffer layer above the guiding region may partially cover the P+ collector region (as shown in the figure). 9), it is also possible to cover the P+ collector area (Fig. 10), and even cover all or part of the adjacent N+ collector area.
  • the electron current above the lead-in region must flow through the low-doped buffer layer of the lead-in region (distributed resistance is Rbl and the resistance is large) and the highly doped buffer layer of the lead-in region (distribution resistance) For Rb2).
  • Rbl+Rb2 reaches a large level due to the introduction of a low doping buffer layer.
  • the PN junction turn-on voltage of the P+ collector region and the N+ buffer layer is lowered.
  • the size of Rb 1 can be controlled so that the width of the guiding region can be as low as P to the level of the width of the reverse conducting region P+ collecting region, which greatly improves the current uniformity problem.
  • the resistance of Rbl is not as large as possible, as long as it can guarantee that the device will not rebound.
  • the doping concentration of the low doped region is smaller than the doping concentration of the N+ buffer layer of the lead region and the P+ collector region of the lead region.
  • the low doped region may be P-type or N-type, and may have both a P region and an N region. For the case of both the P region and the N region, it is necessary to ensure that the P-type low doped region is located above the P+ collector region, and the N-type low doped region is located between the P-type low doped region and the N+ buffer layer.
  • the low-doped region of the guiding region may partially cover the P+ collector region (as shown in FIG. 11), or may completely cover the P+ collector region (as shown in FIG. 12), or even the adjacent N+ collector region. Or partial
  • a low-doped region is introduced between the N+ buffer layer and the P+ collector region of the device lead-in region, so that the collector PN junction has low-doped semiconductor on one side or both sides, which greatly reduces the turn-on voltage of the PN junction. It is not necessary to widen the lead-in area of the P+ collector region to suppress the rebound of the device, thereby narrowing the spacing of the N+ collector regions on both sides or around the lead-out region.
  • the concentration of the low doped region the size of the PN junction can be controlled, so that the width of the guiding region can be reduced to a level equivalent to the width of the P+ collector region of the reverse conducting region, which greatly improves the current uniformity problem.
  • the doping concentration of the low doping region is small, and the smaller the voltage required for the collector junction to be turned on, the smaller the width of the guiding region can be reduced.
  • the dual-mode insulated gate transistor provided by the embodiment of the invention can reduce the guiding region width of the dual-mode insulated gate transistor from several hundred micrometers to several tens of micrometers, which greatly improves the current uniformity of the dual-mode insulated gate transistor chip and improves The reliability of the device. Specifically, it can improve the power cycling capability, current overshoot capability, and short circuit resistance of the device.
  • the layout scheme in the actual engineering can be composed of a plurality of graphics, but all of the P+ collector regions can be isolated according to the structure provided by the embodiment of the present invention to form a small-sized guiding region structure.
  • this patent no longer lists one by one, and any scheme that reduces the width of the lead-in area P+ collector area to improve current uniformity by using a specific technical solution belongs to the patent. protected range.
  • the disadvantage of the dual mode insulated gate transistor is that the N+ collector interval on both sides or around the lead-in area is too large, resulting in current concentration.
  • the idea of this patent is to reduce the width of the guiding region by various methods, that is, to reduce the spacing of the N+ collector regions on both sides or around the guiding region, which can further improve the current distribution of the guiding region of the dual mode insulated gate transistor, Improve the reliability of the device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

一种双模式绝缘栅晶体管，属于IGBT技术领域。该双模式绝缘栅晶体管包括逆导区和引导区；逆导区和引导区均包括P+集电区，漂移区和MOS元胞区，漂移区均在P+集电区的上方，MOS元胞区均在漂移区的上方；逆导区还包括N+集电区，N+集电区与P+集电区相间分布；引导区还包括分离区或低掺杂区，分离区将引导区的P+集电区与逆导区的P+集电区和N+集电区隔离，低掺杂区在引导区的P+集电区上方。通过增加器件在VDMOS模式时引导区上方电子电流通道的电阻或引导区集电极PN结内建电势，缩小双模式绝缘栅晶体管的引导区尺寸，从而提高了器件工作时内部电流密度的均匀性，进而提高器件的整体可靠性。

Description

一种双模式绝缘栅晶体管
技术领域
本发明属于 I GBT技术领域， 特别涉及一种双模式绝缘栅晶体管。 背景技术
RC-I GBT是将传统 IGBT背面集电区中引入 N+掺杂区域（N+集电区） ， 从而 使器件增加了一个反向电流通道。 RC-IGBT具有成本和性能上的优势， 在一些 领域可以替代传统 I GBT。 RC-IGBT最大的问题是导通时电压会出现 snap-back (以后简称 "回跳 " ) ,极大的限制了器件的应用。为了抑制回跳现象， RC-IGBT 通常需要保证相邻的 N+集电区的间距足够大， 但这样也造成芯片内部电流分 布不均匀， 影响器件的可靠性。 为此， 人们提出了 BIGT (双模式绝缘栅晶体 管） 结构， 将 RC-I GBT和传统 IGBT结构集成在同一芯片。 根据器件工作原理， 将芯片内部传统 IGBT区域称为引导区 （P i lo t IGBT区） 。 引导区主要作用是 在导通初期引导器件进入 IGBT模式， 从而避免了回跳的出现， 这使得 RC-IGBT 的设计更加自由， 可以为改善电流均勾性将相邻的 N+集电区间距缩小。
引导区的引入， 使得 RC-I GBT区的设计更加自由， N+集电区间距的设计不 要考虑抑制回跳的问题。 这使得设计自由度增加， 也有利于更充分地优化 RC-I GBT的整体性能。 所以双模式绝缘栅晶体管芯片中的 RC-I GBT区， N+集电 区间距可以适当减小以改善芯片内部的电流均匀性问题。 但双模式绝缘栅晶 体管并没有彻底改善芯片内部的电流均匀性， 实事上只有 RC-IGBT区的电流分 布较为均匀， 而引导区及附近 N+集电区电流均匀性仍然较差。 比如， 当双模 式绝缘栅晶体管工作于 I GBT模式时， 引导区中间区域电流密度比引导区边缘 及逆导区的电流密度要大很多。 当双模式绝缘栅晶体管工作于二极管模式时， 与引导区相邻的 N+集电区的电流密度较其它 N+集电区的电流密度大很多。 因 此双模式绝缘栅晶体管的器件结构仍然存在可靠性风险。
双模式绝缘栅晶体管可以使得 RC-IGBT的设计更加自由， 在一定程度上改 善了芯片内部电流的均匀性， 但双模式绝缘栅晶体管的引导区附近仍会出较 严重的电流集中问题， 导致芯片的可靠性较差， 主要表面为以下几个方面： 第一、 芯片内部不同区域温度差较大， 芯片内部由于温度梯度引入了较 大的应力导致器件的功率循环能力较差。
第二、 由于电流会集中在某些特点区域， 当器件承受电流过冲时会导致 芯片某些薄弱区域烧毁， 导致器件的抗电流过冲能力较差。
第三、 由于电流可会集中在某些特点区域， 导致器件的抗短路能力较差。 以上三个方面均会造成器件可靠性较差， 不利于器件长期安全工作。 发明内容
本发明所要解决的技术问题是提供一种双模式绝缘栅晶体管， 解决了现 有技术中双模式绝缘栅晶体管引导区尺寸太大， 导致引导区及其附近区域电 流集中较严重的技术问题。
为解决上述技术问题， 本发明提供了一种双模式绝缘栅晶体管， 包括逆 导区和引导区；
所述逆导区和所述引导区均包括 P+集电区， 漂移区和 M0S元胞区， 所述漂 移区均在所述 P+集电区的上方， 所述 M0S元胞区均在所述漂移区的上方； 所述逆导区还包括 N+集电区， 所述 N+集电区与所述 P+集电区相间分布； 所述引导区还包括分离区或低掺杂区， 所述分离区将所述引导区的 P+集 电区与所述逆导区的 P+集电区和所述 N+集电区隔离， 所述低掺杂区在所述引 导区的 P+集电区的上方。
进一步地， 所述逆导区和所述引导区均还可以设置 N+緩冲层， 所述逆导 区的 N+緩冲层在所述逆导区的 P+集电区或 N+集电区和所述逆导区的漂移区之 间， 所述引导区的 N+緩冲层在所述引导区的 P+集电区和所述引导区的漂移区 之间， 所述引导区的分离区将所述逆导区的 N+緩冲层和所述引导区的 N+緩冲 层隔离。
进一步地， 所述分离区的下方还有一绝缘体区， 所述绝缘体区位于硅衬 底与集电极金属层之间 , 通过调整所述绝缘体区的宽度使所述引导区的 N+緩 冲层与集电极金属电位隔离。
进一步地， 所述分离区为填充有绝缘体的沟槽。
进一步地， 所述引导区的 N+緩冲层掺杂浓度小于所述逆导区 N+緩冲层掺 杂浓度。
进一步地， 所述低掺杂区的掺杂浓度均小于所述引导区的 N+緩冲层和所 述引导区的 P+集电区的掺杂浓度。
本发明提供的双模式绝缘栅晶体管， 通过设置分离区或绝缘体沟槽， 增 加器件在 VDM0S模式时电子电流通道的电阻， 缩小双模式绝缘栅晶体管的引导 区尺寸。 使器件工作时电流在芯片内分布更均匀， 从而提高了器件整体的可 靠性。 另外， 通过设置低掺杂区， 降低引导区集电极 PN的开启电压， 从而缩 小双模式绝缘栅晶体管的引导区尺寸。 使器件工作时电流在芯片内分布更均 匀， 从而提高了器件整体的可靠性。 附图说明 图 1为本发明实施例 1提供的一种绝缘体逆导区一侧上方为 P+集电区的双 模式绝缘栅晶体管；
图 2为本发明实施例 1提供的一种绝缘体逆导区一侧上方为 N+集电区的双 模式绝缘栅晶体管；
图 3为本发明实施例 1提供的一种具有条形 N+集电区的双模式绝缘栅晶体 管的背面版图布局；
图 4为本发明实施例 1提供的一种具有圆形 N+集电区的双模式绝缘栅晶体 管的背面版图布局；
图 5为本发明实施例 2提供的一种绝缘体沟槽逆导区一侧为 P+集电区， 并 且分离区为沟槽的双模式绝缘栅晶体管；
图 6为本发明实施例 2提供的一种绝缘体沟槽逆导区一侧为 N+集电区， 并 且分离区为沟槽的双模式绝缘栅晶体管；
图 7为本发明实施例 3提供的一种没有 N+緩冲层， 且绝缘体沟槽逆导区一 侧为 P+集电区的双模式绝缘栅晶体管；
图 8为本发明实施例 3提供的一种没有 N+緩冲层， 绝缘体沟槽逆导区一侧 为 N+集电区的双模式绝缘栅晶体管；
图 9为本发明实施例 4提供的一种引导区的緩冲层掺杂浓度小于逆导区的 緩冲层掺杂浓度， 且低浓度緩冲层部分覆盖 P+集电区的双模式绝缘栅晶体管； 图 10为本发明实施例 4提供的一种引导区的緩冲层掺杂浓度小于逆导区 的緩冲层掺杂浓度， 且低浓度緩冲层完全覆盖 P+集电区的双模式绝缘栅晶体 管；
图 11为本发明实施例 5提供的一种引导区包含完全覆盖 P+集电区， 且具有 低掺杂区的双模式绝缘栅晶体管；
图 12为本发明实施例 5提供的一种引导区包含部分覆盖 P+集电区， 且具有 低掺杂区的双模式绝缘栅晶体管。 具体实施方式
参见图 1 , 本发明实施例提供的一种双模式绝缘栅晶体管， 包括逆导区和 引导区；
逆导区和引导区均包括 P+集电区， 漂移区和 M0S元胞区， 漂移区均在 P+集 电区的上方， M0S元胞区均在漂移区的上方；
逆导区还包括 N+集电区， N+集电区与 P+集电区相间分布；
引导区还包括分离区或低掺杂区， 分离区将引导区的 P+集电区与逆导区 的 P+集电区和 N+集电区隔离， 氐掺杂区在引导区的 P+集电区的上方。 本发明提供的双模式绝缘栅晶体管， 通过设置分离区或绝缘体沟槽， 增 加器件在 VDM0S模式时电子电流通道的电阻， 缩小双模式绝缘栅晶体管的引导 区尺寸。 使器件工作时电流在芯片内分布更均匀， 从而提高了器件整体的可 靠性。 另外， 通过设置低掺杂区， 降低引导区集电极 PN的开启电压， 从而缩 小双模式绝缘栅晶体管的引导区尺寸。 使器件工作时电流在芯片内分布更均 匀， 从而提高了器件整体的可靠性。
实施例 1 :
参见图 1、 图 2、 图 3和图 4 , 在本实施例中， 引导区包括分离区， 其基本 思路是将引导区的 N+緩冲层与逆导区的 N+緩冲层分离， 这也就是说让这两部 分緩冲层结构相互隔离， 如图 1和图 2所示。 分离区为未引入緩冲层掺杂的半 导体衬底， 通常与 N-漂移区掺杂浓度相同， 当然也可以适当引入少量杂质或 者将此区域加工成为电阻率大于 N-漂移区的半导体结构。
为了保证器件耐压， 在分离区下方制造一定尺寸的绝缘体区， 绝缘体区 位于半导体衬底与集电极金属层之间。 绝缘体的宽度要保证可以将所述 N+緩 冲层与集电极金属电位隔离 , 绝缘体区的作用是防止器件耐压时耗尽区边界 与集电极金属接触而发生穿通击穿。
本实施例中， 绝缘体靠近逆导区一侧上方可以设置一段 P+集电区 （如图 1 ) , 也可直接设置为 N+集电区 （如图 2 ) 。
背面版图布局以图 3和图 4为例， 通过将引导区的緩冲层隔离， 可以使引 导区两侧或四周的 N+集电区间距减小为与逆导区 N+集电区间距相当的水平。 这样可以使 N+集电区在整个芯片范围内均匀且规律地分布， 很大程度地改善 了电流均匀性。 这样当器件处于 VDM0S模式时， 引导区上方的电子电流必须流 过引导区的緩冲层（分布电阻为 Rbl )、 分离区处的低掺杂区（分布电阻为 Rd ) 以及逆导区的緩冲层 （分布电阻为 Rb2 ) 。 由于緩冲层之间为低掺杂区， 故 Rd»Rbl +Rb20 Rd的引入可以使得引导区不必拉大 P+集电区的宽度就足以抑制 器件的回跳， 从而使引导区的两侧或四周的 N+集电区间距缩小。 通过调整緩 冲层不连续处的低掺杂区宽度及掺杂浓度可以控制 Rd的大小 , 使得引导区的 宽度可以降低到同逆导区 P+集电区宽度相当的水平， 很大程度地改善了电流 均匀性问题。 通常緩冲层之间低掺杂区宽度越大， 掺杂浓度越低， Rd就会越 大， 引导区的宽度可以降得越小。 但 Rd的阻值并不是越大越好， 只要能够保 证器件不会出现回跳即可。
实施例 2:
本实施例提供的双模式绝缘栅晶体管与实施例 1的结构相似。 两者的不同 之处是， 实施例 2的分离区为填充有绝缘体的沟槽， N+緩冲层和集电区被一个 填充有绝缘体的沟槽所分离 （如图 5和图 6 ) 。 图示沟槽左侧緩冲层为引导区 緩冲层， 沟槽右侧緩冲层为逆导区緩冲层。
本实施例中， 绝缘体靠近逆导区一侧可以设置一段 P+集电区 （如图 5 ) , 也可直接设置为 N+集电区 （如图 6 ) 。
当器件处于 VDM0S模式时， 引导区上方的电子电流必须流过引导区的緩冲 层 （分布电阻为 Rbl ) 、 沟槽两侧及上方的低掺杂区 （总分布电阻为 Rd )以及 逆导区的緩冲层 （分布电阻为 Rb2 ) 。 由于沟槽两侧及上方为低掺杂区， 故 Rd»Rbl +Rb20 Rd的引入可以使得引导区不必拉大 P+集电区的宽度就足以抑制 器件的回跳， 从而使引导区的两侧或四周的 N+集电区间距缩小。 通过调整沟 槽的宽度及深度可以控制 Rd的大小， 使得引导区的宽度可以降低到同逆导区 P+集电区宽度相当的水平， 很大程度地改善了电流均匀性问题。 通常沟槽的 宽度及深度越大， Rd越大， 引导区的宽度可以降得越小。 但 Rd的阻值并不是 越大越好， 只要能够保证器件不会出现回跳即可。
实施例 3:
事实上， 不光 FS结构的双模式绝缘栅晶体管可以采用此方案， NPT结构的 双模式绝缘栅晶体管也可以改善电流均匀性。 实施例 3提出的逆导区的结构与 实施例 2的结构相似。 两者的不同之处是， 实施例 3的结构中没有 N+緩冲层结 构。
本实施例中， 绝缘体靠近逆导区一侧可以设置一段 P+集电区 （如图 7 ) , 也可直接设置为 N+集电区 （如图 8 ) 。
当器件处于 VDM0S模式时， 引导区上方的电子电流必须流过引导区的漂移 区 （分布电阻为 Rdl ) 、 沟槽两侧及上方的低掺杂区 （总分布电阻为 Rd ) 以及 逆导区 N+集电区上方的漂移区 （分布电阻为 Rd2 ) 。 Rd的引入可以使得引导区 不必拉大 P+集电区的宽度就足以抑制器件的回跳， 从而使引导区的两侧或四 周的 N+集电区间距缩小。 通过调整沟槽的宽度及深度可以控制 Rd的大小， 使 得引导区的宽度可以 P条低到同逆导区 P+集电区宽度相当的水平 , 很大程度地 改善了电流均匀性问题。 通常沟槽的宽度及深度越大， Rd越大， 引导区的宽 度可以降得越小。 但 Rd的阻值并不是越大越好， 只要能够保证器件不会出现 回 ii兆即可。
实施例 4:
本实施例中将引导区 N+緩冲层的掺杂浓度在保证器件耐压足够的前提下 作适当减小。 也就是说引导区的緩冲层掺杂浓度小于逆导区的緩冲层掺杂浓 度。
本实施例中， 引导区上方的低掺杂緩冲层可以部分覆盖 P+集电区 （如图 9 ) , 也可以全部覆盖 P+集电区 （如图 10 ) , 甚至将相邻的 N+集电区也全部或 部分覆盖。
当器件处于 VDM0S模式时， 引导区上方的电子电流必须流过引导区的低掺 杂緩冲层（分布电阻为 Rbl , 且阻值较大）和引导区的高掺杂緩冲层（分布电 阻为 Rb2 ) 。 由于低掺杂緩冲层的引入， 使得 Rbl+Rb2达到较大的水平。 另夕卜， 由于低掺杂緩冲层引入， 使得 P+集电区和 N+緩冲层所组成的 PN结开启电压降 低。 以上两方面的因素使得引导区不必拉大 P+集电区的宽度就足以抑制器件 的回跳， 从而使引导区的两侧或四周的 N+集电区间距缩小。 通过调整低掺杂 緩冲层的长度可以控制 Rb 1的大小， 使得引导区的宽度可以 P条低到同逆导区 P+ 集电区宽度相当的水平， 很大程度地改善了电流均匀性问题。 通常低掺杂緩 冲层的长度越大， Rbl越大， 引导区的宽度可以降得越小。 但 Rbl的阻值并不 是越大越好， 只要能够保证器件不会出现回跳即可。
实施例 5:
在本实施例中 , 低掺杂区的掺杂浓度均小于引导区的 N+緩冲层和引导区 的 P+集电区的掺杂浓度。
此低掺杂区可以为 P型， 也可以为 N型， 还可以既有 P区又有 N区。 对于既 有 P区又有 N区的情况， 需要保证 P型低掺杂区位于 P+集电区上方， 而 N型低掺 杂区位于 P型低掺杂区及 N+緩冲层之间。
本实施例中， 引导区的低掺杂区可以部分覆盖 P+集电区 （如图 11 ) , 也 可以全部覆盖 P+集电区 （如图 12 ) , 甚至将相邻的 N+集电区也全部或部分覆
。
在器件引导区的 N+緩冲层及 P+集电区之间引入低掺杂区 , 使得集电极 PN 结一侧或两侧有低掺杂半导体， 很大程度地降低了 PN结的开启电压。 使得引 导区不必拉大 P+集电区的宽度就足以抑制器件的回跳， 从而使引导区的两侧 或四周的 N+集电区间距缩小。 通过调整低掺杂区的浓度可以控制 PN结开启的 大小， 使得引导区的宽度可以降低到同逆导区 P+集电区宽度相当的水平， 很 大程度地改善了电流均匀性问题。 通常低掺杂区掺杂浓度较小， 集电结开启 所需的电压越小， 引导区的宽度可以降得越小。
本发明实施例提供的双模式绝缘栅晶体管， 可以使双模式绝缘栅晶体管 的引导区宽度从几百微米减小为几十微米， 极大地改善了双模式绝缘栅晶体 管芯片的电流均匀性， 提高了器件的可靠性。 具体可以改善器件的功率循环 能力、 抗电流过冲能力和抗短路能力等。
在实际工程中的版图方案可以有多种图形组成， 但均可以根据本发明实 施例提供的结构， 将部分 P+集电区隔离出来， 形成一个小尺寸引导区结构。 对于可以使得引导区 P+集电区宽度可以减小的方案本专利不再一一列举， 凡是采用特定技术方案使得引导区 P+集电区宽度减小以改善电流均匀性的方 案均属本专利的保护范围。
因此， 双模式绝缘栅晶体管的缺点在于引导区两侧或四周的 N+集电区间 距太大， 导致电流集中。 本专利的思想就是通过各种方法减小引导区的宽度， 也就是减小引导区两侧或四周 N+集电区间距， 这样能近一步改善双模式绝缘 栅晶体管的引导区的电流分布 , 近而提高器件的可靠性。
最后所应说明的是， 以上具体实施方式仅用以说明本发明的技术方案而 非限制， 尽管参照实例对本发明进行了详细说明， 本领域的普通技术人员应 当理解， 可以对本发明的技术方案进行修改或者等同替换， 而不脱离本发明 技术方案的精神和范围， 其均应涵盖在本发明的权利要求范围当中。

Claims

权 利 要 求
1、 一种双模式绝缘栅晶体管， 其特征在于， 包括逆导区和引导区； 所述逆导区和所述引导区均包括 P+集电区， 漂移区和 M0S元胞区， 所述漂 移区均在所述 P+集电区的上方， 所述 M0S元胞区均在所述漂移区的上方； 所述逆导区还包括 N+集电区， 所述 N+集电区与所述 P+集电区相间分布； 所述引导区还包括分离区或低掺杂区， 所述分离区将所述引导区的 P+集 电区与所述逆导区的 P+集电区和所述 N+集电区隔离， 所述低掺杂区在所述引 导区的 P+集电区的上方。
2、 根据权利要求 1所述的双模式绝缘栅晶体管， 其特征在于， 所述逆导 区和所述引导区均还可以设置 N+緩冲层， 所述逆导区的 N+緩冲层在所述逆导 区的 P+集电区或 N+集电区和所述逆导区的漂移区之间， 所述引导区的 N+緩冲 层在所述引导区的 P+集电区和所述引导区的漂移区之间， 所述引导区的分离 区将所述逆导区的 N+緩冲层和所述引导区的 N+緩冲层隔离。
3、 根据权利要求 2所述的双模式绝缘栅晶体管， 其特征在于， 所述分离 区的下方还有一绝缘体区， 所述绝缘体区位于硅衬底与集电极金属层之间， 通过调整所述绝缘体区的宽度使所述引导区的 N+緩冲层与集电极金属电位隔 离。
4、 根据权利要求 1所述的双模式绝缘栅晶体管， 其特征在于， 所述分离 区为填充有绝缘体的沟槽。
5、 根据权利要求 2所述的双模式绝缘栅晶体管， 其特征在于， 所述引导 区的 N+緩冲层掺杂浓度小于所述逆导区 N+緩冲层掺杂浓度。
6、 根据权利要求 2所述的双模式绝缘栅晶体管， 其特征在于， 所述低掺 杂区的掺杂浓度均小于所述引导区的 N+緩冲层和所述引导区的 P+集电区的掺 杂浓度。
PCT/CN2014/084086 2014-06-24 2014-08-11 一种双模式绝缘栅晶体管 WO2015196534A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/321,688 US20170148878A1 (en) 2014-06-24 2014-08-11 Bi-mode insulated gate transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410287757.3A CN104037208B (zh) 2014-06-24 2014-06-24 一种双模式绝缘栅晶体管
CN201410287757.3 2014-06-24

Publications (1)

Publication Number Publication Date
WO2015196534A1 true WO2015196534A1 (zh) 2015-12-30

Family

ID=51467914

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/084086 WO2015196534A1 (zh) 2014-06-24 2014-08-11 一种双模式绝缘栅晶体管

Country Status (3)

Country Link
US (1) US20170148878A1 (zh)
CN (1) CN104037208B (zh)
WO (1) WO2015196534A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768429B (zh) * 2017-10-27 2020-11-13 电子科技大学 一种具有混合导电模式的超结igbt器件
CN109920840B (zh) * 2019-03-20 2022-02-11 重庆邮电大学 一种具有L型SiO2隔离层的复合型RC-LIGBT器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515384A (zh) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 具有电荷载流子寿命降低设备的半导体器件
CN103855202A (zh) * 2012-12-06 2014-06-11 江苏物联网研究发展中心 Igbt及其元胞结构、以及igbt的形成方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4198251B2 (ja) * 1999-01-07 2008-12-17 三菱電機株式会社 電力用半導体装置およびその製造方法
JP4761644B2 (ja) * 2001-04-18 2011-08-31 三菱電機株式会社 半導体装置
JP2007184486A (ja) * 2006-01-10 2007-07-19 Denso Corp 半導体装置
DE102006050338B4 (de) * 2006-10-25 2011-12-29 Infineon Technologies Austria Ag Halbleiterbauelement mit verbessertem Speicherladung zu Dioden-Softness Trade-off
EP2086012A1 (en) * 2007-12-19 2009-08-05 ABB Technology AG Reverse-conducting insulated gate bipolar transistor and method for manufacturing such a reverse-conducting insulated gate bipolar transistor
EP2360717B1 (en) * 2009-12-09 2012-03-28 ABB Technology AG Method for producing a semiconductor device using laser annealing for selectively activating implanted dopants
JP2011249712A (ja) * 2010-05-31 2011-12-08 Toshiba Corp 半導体装置及びその製造方法
JP2012069579A (ja) * 2010-09-21 2012-04-05 Toshiba Corp 逆通電型の絶縁ゲート型バイポーラトランジスタ
CN103219370A (zh) * 2013-03-11 2013-07-24 电子科技大学 一种具有p浮空层电流栓的rc-igbt
CN104253153B (zh) * 2013-06-28 2017-09-15 无锡华润上华半导体有限公司 场截止型反向导通绝缘栅双极型晶体管及其制造方法
CN103383958B (zh) * 2013-07-17 2016-06-08 电子科技大学 一种rc-igbt器件及其制作方法
JP6119577B2 (ja) * 2013-11-26 2017-04-26 三菱電機株式会社 半導体装置
JP5920383B2 (ja) * 2014-03-03 2016-05-18 トヨタ自動車株式会社 半導体装置を製造する方法及び半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515384A (zh) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 具有电荷载流子寿命降低设备的半导体器件
CN103855202A (zh) * 2012-12-06 2014-06-11 江苏物联网研究发展中心 Igbt及其元胞结构、以及igbt的形成方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
M. RAHIMO ET AL.: "The Bi-mode Insulated Gate Transistor (BIGT) A Potential Technology for Higher Power Applications.", ISPSD 2009: 21ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S, 2009., 18 June 2009 (2009-06-18), pages 283 - 286, XP031485194 *
ZHANG WENLIANG ET AL.: "The negative differential resistance characteristics of an RC-IGBT and its equivalent circuit model.", JOURNAL OF SEMICONDUCTORS, vol. 35, no. 2, 28 February 2014 (2014-02-28), pages 024008.1 - 024008.5, XP055247104, ISSN: 1674-4926 *

Also Published As

Publication number Publication date
US20170148878A1 (en) 2017-05-25
CN104037208B (zh) 2017-09-26
CN104037208A (zh) 2014-09-10

Similar Documents

Publication Publication Date Title
JP7428211B2 (ja) 半導体装置
KR101745776B1 (ko) 전력용 반도체 소자
US10109725B2 (en) Reverse-conducting semiconductor device
WO2013035818A1 (ja) 半導体装置
EP2822038B1 (en) Insulated gate bipolar transistor
US10340373B2 (en) Reverse conducting IGBT
KR102206965B1 (ko) 트렌치형 전력 트랜지스터
JP6947915B2 (ja) Ｉｇｂｔパワーデバイス
CN105448961A (zh) 超结器件的终端保护结构
US9899374B2 (en) Semiconductor device
WO2012113818A2 (en) Power semiconductor device and method for manufacturing such a power semiconductor device
US10128340B2 (en) Power semiconductor device
US20150123164A1 (en) Power semiconductor device and method of fabricating the same
US8907374B2 (en) Insulated gate bipolar transistor
US10886371B2 (en) Silicon carbide semiconductor device
WO2015196534A1 (zh) 一种双模式绝缘栅晶体管
JP6299658B2 (ja) 絶縁ゲート型スイッチング素子
US20180350974A1 (en) Semiconductor device
JP2005150348A (ja) 半導体装置
WO2019134466A1 (zh) 横向绝缘栅双极晶体管及其制作方法
US20150221641A1 (en) Semiconductor device
JP2015188104A (ja) トレンチゲート型電力半導体素子
CN100377366C (zh) 半导体装置
JP5884772B2 (ja) 半導体装置
EP3223316A1 (en) Wide bandgap power semiconductor device and method for manufacturing such a device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14896117

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15321688

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14896117

Country of ref document: EP

Kind code of ref document: A1