CN104034928A - Multi-path signal source based on PCI and FPGA - Google Patents
Multi-path signal source based on PCI and FPGA Download PDFInfo
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Abstract
本发明公开了一种基于PCI和FPGA的多路信号源。本发明采用FPGA为中央控制单元,利用DDS技术实现正弦波频率的变化,通过PCI与上位机通信,该信号源以高精度D/A转换芯片为核心构成波形电路,使用电子模拟开关实现多路信号输出切换。输出的信号频率、幅值和偏置可调,并且精度达到了0.01%,满足了设计要求。
The invention discloses a multi-channel signal source based on PCI and FPGA. The invention adopts FPGA as the central control unit, uses DDS technology to realize the change of sine wave frequency, and communicates with the upper computer through PCI. The signal source uses a high-precision D/A conversion chip as the core to form a waveform circuit, and uses electronic analog switches to realize multiple Signal output switching. The output signal frequency, amplitude and offset are adjustable, and the precision reaches 0.01%, which meets the design requirements.
Description
技术领域technical field
本发明涉及数字技术领域,尤其涉及的是一种基于PCI和FPGA的多路信号源。The invention relates to the field of digital technology, in particular to a multi-channel signal source based on PCI and FPGA.
背景技术Background technique
信号源作为激励源可以仿真模拟各种测试信号以提供给被测设备,从而满足测量和各种实际需要,早期的频率合成技术运用一个频率基准由数字合成电路产生可变频率信号,这种方式工作不稳定、可靠性不高、不易调试。直接数字频率合成即DDS(DirectDigital Frequency Synthesis)作为一种全新的频率合成方法被业界所关注,它能够有效克服以上缺点。本发明中采用的FPGA和DDS相结合的方式产生信号源,输出了50路模拟信号。包括26路低压直流和正弦信号以及24路高压直流量信号,其中正弦信号输出频率0-8kHZ,,低压直流量为0-6V,高压直流量0-48V,信号源幅值均可调,输出精度达到0.01%。用PCI总线与上位机进行命令下发和数据数据上传,相对于USB总线来说,更稳定,速度也更快。As an excitation source, the signal source can simulate various test signals to provide to the equipment under test, so as to meet the measurement and various practical needs. The early frequency synthesis technology uses a frequency reference to generate variable frequency signals from digital synthesis circuits. This way The work is unstable, the reliability is not high, and it is not easy to debug. Direct Digital Frequency Synthesis, DDS (DirectDigital Frequency Synthesis), as a brand-new frequency synthesis method has attracted the attention of the industry, and it can effectively overcome the above shortcomings. The combination of FPGA and DDS adopted in the present invention generates a signal source, and outputs 50 analog signals. Including 26 channels of low-voltage DC and sinusoidal signals and 24 channels of high-voltage DC signals, among which the output frequency of sinusoidal signals is 0-8kHZ, the output frequency of low-voltage DC is 0-6V, and that of high-voltage DC is 0-48V. The amplitude of the signal source can be adjusted, and the output Accuracy reaches 0.01%. Using the PCI bus to send commands and upload data to the host computer is more stable and faster than the USB bus.
发明内容Contents of the invention
本发明所要解决的技术问题是针对现有技术的不足提供一种基于PCI和FPGA的多路信号源。本发明采用FPGA为中央控制单元,利用DDS技术实现正弦波频率的变化,通过PCI与上位机通信,该信号源以高精度D/A转换芯片为核心构成波形电路,使用电子模拟开关实现多路信号输出切换。输出的信号频率、幅值和偏置可调,并且精度达到了0.01%,满足了设计要求。The technical problem to be solved by the present invention is to provide a multi-channel signal source based on PCI and FPGA in view of the deficiencies of the prior art. The invention adopts FPGA as the central control unit, uses DDS technology to realize the change of sine wave frequency, and communicates with the upper computer through PCI. The signal source uses a high-precision D/A conversion chip as the core to form a waveform circuit, and uses electronic analog switches to realize multiple Signal output switching. The output signal frequency, amplitude and offset are adjustable, and the precision reaches 0.01%, which meets the design requirements.
本发明的技术方案如下:Technical scheme of the present invention is as follows:
一种基于PCI和FPGA的多路信号源,包括电源板卡、PCI卡、背板、模拟量卡、D/A转换、信号放大调理、多路开关选择模块、跟随滤波模块;电源板卡将输入的AC/DC转换为所需要的电压输出给背板,然后背板为电压模拟量卡供电,并且背板通过光纤与计算机上的PCI卡进行数据交换,完成命令下传与数据上传;所述模拟量卡包括模拟量低压卡和模拟量高压卡;模拟量低压卡输出0~6V直流模拟量信号以及频率可调的正弦信号。模拟量高压卡输出为0~48V,幅值可调的直流量;上位机将板卡号、通道号、幅值以及频率命令打包通过PCI总线发送给背板,背板通过判断不同的板卡号转发给不同的板卡,FPGA对接收到的上位机命令解析,解析后的命令将用于FPGA内部ROM的读写、高精度D/A芯片AD768的转换及多路选择开关ADG708的选通,低压板卡信号滤波后输出,高压板卡经过跟随增大其驱动电流能力,通过OPA454进行二次放大滤波后输出。A multi-channel signal source based on PCI and FPGA, including power supply board, PCI card, backplane, analog quantity card, D/A conversion, signal amplification and conditioning, multi-channel switch selection module, following filter module; the power supply board will The input AC/DC is converted into the required voltage and output to the backplane, and then the backplane supplies power to the voltage analog card, and the backplane exchanges data with the PCI card on the computer through the optical fiber to complete the command download and data upload; The above-mentioned analog quantity card includes an analog quantity low-voltage card and an analog quantity high-voltage card; the analog quantity low-voltage card outputs a 0-6V DC analog signal and a sinusoidal signal with an adjustable frequency. The output of the analog high-voltage card is 0-48V, and the DC flow with adjustable amplitude; the host computer packs the board number, channel number, amplitude and frequency commands and sends them to the backplane through the PCI bus, and the backplane judges different boards The number is forwarded to different boards, and the FPGA parses the received host computer commands. The parsed commands will be used for reading and writing of FPGA internal ROM, conversion of high-precision D/A chip AD768 and strobe of multi-channel selection switch ADG708 , The low-voltage board signal is filtered and output, and the high-voltage board is followed to increase its drive current capability, and the OPA454 is used for secondary amplification and filtering before output.
所述的基于PCI和FPGA的多路信号源,采用Xilinx公司spartan-3系列芯片XC3S400作为模拟量卡的主控芯片与外围电路进行连接The multi-channel signal source based on PCI and FPGA adopts the spartan-3 series chip XC3S400 of Xilinx Company as the main control chip of the analog quantity card to connect with the peripheral circuit
所述的基于PCI和FPGA的多路信号源,PCI卡采用了专用的接口芯片PCI9054实现接口模块的设计,PCI9054符合PCI本地规定2.2,数据宽度为32位。In the multi-channel signal source based on PCI and FPGA, the PCI card adopts a dedicated interface chip PCI9054 to realize the design of the interface module. The PCI9054 complies with PCI local regulation 2.2, and the data width is 32 bits.
所述的基于PCI和FPGA的多路信号源,PCI卡与背板之间采用光纤传输,光模块选择84M/S的OCM3443,分别置于PCI卡与背板完成数据的通信。For the multi-channel signal source based on PCI and FPGA, the optical fiber transmission is adopted between the PCI card and the backplane, and the optical module is selected as 84M/S OCM3443, which is respectively placed on the PCI card and the backplane to complete the data communication.
本发明利用FPGA和PCI总线技术,借助于DDS(直接数字合成)的原理思想,实现了多通道模拟信号源的系统设计,上位机控制信号的频率与幅值,信号源具有精度高、稳定性好以及多路同时输出等优点。The present invention utilizes FPGA and PCI bus technology, and by means of the principle of DDS (Direct Digital Synthesis), realizes the system design of multi-channel analog signal source, the frequency and amplitude of the host computer control signal, and the signal source has high precision and stability Good and multi-channel simultaneous output and other advantages.
附图说明Description of drawings
图1是系统总体方案框图;Figure 1 is a block diagram of the overall scheme of the system;
图2是OCM3443外围电路原理图;Figure 2 is a schematic diagram of the OCM3443 peripheral circuit;
图3是D/A转换电路原理图;Fig. 3 is a schematic diagram of a D/A conversion circuit;
图4是多路输出及信号保持电路原理图;Fig. 4 is a schematic diagram of a multi-channel output and signal holding circuit;
图5是二级放大电路原理图;Fig. 5 is a schematic diagram of a secondary amplifier circuit;
图6是低通滤波器原理图;Fig. 6 is a schematic diagram of a low-pass filter;
图7是信号源程序流程图;Fig. 7 is a flow chart of signal source program;
图8是高压卡直流量测试结果;Figure 8 is the test result of high voltage card DC flow;
图9是低压卡直流量;Figure 9 is the flow rate of the low pressure card;
图10(1.00009KHz)、图11(8.00001KHz)为可变频率的正弦波。Figure 10 (1.00009KHz) and Figure 11 (8.00001KHz) are sine waves with variable frequency.
具体实施方式Detailed ways
以下结合具体实施例,对本发明进行详细说明。The present invention will be described in detail below in conjunction with specific embodiments.
1系统总体设计方案1 overall design of the system
本发明采用模块化设计,每个模块即为一块单独的板卡,各个板卡功能明确且整体协调性好,系统包括电源板卡(模块)、PCI卡、背板、模拟量卡、D/A转换、信号放大调理、多路开关选择模块、跟随滤波模块。模块化设计便于设计人员调试和扩展,当功能板卡出现问题时,排故简单,易于维修。The present invention adopts a modular design, each module is a separate board, each board has clear functions and good overall coordination, and the system includes a power supply board (module), PCI card, backplane, analog quantity card, D/ A conversion, signal amplification and conditioning, multi-way switch selection module, following filter module. The modular design is convenient for designers to debug and expand. When there is a problem with the functional board, it is easy to troubleshoot and maintain.
电源板卡(模块)将输入的AC/DC转换为所需要的电压输出给背板,然后背板为电压模拟量卡供电,并且背板通过光纤与计算机上的PCI卡进行数据交换,完成命令下传与数据上传。本发明用了两块模拟量卡(模拟量低压卡和模拟量高压卡)来实现功能,采用Xilinx公司spartan-3系列芯片XC3S400作为模拟量卡的主控芯片与外围电路进行连接。The power board (module) converts the input AC/DC into the required voltage and outputs it to the backplane, and then the backplane supplies power to the voltage analog card, and the backplane exchanges data with the PCI card on the computer through the optical fiber to complete the command Download and upload data. The present invention uses two analog quantity cards (analog quantity low-voltage card and analog quantity high-voltage card) to realize the function, adopts Xilinx company spartan-3 series chip XC3S400 as the main control chip of the analog quantity card to connect with the peripheral circuit.
PCI卡采用了专用的接口芯片PCI9054实现接口模块的设计,PCI9054符合PCI本地规定2.2,数据宽度为32位,33M时钟输入时的突发传输速度最高达到132MHz/s,系统总体方案设计如图1所示。The PCI card adopts a dedicated interface chip PCI9054 to realize the design of the interface module. PCI9054 complies with PCI local regulation 2.2, the data width is 32 bits, and the burst transmission speed can reach up to 132MHz/s when the 33M clock is input. The overall system design is shown in Figure 1 shown.
本发明中模拟量低压卡输出0~6V直流模拟量信号以及频率可调的正弦信号。模拟量高压卡输出为0~48V,幅值可调的直流量。系统的工作原理是:上位机将板卡号、通道号、幅值以及频率命令打包通过PCI总线发送给背板,背板通过判断不同的板卡号转发给不同的板卡(本发明中高压卡为00,低压卡为01),FPGA对接收到的上位机命令解析,解析后的命令将用于FPGA内部ROM的读写、高精度D/A芯片AD768的转换及多路选择开关ADG708的选通,低压板卡信号滤波后输出,高压板卡经过跟随增大其驱动电流能力,通过OPA454进行二次放大滤波后输出。电源模块包括电源板卡(28V转成5V)和定制的直流电源(输出+55V、+28V、±9V),满足整个系统的电压需求。In the present invention, the analog low-voltage card outputs 0-6V DC analog signals and sinusoidal signals with adjustable frequency. The output of the analog high-voltage card is 0-48V, and the DC flow with adjustable amplitude. The working principle of the system is: the upper computer packs the board number, channel number, amplitude and frequency commands and sends them to the backplane through the PCI bus, and the backplane forwards them to different boards by judging different board numbers (high voltage in the present invention) The card is 00, the low-voltage card is 01), the FPGA parses the commands received from the host computer, and the parsed commands will be used for reading and writing of FPGA internal ROM, conversion of high-precision D/A chip AD768 and multi-channel selection switch ADG708 Strobe, the low-voltage board signal is filtered and output, and the high-voltage board is followed to increase its drive current capability, and the output is output after secondary amplification and filtering by OPA454. The power module includes a power board (28V converted to 5V) and a customized DC power supply (output +55V, +28V, ±9V) to meet the voltage requirements of the entire system.
2、硬件电路设计2. Hardware circuit design
2.1PCI接口设计2.1 PCI interface design
PCI卡插在计算机PCI插槽中,是连接上位机和背板的中间枢纽,采用专用的接口芯片PCI9054实现本地总线与PCI总线的连接,PCI9054的PCI端允许接入33M时钟,如用32位数据宽度,传输速率可达132MB/S[1]。PCI9054的本地端提供独立的地址线和数据线,数据宽度可配置为8位、16位或32位,允许接入0~50M本地时钟。PCI9054可配置为从方式,计算机通过PCI9054控制本地总线,完成命令的下发。也可配置成DMA方式,在这种方式下不需要CPU的参与,直接由PCI9054控制本地总线与计算机内存之间进行直接数据传输,本发明中采用DMA突发传输方式来满足上位机与PCI总线的高速数据传输。The PCI card is inserted in the PCI slot of the computer, and is the intermediate hub connecting the upper computer and the backplane. The connection between the local bus and the PCI bus is realized by using a dedicated interface chip PCI9054. Data width, transfer rate up to 132MB/S [1] . The local end of PCI9054 provides independent address lines and data lines, and the data width can be configured as 8 bits, 16 bits or 32 bits, allowing access to 0-50M local clocks. PCI9054 can be configured as a slave mode, and the computer controls the local bus through PCI9054 to complete the issuing of commands. It can also be configured as a DMA mode. In this mode, the participation of the CPU is not required, and the direct data transmission between the local bus and the computer memory is directly controlled by the PCI9054. In the present invention, the DMA burst transmission mode is used to meet the requirements of the upper computer and the PCI bus. high-speed data transmission.
2.2光电转换电路设计2.2 Photoelectric conversion circuit design
模拟信号要求高精度、低功耗传输,所以PCI卡与背板之间采用光纤传输,采用光纤传输的优点是通信容量大、损耗低、中继距离长并且保密性强。采用光电转换还可以抗干扰,提高可靠性,光模块选择84M/S的OCM3443分别置于PCI卡与背板完成数据的通信。OCM3443接口电平标准为TTL,与FPGA引脚电平兼容,所以直接与FPGA相接,极低功耗设计,其外围电路如图2所示。Analog signals require high-precision, low-power transmission, so optical fiber transmission is used between the PCI card and the backplane. The advantages of optical fiber transmission are large communication capacity, low loss, long relay distance, and strong confidentiality. The use of photoelectric conversion can also resist interference and improve reliability. The optical module chooses 84M/S OCM3443 and places it on the PCI card and the backplane to complete the data communication. OCM3443 interface level standard is TTL, which is compatible with FPGA pin level, so it is directly connected to FPGA, designed with extremely low power consumption, and its peripheral circuit is shown in Figure 2.
2.3信号源模块设计2.3 Signal source module design
2.3.1D/A转换电路设计2.3.1 D/A conversion circuit design
D/A转换电路的作用是把合成的信号波形数字量转化成模拟量,且D/A转换器的分辨率越高,输出波形的精度也就越高,通常8位的量化精度基本满足了精度要求,而实际的DAC输出需要考虑外界条件如温度对信号精度的影响,实际输出信号是无法达到DAC[2]芯片所描述的精度。因此为了达到指标要求的信号精度,本发明中选用16位分辨率的高精度AD768,AD768是电流/电压方式输出的高速模数转换器,数字量输入全部为1时满偏电流达到20mA,满足了驱动电流的要求,转换速率高达30MSPS,。设计电路如图3所示,IOUTA和IOUTB为AD768两个互补的电流输出端;根据芯片资料REFOUT为AD768的参考电压输出值为2.5V,参考电流为5mA,本发明采用AD768的双极性模式。该模式通过设置IBIPOLAR的值为最大反馈电流IFB的一半,使得输出电压的边界值对称。AD768的输出电流IOUTA与参考电流IBIPOLAR的关系式为:The function of the D/A conversion circuit is to convert the digital quantity of the synthesized signal waveform into an analog quantity, and the higher the resolution of the D/A converter, the higher the precision of the output waveform. Usually, the quantization precision of 8 bits is basically satisfied. Accuracy requirements, and the actual DAC output needs to consider the influence of external conditions such as temperature on the signal accuracy, the actual output signal cannot reach the accuracy described by the DAC [2] chip. Therefore in order to reach the signal accuracy of index requirement, select the high-precision AD768 of 16 resolutions in the present invention, AD768 is the high-speed analog-to-digital converter of current/voltage mode output, and the full-bias current reaches 20mA when digital quantity input is all 1, satisfies To meet the requirements of the drive current, the conversion rate is as high as 30MSPS. Design circuit as shown in Figure 3, I OUTA and I OUTB are two complementary current output ends of AD768; According to chip data REFOUT is the reference voltage output value of AD768 is 2.5V, and reference current is 5mA, the present invention adopts the bipolar of AD768 sexual pattern. This mode makes the boundary value of the output voltage symmetrical by setting the value of I BIPOLAR to half of the maximum feedback current I FB . The relationship between the output current I OUTA of the AD768 and the reference current I BIPOLAR is:
IOUTA=(DAC CODE/65536)×(IBIPOLAR×4) (1)I OUTA =(DAC CODE/65536)×(I BIPOLAR ×4) (1)
式(1)中,DAC CODE是16位数字输入码,在0~65535间变化。IBIPOLAR的值为5mA。因此输出电流IOUTA范围在0~20mA之间。输出电流经过运算放大器AD811缓冲放大后,第一级的输出端电压为VOUT1为-1~+1V,第二级运放的作用为反相放大电路,得到最后的输出电压为VOUT2为-4~+4V,第三级运放的作用为带基准电压的放大电路,得到最后的输出电压VOUT3为-0.7V~+7.3V,其中DAC CODE由输入的待转换数据值来决定。In formula (1), DAC CODE is a 16-bit digital input code, which changes between 0 and 65535. The value of I BIPOLAR is 5mA. Therefore, the range of the output current IOUTA is between 0 and 20mA. After the output current is buffered and amplified by the operational amplifier AD811, the output voltage of the first stage is V OUT1 which is -1~+1V, and the function of the second stage operational amplifier is an inverting amplifier circuit, and the final output voltage is V OUT2 which is - 4~+4V, the function of the third-stage operational amplifier is an amplifying circuit with a reference voltage, and the final output voltage V OUT3 is -0.7V~+7.3V, where the DAC CODE is determined by the input data value to be converted.
2.3.2模拟开关及信号保持电路设计2.3.2 Design of analog switch and signal holding circuit
本发明中模拟量较多,减少成本与空间考虑,采用模拟开关实现多通道的选择与切换,本发明选择了ADG708完成8选1模拟信号输出,ADG708为8通道电子开关,使能有效时,3位的地址线A0、A1、A2的8中二进制数组合控制要选择输出的模拟信号,经实验验证,信号通过模拟开关存在消弱的问题,所以必须设计信号保持电路保证模拟信号的稳定,并增大其驱动电流,以便于输出时能够有效驱动负载。图4为低压设计的模拟开关(A)以及跟随电路(B)。图4为低压模拟卡使用的电路,对于高压卡来说,D/A转换以及三级运放级联后的电压值远远不能达到要求,必须对开关输出的信号进行二次放大,放大电路如图5所示,运放芯片选择了OPA454,有0~100V和±50V两种供电方式,试验中发现OPA454不是轨到轨运放,所以其负端电压必须小于0V,本发明用-9V~+55V供电,放大倍数为:1+R119/R110,其中R119选用了12K电阻,R110为2K,所以电压增益为7倍,经放大后的理论最高电压达到49V,满足设计要求。In the present invention, there are many analog quantities, reducing cost and space considerations, and using an analog switch to realize multi-channel selection and switching. The present invention selects ADG708 to complete 8-to-1 analog signal output. ADG708 is an 8-channel electronic switch. When it is enabled, The combination of 8 binary numbers of the 3-bit address lines A0, A1, and A2 controls the analog signal to be selected for output. It has been verified by experiments that there is a problem of weakening the signal through the analog switch, so a signal holding circuit must be designed to ensure the stability of the analog signal. And increase its driving current so that it can effectively drive the load during output. Figure 4 shows the analog switch (A) and follower circuit (B) for a low-voltage design. Figure 4 shows the circuit used by the low-voltage analog card. For the high-voltage card, the voltage value after D/A conversion and three-stage operational amplifier cascading is far from meeting the requirements. The signal output by the switch must be amplified twice. As shown in Figure 5, OPA454 is selected as the operational amplifier chip, and there are two power supply modes of 0-100V and ±50V. During the test, it was found that OPA454 is not a rail-to-rail operational amplifier, so its negative terminal voltage must be less than 0V. In this invention, -9V ~+55V power supply, the amplification factor is: 1+R119/R110, in which R119 uses a 12K resistor, and R110 is 2K, so the voltage gain is 7 times, and the theoretical maximum voltage after amplification reaches 49V, which meets the design requirements.
信号的输入频率较低,为了有效避免高频信号的干扰,采用低通滤波器对输出信号进行处理,由集成运放构成的RC有源滤波器,输入阻抗高,输出阻抗低,可提供一定增益,截止频率可调,如图所示为低压板卡设计的滤波器,其中第一级电容接至输出端,引入了适量正反馈以改善幅频特性。高压模拟量卡与低压模拟量卡的区别是采用的集成运放芯片不同,高压卡采用OPA454构成滤波电路(图6)。The input frequency of the signal is low. In order to effectively avoid the interference of high-frequency signals, a low-pass filter is used to process the output signal. The RC active filter composed of an integrated operational amplifier has high input impedance and low output impedance, which can provide a certain The gain and cut-off frequency are adjustable. As shown in the figure, the filter is designed for a low-voltage board, in which the first-stage capacitor is connected to the output terminal, and an appropriate amount of positive feedback is introduced to improve the amplitude-frequency characteristics. The difference between the high-voltage analog card and the low-voltage analog card is that the integrated operational amplifier chip is different, and the high-voltage card uses OPA454 to form a filter circuit (Figure 6).
3、系统软件设计3. System software design
本发明利用DDS原理,用VHDL语言在FPGA内部利用IP Core例化波形ROM完成,其中正弦波的波形数据由MATLAB程序产生,将一个完整周期的正弦信号离散成28即256个抽样序列,经量化后存入波形存储器,然后通过寻址方式将波形数据以16位二进制数送给D/A完成数模转换。上位机点击打开设备即为信号源启动,然后FPGA根据内部的寄存器的信息,判断是直流量还是正弦波,假如是正弦波则通过DDS原理[4]计算出频率值对应的ROM地址,从ROM中取出数据送给DA进行输出,若是直流量则直接将对应内部寄存器的二进制数据送给D/A输出。每一路直流量或者正弦波都对应不同的独立地址,通过寻址的方式完成频率与幅值的调节。控制流程图如图7所示。The present invention utilizes the principle of DDS and uses VHDL language to complete the instantiation waveform ROM of IP Core inside the FPGA, wherein the waveform data of the sine wave is generated by the MATLAB program, and a complete cycle of the sine signal is discretized into 28 or 256 sampling sequences. After quantization, it is stored in the waveform memory, and then the waveform data is sent to the D/A as 16-bit binary numbers to complete the digital-to-analog conversion by addressing. The upper computer clicks to open the device to start the signal source, and then the FPGA judges whether it is a DC flow or a sine wave according to the information of the internal register. If it is a sine wave, the ROM address corresponding to the frequency value is calculated by the DDS principle [4] , and the ROM address is read from the ROM The data is taken out from the middle and sent to DA for output. If it is DC flow, the binary data corresponding to the internal register is directly sent to D/A for output. Each channel of DC flow or sine wave corresponds to a different independent address, and the adjustment of frequency and amplitude is completed by addressing. The control flow chart is shown in Figure 7.
4、测试结果分析4. Analysis of test results
用示波器与高精度万用表分别测试系统的输出波形与直流量电压值,得到了不同频率正弦波,不同幅值的直流量,图8为高压板输出的直流量,图9为低压板输出的直流量,图10(1.00009KHz)、图11(8.00001KHz)为可变频率的正弦波。由图可知得到的波形光滑,分辨率较高。其中在正弦波的输出中频率精确度达到0.01%,在直流量的输出中幅值精确度达到0.1%,满足设计要求。Use an oscilloscope and a high-precision multimeter to test the output waveform and DC voltage value of the system respectively, and obtain sine waves with different frequencies and DC values with different amplitudes. Figure 8 shows the DC output of the high-voltage board, and Figure 9 shows the DC output of the low-voltage board. Flow, Figure 10 (1.00009KHz) and Figure 11 (8.00001KHz) are sine waves with variable frequency. It can be seen from the figure that the obtained waveform is smooth and the resolution is high. Among them, the frequency accuracy reaches 0.01% in the sine wave output, and the amplitude accuracy reaches 0.1% in the DC flow output, meeting the design requirements.
应当理解的是,对本领域普通技术人员来说,可以根据上述说明加以改进或变换,而所有这些改进和变换都应属于本发明所附权利要求的保护范围。It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should belong to the protection scope of the appended claims of the present invention.
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