CN107449986B

CN107449986B - Multifunctional virtual instrument and data processing end thereof

Info

Publication number: CN107449986B
Application number: CN201710760227.XA
Authority: CN
Inventors: 王广君; 刘刚; 姜建金
Original assignee: China University of Geosciences
Current assignee: China University of Geosciences
Priority date: 2017-08-30
Filing date: 2017-08-30
Publication date: 2023-08-29
Anticipated expiration: 2037-08-30
Also published as: CN107449986A

Abstract

The invention discloses a multifunctional virtual instrument and a data processing end thereof, wherein the data processing end comprises a front-end signal conditioning circuit, a data acquisition module, a DDS signal generation source module, a DA waveform generation module, an upper computer communication module and other equipment communication modules, wherein an FPGA in the data acquisition module can convert acquired signals into functional signals with one or more functions of an oscilloscope, spectrum analysis, phase analysis, a frequency meter and a sweep generator, the DDS signal generation source module can generate signal sources with the frequency up to 200MHz, and the DA waveform generation module can generate special waveforms or synthesize any signal sources, so that the multifunction of the virtual instrument is realized.

Description

Multifunctional virtual instrument and data processing end thereof

Technical Field

The invention relates to the field of instrument equipment, in particular to the aspect of virtual instruments, and more particularly relates to a multifunctional virtual instrument and a data processing end thereof.

Background

Advances in instrumentation and modern testing technology have prompted the development of new-concept instrumentation-virtual instrumentation (Virtual Instrument, VI for short). The virtual instrument utilizes a computer to develop an instrument and is provided with an upper computer (such as a computer) and a data processing end, wherein the upper computer and the data processing end are generally in communication connection through a wired interface mode, the upper computer is used for displaying signals and realizing a user interface and interface operation, and the data processing end is used for collecting data or generating signals. The functions performed by the specific upper computer and the data processing end are different according to the specific virtual instrument. If the virtual instrument is an oscilloscope, the data processing end is used for collecting and conditioning the measured signals, the upper computer displays the conditioned signals, a control panel is also displayed on the upper computer, and after the user adjusts the control panel, the upper computer can adjust the signal size and sampling frequency and the like represented by the unit distances of the horizontal and vertical coordinates when the waveform is displayed; if the virtual instrument is a signal generator, the upper computer can display the current signal, and the upper computer is also provided with a control panel, after the user adjusts the control panel, different signals can be selectively generated, and then the data processing end generates different signals.

However, the existing virtual instruments are all virtual instruments with single functions, such as oscilloscopes, sweep generators, signal generators, and the like, and one data terminal is not yet capable of completing the processing of multiple functions.

Disclosure of Invention

The invention aims to solve the technical problem that a multifunctional virtual instrument and a data processing end thereof are provided for solving the technical defect that a data terminal can finish processing of multiple functions at present.

According to one aspect of the present invention, in order to solve the technical problem, the present invention provides a data processing end of a multifunctional virtual instrument, including:

the front-end signal conditioning circuit is used for conditioning input signals of at least two input channels;

the data acquisition module comprises two AD converters and an FPGA, wherein the two AD converters are respectively connected between the front-end signal conditioning circuit and the FPGA so as to perform analog-to-digital conversion on signals conditioned by the two input channels, and the converted signals are transmitted to the FPGA to be processed into functional signals with one or more functions of an oscilloscope, spectrum analysis, phase analysis, a frequency meter and a sweep generator;

the DDS signal generation source module is connected with and controlled by the FPGA to generate a first type signal source with a frequency higher than a preset frequency and transmit the first type signal source to the FPGA;

the DA waveform generation module comprises a DA conversion unit and a power amplification unit, wherein the DA conversion unit is connected with and controlled by the FPGA to generate a preset type signal with the frequency not higher than the preset frequency or synthesize a specified type signal according to the preset type signal, then the preset type signal or the specified type signal is subjected to digital-to-analog conversion, and the power amplification unit is connected with the DA conversion unit to amplify the power of the signal subjected to digital-to-analog conversion and transmit the amplified signal to the FPGA to be used as a preset type signal source or a specified type signal source respectively;

the upper computer communication module is connected with the FPGA to transmit the functional signals to the upper computer for display;

and the other equipment communication module is connected with the FPGA to transmit the first type signal source, the preset type signal source or the fixed type signal source to other equipment connected with the FPGA as the signal source of the other equipment.

Preferably, in the data processing terminal of the present invention, the two AD converters are a first AD converter and a second AD converter, the sampling clocks are all from the FPGA and have 180 ° phase difference, and the input ends of the first AD converter and the second AD converter are respectively connected to a first output end and a second output end, where the first output end and the second output end are respectively two output ends of the two input channels in the front-end signal conditioning circuit;

a controlled switch is connected between the second AD converter and the second output end, two input ends of the controlled switch are respectively connected with the first output end and the second output end, and the output end of the controlled switch is connected with the second AD converter;

the controlled switch is controlled by the FPGA and has two open and close states: in the first opening and closing state, the first AD converter acquires a signal of the first output end to perform analog-to-digital conversion, and the second AD converter acquires a signal of the second output end to perform analog-to-digital conversion; in the second switching state, the first AD converter and the second AD converter acquire signals of the first output end to perform analog-to-digital conversion so as to be combined into a sampled signal in the FPGA.

Preferably, in the above data processing terminal of the present invention, the front-end signal conditioning circuit includes two sets of implementation circuits corresponding to each input channel respectively, each set of implementation circuits including a voltage-controlled attenuation circuit with adjustable gain, a fixed gain amplifying circuit, a single-ended differential circuit, a digital-to-analog conversion circuit for controlling an output voltage range of the voltage-controlled attenuation circuit, and a dc offset adjusting circuit for eliminating dc offset in an output signal of the voltage-controlled amplifying circuit;

the input end of the voltage-controlled attenuation circuit is connected with one of the input channels, the control end of the voltage-controlled attenuation circuit is connected with the digital-to-analog conversion circuit, the output end of the voltage-controlled attenuation circuit is connected with the input end of the fixed gain amplification circuit, and the output end of the fixed gain amplification circuit is connected with the input end of the single-end-to-differential circuit.

Preferably, in the data processing terminal of the present invention, the upper computer communication module is a wireless WIFI transmission module, and the wireless WIFI transmission module is implemented by using STM32F103 and WM-G-MR 09.

Preferably, the data processing terminal of the present invention further includes a power module, configured to convert ac mains supply into dc power, and supply power to the data processing terminal.

Preferably, in the data processing terminal of the present invention, the two AD converters are implemented by one chip MXT2002.

Preferably, in the above data processing end of the present invention, the DDS signal generating source module includes a DA converter, so that the first type signal source is an analog signal.

According to another aspect of the present invention, in order to solve the technical problem, the present invention further provides a multifunctional virtual instrument, which includes a data processing end as any one of the above.

The multifunctional virtual instrument and the data processing end thereof can integrate one or more functions of an oscilloscope, spectrum analysis, phase analysis, a frequency meter and a sweep generator with the functions of a signal generator, and have the advantages of centralization by utilizing virtual instrument equipment and cost reduction. Furthermore, the multifunctional virtual instrument and the data processing end thereof have two acquisition modes of high-speed acquisition and low-speed acquisition, and the upper limit of the sampling rate of the sampling chip can be broken through in the high-speed acquisition mode, so that the sampling rate is higher.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic diagram of the simulation of the working state of a multifunctional virtual instrument of the present invention;

FIG. 2 is a schematic circuit diagram of a preferred embodiment of the data processing end of the multifunction virtual machine of the present invention;

FIG. 3 is a schematic circuit diagram of the front-end signal conditioning circuit of FIG. 2 in accordance with the present invention;

FIG. 4 is a schematic diagram of a two-stage amplification circuit of VCA824+OPA847 of FIG. 3 in accordance with the invention;

FIG. 5 is a schematic diagram of the voltage output circuit of DAC8043 of FIG. 3 in accordance with the invention;

FIG. 6 is a schematic diagram of the ADR430 reference source and OPA656 DC offset circuits of FIG. 3 in accordance with the invention;

fig. 7 is a schematic circuit diagram of another embodiment of the front-end signal conditioning circuit and data acquisition module of fig. 1 according to the present invention.

Detailed Description

For a clearer understanding of technical features, objects and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating the operation state simulation of the multifunctional virtual instrument according to the present invention. The multifunctional virtual instrument in the embodiment comprises a notebook computer 2 and a data processing end 1. The notebook computer 2 is connected with the data processing end 1 through WIFI to realize data communication, and the two devices 3 are respectively used for generating signal sources to be sent to the data processing end 1 and displaying signals generated by the data processing end 1 so as to simulate the real working condition of the multifunctional virtual instrument, and the two devices can be respectively realized through an oscilloscope and a signal generator.

Referring to fig. 2, a schematic circuit diagram of a preferred embodiment of the data processing end of the multifunctional virtual instrument of the present invention is shown. In this embodiment, the data processing end includes a front end signal conditioning circuit 11, a data acquisition module 12, a DDS signal generation source module 13, a DA waveform generation module 14, a host computer communication module 15, and other device communication modules (not shown in fig. 2). The data acquisition module 12 includes a first AD converter and a second AD converter, the host communication module 15 includes an ARM chip and a WIFI module, and the notebook computer 2 includes a WIFI module communicatively connected to the host communication module 15.

The data processing end is provided with two input channels, namely a first channel and a second channel, and the front-end signal conditioning circuit 11 is used for conditioning input signals of the two input channels. The front-end signal conditioning circuit 11 may be implemented by an analog circuit, where when two input channels have input signals, the front-end signal conditioning circuit 11 conditions the two input signals, respectively, and when there is only one input signal, the front-end signal conditioning circuit conditions only one input signal. When the multifunctional virtual instrument of the embodiment needs to be used as any one or more functions of an oscilloscope, spectrum analysis, phase analysis, a frequency meter and a sweep generator, signals to be measured of other devices need to be collected as input signals, and at this time, the front-end signal conditioning circuit 11 and the data collection module 12 work.

The front-end signal conditioning circuit 11 is provided with two groups of implementation circuits corresponding to each input channel respectively, each group of implementation circuits comprises a voltage-controlled attenuation circuit with adjustable gain, a fixed gain amplifying circuit, a single-end rotating differential circuit, a digital-to-analog conversion circuit for controlling the output voltage range of the voltage-controlled attenuation circuit and a direct-current deviation adjusting circuit for eliminating direct current shunting in the output signal of the voltage-controlled amplifying circuit, the input end of each voltage-controlled attenuation circuit is connected with one input channel, the control end is connected with the digital-to-analog conversion circuit, the output end is connected with the input end of the fixed gain amplifying circuit, and the output end of the fixed gain amplifying circuit is connected with the input end of the single-end rotating differential circuit. Wherein the voltage-controlled attenuation circuit adopts a gain voltage-controlled operational amplifier VCA824 with the bandwidth of 320MHz as a core, and controls the output voltage V thereof through a 12-bit digital-to-analog conversion DAC8043 chip _g The gain of the voltage-controlled gain amplifying circuit is adjustable by changing the voltage between-1V and 1V, the fixed gain amplifying circuit is realized by adopting an ultralow noise operational amplifier OPA847 with a gain bandwidth of 3.9GHz, meanwhile, the direct current component introduced by a power supply is eliminated by designing an OPA656 direct current bias circuit, and then an analog signal meeting the input range of a high-speed AD converter C is obtained after a single-ended signal is converted into a differential signal by an ultrahigh-speed differential line driver LMH6555, and each AD converter takes a group of differential signals as input for sampling. The circuits of each part of the front-end signal conditioning circuit are shown in fig. 4, 5 and 6.

The first AD converter (analog-to-digital conversion) and the second AD converter are respectively connected between the front-end signal conditioning circuit 11 and the FPGA122, so as to perform analog-to-digital conversion on the signals conditioned by the first channel and the second channel, and transmit the converted signals to the FPGA122 to process into functional signals with one or more functions of an oscilloscope, spectrum analysis, phase analysis, a frequency meter, and a sweep generator. The first AD converter and the second AD converter may be two independent AD converter conversion chips, and may be implemented by one chip having a plurality of groups of AD converter conversion functions, and in this embodiment, the latter is used, and the MXT2002 is selected as the chip.

In this embodiment, the first AD converter and the second AD converter collect signals independently, and the collected signals are processed independently by the FPGA122. In another embodiment of the present invention, referring to fig. 7, the sampling clocks of the first AD converter and the second AD converter are both from PLL (Phase Locked Loop) of the FPGA122 and are 180 ° out of phase, and the input ends of the first AD converter and the second AD converter are respectively connected to the first output end and the second output end, where the first output end and the second output end are respectively two output ends of two input channels in the front-end signal conditioning circuit. A controlled switch 123 is connected between the second AD converter and the second output terminal, two input terminals of the controlled switch 123 are respectively connected to the first output terminal and the second output terminal, and the output terminal is connected to the second AD converter. The controlled switch 124 is controlled by the FPGA, and has two open and close states to sample the high speed and low speed states, respectively: in the first open-close state, the first AD converter obtains the signal at the first output end to perform analog-to-digital conversion, and the second AD converter obtains the signal at the second output end to perform analog-to-digital conversion, which is the same as the independent sampling and independent processing in the above embodiment, and belongs to the low-speed sampling state; in the second switching state, the first AD converter and the second AD converter acquire signals at the first output end and perform analog-to-digital conversion to combine the signals into a sampled signal in the FPGA122, at this time, no signal input or no signal input at the second channel is invalid, since the sampling clock phase difference of the two paths of AD converters is 180 °, in each clock period, the two times of data acquisition are equivalent, the acquired data are transmitted to the FPGA122, and in the FPGA122, the sampling of the data at the sampling speed of the AD converter performed by one AD converter chip is equivalent, so that the sampling frequency of the existing equipment is greatly improved, and the system belongs to the high-speed acquisition state.

After the first AD converter and the second AD converter perform analog-to-digital conversion, the converted signals are transmitted to the FPGA122, and the FPGA122 processes the signals into functional signals of one or more functions of an oscilloscope, a spectrum analysis, a phase analysis, a frequency meter, and a sweep generator according to a user's needs, and the functional signals are sent to the notebook computer 2 by the upper computer communication module 15, and are displayed on the notebook computer 2 according to the settings of the notebook computer 2.

The upper computer communication module 15 is a wireless WIFI transmission module, and the wireless WIFI transmission module is realized by adopting STM32F103 (ARM) and WM-G-MR 09. In order to improve the transmission rate, the wireless module MR09 is controlled by the ARM embedded processor to be connected with an SDIO interface mode, wherein: the wireless module MR09 is connected with the ARM embedded processor in a mode of selecting an SDIO interface, wherein a2 nd pin DATA0 of the MR09 is connected with a PC8 pin of the STM 32; the 1 st pin DATA1 of MR09 is connected with the PC9 pin of STM 32; the 9 th pin DATA2 of MR09 is connected to the PC10 pin of STM 32; the 8 th pin DATA3 of MR09 is connected to the PC11 pin of STM 32; pins 3, 6 and 9 of the MR09 are grounded; the 5 th pin of MR09 is connected with a 3.3v power supply; the 4 th pin CLK of MR09 is connected with the PC12 pin of STM 32; the 7 th pin CMD of MR09 is connected with the PD2 pin of STM 32; PA0-PA15 of STM32 are connected with 23-38 pins of EP1C12T240 respectively; the PB2 pin of STM32 is grounded through a resistor R1; the PB12 pin of STM32 is connected with the base electrode of the PNP triode Q1 through R2; the PB12 pin of STM32 is connected with the base electrode of the PNP triode Q2 through R3; the emitter of Q1 is connected with a 3.3v power supply; the emitter of Q2 is connected with a 3.3v power supply; the collector of the Q1 is connected with the collector of the PNP triode Q2; pins PD0 and PD1 of STM32 are grounded; pins PD0 and PD1 of STM32 are connected through an active crystal oscillator; the BOOT0 pin of STM32 is connected to a 3.3v power supply through a key Down1 and a resistor R4; the BOOT0 pin of STM32 is grounded through a resistor R6; the NRST pin of STM32 is connected to a 3.3v power supply via R5; the NRST pin of STM32 is grounded through a capacitor C1; the NRST pin of STM32 is grounded through a key Reset 1; VBAT, VDD_1, VDD_2, VDD_3, VDD_4 and VDD_A pins of STM32 are connected to a 3.3v power supply; the vss_1, vss_2, vss_3, vss_4, and vss_a pins of STM32 are grounded.

The FPGA122 completes the registration of the data transmitted by the AD converter, the internal register of the FPGA122 transmits the data to the ARM end for DMA transmission without excessive intervention of the CPU, the FPGA122 reads the status register of the DMA, invokes the DMA transmission channel, and continuously and intermittently transmits the data packets with the fixed word length until the specified DMA data transmission is completed. The FPGA122 is connected to the ARM processor external gpio a, and can selectively use 8 or 16 data lines, each bit of data corresponding to a synchronous clock. The FPGA122 is mainly composed of a controllable clock PLL, an AD converter acquisition controller, a shift register, a data memory RAM, and a function control logic circuit. The shift register mainly converts serial commands into parallel commands, and controls a clock end and an acquisition end. The RAM memory is mainly circularly shifted and stored according to the rising edge of the clock, after the central controller shifts and stores one bit of data, the RAM automatically points to the data bit corresponding to the next clock and transmits the data bit to the GPIO_A end of the ARM core controller until the counter part value of the clock generator reaches 1460, and the waiting for a zero clearing signal is suspended. After finishing the registering and packaging of the length data, the CPU sends the length data to the wireless terminal AP, feeds back a zero clearing signal to the FPGA122 counter, and sequentially circulates. After the ARM end writes the DMA drive and configures the bus channel mode, a channel request and a loop detection mode are set, and once the corresponding channel has a data transmission interrupt request, the DMA data transmission is started, and an I/O port feedback signal for the specified count value is reached to the FPGA122 end. The system selects a cyclon WIFI module WM-G-MR09, adopts Marvell 8686 as a main chip, and provides SDIO and GSPI interfaces. The system selects the SDIO interface of the STM32F103 singlechip and the WIFI chip as the interface for directly carrying out data interaction between the WIFI module and the MCU. The pins SD1_CLK, SD1_CMD, SD 1_DATA0-SDA_DATA3 are respectively connected with corresponding pins of the SDIO distribution area of the central controller. By combining the WIFI module and the Lwip control theory, the main transmission process of wireless data is as follows: firstly, a client sends a request for reading data signal frame header information, and after receiving the client information, a server sends the data signal frame header information. And secondly, the client sets and initializes the size of a data frame buffer area according to the frame header information and corresponding zone bit information. And then the server sends the real data information, and the client receives the real data information and encapsulates the real data information in a corresponding mailbox length mechanism.

DDS (Direct Digital Synthesizer) signal generating source module 13 is connected to and controlled by FPGA122 to generate a first type signal source with a frequency higher than a preset frequency and transmit the first type signal source to FPGA122, and the signal generated by DDS signal generating source module 13 may be a square wave, a sine wave, a triangle wave, etc., and the generated waveform is transmitted to FPGA122. The DDS signal generating source module 13 uses the AD9959 to output a high-frequency signal source up to 200MHz, and includes a DA converter therein, so that the first type signal source is an analog signal.

The DA waveform generating module 14 includes a DA converting unit and a power amplifying unit, where the DA converting unit 14 is connected to and controlled by the FPGA122 to generate a preset type signal with a frequency not higher than the preset frequency or synthesize a specified type signal according to the preset type signal, and then digital-to-analog convert the preset type signal or the specified type signal, and the power amplifying unit is connected to the DA converting unit to amplify the power of the digital-to-analog converted signal and transmit the amplified signal to the FPGA to be used as a preset type signal source or a specified type signal source respectively.

The DDS signal generating source module 13 and the DA waveform generating module 14 are both for outputting waveforms as signal sources to other devices, one generates high frequency, the other generates special waveforms and synthesizes arbitrary waveforms within a certain frequency, the functions are different, for what waveforms are generated, the user sets parameters on the notebook computer 2, the notebook computer 2 transmits the parameters to the ARM through the WIFI module of the upper computer communication module and then to the FPGA122, and the FPGA122 controls the corresponding modules to generate waveforms.

The other device communication module is connected with the FPGA122 to transmit the first type signal source, the preset type signal source or the fixed type signal source to other devices connected with the FPGA122 as signal sources of other devices, and in this embodiment, one of the two devices 3 is adopted as the other device, and a wired connection mode is adopted for connection.

In this embodiment, the data processing end further has a power module, and the power module converts ac mains supply into dc power to supply power to the data processing end of the multifunctional virtual instrument.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. A data processing terminal of a multifunctional virtual instrument, comprising:

the front-end signal conditioning circuit comprises two groups of implementation circuits which respectively correspond to each input channel, wherein each group of implementation circuits comprises a voltage-controlled attenuation circuit with adjustable gain, a fixed gain amplifying circuit, a single-ended differential circuit, a digital-to-analog conversion circuit for controlling the output voltage range of the voltage-controlled attenuation circuit and a direct-current offset adjusting circuit for eliminating direct-current offset in the output signal of the voltage-controlled amplifying circuit;

the input end of the voltage-controlled attenuation circuit is connected with one of the input channels, the control end of the voltage-controlled attenuation circuit is connected with the digital-to-analog conversion circuit, the output end of the voltage-controlled attenuation circuit is connected with the input end of the fixed gain amplification circuit, and the output end of the fixed gain amplification circuit is connected with the input end of the single-ended differential circuit;

the two AD converters are respectively a first AD converter and a second AD converter, sampling clocks are all from the FPGA and have 180-degree phase difference, the input ends of the first AD converter and the second AD converter are respectively connected with a first output end and a second output end, and the first output end and the second output end are respectively two output ends of the two input channels in the front-end signal conditioning circuit;

the controlled switch is controlled by the FPGA and has two open and close states: in the first opening and closing state, the first AD converter acquires a signal of the first output end to perform analog-to-digital conversion, and the second AD converter acquires a signal of the second output end to perform analog-to-digital conversion; in the second switching state, the first AD converter and the second AD converter acquire signals of the first output end to perform analog-to-digital conversion so as to be combined into a sampled signal in the FPGA;

2. The data processing terminal according to claim 1, wherein the upper computer communication module is a wireless WIFI transmission module, and the wireless WIFI transmission module is implemented by using STM32F103 and WM-G-MR 09.

3. The data processing terminal of claim 1, further comprising:

and the power supply module is used for converting alternating current commercial power into direct current and supplying power for the data processing end.

4. The data processing terminal of claim 1, wherein the two AD converters are provided in one chip MXT2002.

5. The data processing terminal according to claim 1, wherein the DDS signal generating source module includes a DA converter therein, so that the first type signal source is an analog signal.

6. A multifunctional virtual machine comprising a data processing end according to any one of claims 1-5.