CN108761239A - A kind of time domain and frequency domain combined tester - Google Patents
A kind of time domain and frequency domain combined tester Download PDFInfo
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- CN108761239A CN108761239A CN201810552357.9A CN201810552357A CN108761239A CN 108761239 A CN108761239 A CN 108761239A CN 201810552357 A CN201810552357 A CN 201810552357A CN 108761239 A CN108761239 A CN 108761239A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/16—Spectrum analysis; Fourier analysis
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/16—Spectrum analysis; Fourier analysis
- G01R23/165—Spectrum analysis; Fourier analysis using filters
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- G09B23/00—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
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- G09B23/187—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for measuring instruments
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Abstract
The present invention relates to a kind of time domain and frequency domain combined testers, belong to electronic measuring instrument technical field, the LABVIEW software communications that FPGA master controllers pass through communication interface and host computer, High-Speed Double-Channel signal acquisition module, High-Speed Double-Channel signal generating module and memory are connect with FPGA master controllers respectively, and FPGA master controllers are connect by data/address bus with ARM microprocessor；Low speed multi-channel signal acquiring module, low speed multi channel signals occur module, motor drive interface and external data communication interface and are connect respectively with ARM microprocessor, first signal conditioning circuit is connect with low speed multi-channel signal acquiring module, and second signal modulate circuit occurs module with low speed multi channel signals and connect.The present invention realizes the multiple functions such as data acquisition, signal generator, filter, frequency characteristic analyzer, spectrum analysis, oscillograph, and can one-dimensional time-domain signal be mapped to two-dimensional time-frequency plane, reflects the time-frequency combination feature of non-stationary signal comprehensively.
Description
Technical field
The present invention relates to electronic measuring instrument technical fields, more particularly to a kind of time domain and frequency domain combined tester.
Background technology
With the continuous development of computer technology and observation and control technology, the concept of instrument is not limited solely to bulky, work(
Single, the higher traditional instrument of cost of energy, but there is a kind of completely new instrument concept --- virtual instrument.This concept
Occur bringing landmark influence to the development of science and technology and industrial production, at the same for Scientific Research in University Laboratory equipment update with
And the raising of experimental teaching quality brings dawn, a series of is asked for effectively solve that colleges and universities bring since experimental resources are in short supply
Topic provides method and approach.
In test, research and adjustment electronic circuit and equipment, to measure some parameters of circuit, such as frequency response is made an uproar
Sonic system number etc. is often provided using analog oscilloscope and meets the electric signals of certain technical conditions, but traditional analog oscilloscope
General frequency band is wider, has a single function, and Devices to test used pumping signal in actual operation can not be simulated, although and empty
Quasi- technical device is widely used, but in time-frequency domain electronic measuring technology field, there is presently no about utilization
Virtual instrument reacts the measuring apparatus of the time varying spectrum characteristic of non-stationary signal.
Invention content
Based on this, it is necessary to be mapped to two-dimensional time-frequency plane for by one-dimensional time-domain signal, reflect non-stationary letter comprehensively
Number time-frequency combination Characteristic Problem, a kind of time domain and frequency domain combined tester is provided.
To solve the above problems, the present invention takes the following technical solution：
A kind of time domain and frequency domain combined tester, including the host computer of LABVIEW softwares, High-Speed Double-Channel signal acquisition are installed
Module, High-Speed Double-Channel signal generating module, FPGA master controllers, memory, ARM microprocessor, low speed multi channel signals are adopted
Collect module, the first signal conditioning circuit, low speed multi channel signals and module, second signal modulate circuit, motor driving interface occurs
With external data communication interface；
The FPGA master controllers pass through the LABVIEW software communications of communication interface and the host computer, the high speed pair
Channel signal acquisition module, the High-Speed Double-Channel signal generating module and the memory respectively with the FPGA master controllers
Connection, the FPGA master controllers are connect by data/address bus with the ARM microprocessor；
Module, the motor drive occur for the low speed multi-channel signal acquiring module, the low speed multi channel signals
Interface and the external data communication interface are connect with the ARM microprocessor respectively, first signal conditioning circuit and institute
The connection of low speed multi-channel signal acquiring module is stated, with the low speed multi channel signals module occurs for the second signal modulate circuit
Connection；
The FPGA master controllers control the High-Speed Double-Channel signal acquisition module to input according to preset sample rate
The first analog voltage signal carry out data acquisition, and gathered data be uploaded to the host computer carry out waveform parameter and measure point
Analysis and display, the Wave data and high-speed data control command that the FPGA master controllers are sent also according to the host computer, general
The Wave data is stored in the memory, and is controlled the High-Speed Double-Channel according to the high-speed data control command and believed
Number occur module generate analog voltage pumping signal；
The low speed multi-channel signal acquiring module receives the second mould after first signal conditioning circuit conditioning
Quasi- voltage signal, and exported to the ARM microprocessor after second analog voltage signal is carried out analog-to-digital conversion, it is described
Digital voltage signal is uploaded to the host computer and is shown and analyzed by ARM microprocessor；
The low speed multi channel signals occur module and export mould according to the low speed data control command that the host computer is sent
Quasi- voltage control signal, the analog voltage control signal export after the conditioning of second signal modulate circuit to external equipment.
Compared with prior art, time domain and frequency domain combined tester proposed by the invention has the following technical effects：
(1) method that FPGA firmware programs use hardware and software combination, it is specific using user-defined hardware realization
Data acquisition function, efficiency is than software higher.Meanwhile hardware circuit is for various control instructions and dumb, and
It realizes that control function workload is larger with hardware circuit in FPGA, therefore uses the soft cores of NIOS II, it will be user-defined
Hardware is connected to as peripheral hardware on processor core, realizes hardware-accelerated purpose, the software and hardware division of labor is clear, collaborative design, most
It improves to limits system performance and improves design efficiency；
(2) patterned programming language greatly facilitates the Programming of the tester of Non-computer Majors, by
This quick graphical programs language, the tester of professional domain can fast construction test platform, carry out test job,
Time and cost have been saved, efficiency is improved；
(3) data acquisition, signal generator, filter, frequency characteristic analyzer, spectrum analysis, oscillograph etc. are realized
Multiple functions, and one-dimensional time-domain signal can be mapped to two-dimensional time-frequency plane, reflect the time-frequency combination of non-stationary signal comprehensively
Feature has many advantages, such as that friendly interface, performance are stable, operable maintainability is strong.
Description of the drawings
Fig. 1 is the illustrative view of functional configuration of the time domain and frequency domain combined tester of the present invention；
Fig. 2 is that the one of signal acquisition of time domain and frequency domain combined tester high speed double-channel signal acquisition module of the invention is logical
The illustrative view of functional configuration in road；
Fig. 3 is that the time domain and frequency domain combined one of signal of tester high speed double-channel signal generation module of the present invention occurs to lead to
The illustrative view of functional configuration in road.
Specific implementation mode
The present invention provides a kind of time domain and frequency domain combined tester, which utilizes the advantageous resource of computer and powerful
Operational capability is soft integrated by traditional discrete instrumental function of hardware, designs virtual system, one-dimensional time-domain signal is mapped to two
The time-frequency plane of dimension reflects the time-frequency combination feature of non-stationary signal comprehensively, has and is easy to carry about with one, is conducive to improve the quality of teaching
And the features such as level.Technical scheme of the present invention is described in detail below in conjunction with attached drawing and preferred embodiment.
In one of the embodiments, as shown in Figure 1, a kind of time domain and frequency domain combined tester of the present invention includes being equipped with
The host computer 1 of LABVIEW softwares, High-Speed Double-Channel signal acquisition module 2, High-Speed Double-Channel signal generating module 3, FPGA master controls
It is device 4 processed, memory (SRAM) 5, ARM microprocessor 6, low speed multi-channel signal acquiring module 7, the first signal conditioning circuit 8, low
Module 9, second signal modulate circuit 10, motor driving interface 11 and external data communication interface 12 occur for fast multi channel signals,
Wherein, FPGA master controllers 4 pass through the LABVIEW software communications of communication interface and host computer 1, High-Speed Double-Channel signal acquisition mould
Block 2, High-Speed Double-Channel signal generating module 3 and memory 5 are connect with FPGA master controllers 4 respectively, and FPGA master controllers 4 pass through
Data/address bus is connect with ARM microprocessor 6；Module 9, electricity occur for low speed multi-channel signal acquiring module 7, low speed multi channel signals
Motivation driving interface 11 and external data communication interface 12 are connect with ARM microprocessor 6 respectively, the first signal conditioning circuit 8 with
Low speed multi-channel signal acquiring module 7 connects, and second signal modulate circuit 10 occurs module 9 with low speed multi channel signals and connect.
Specifically, in the present embodiment, High-Speed Double-Channel signal acquisition module 2 and High-Speed Double-Channel signal generating module 3
It is controlled by FPGA master controllers 4, is respectively used to waveform parameter measurement and analog voltage pumping signal generates, as shown in Figure 1, high
It includes that channel occurs for two signals that module 3, which occurs, for fast double-channel signal, is that DA waveforms generate CH_1 and DA waveforms generation CH_ respectively
2, DA waveforms generate CH_1 and DA waveforms generation CH_2 and can individually work, and the two can also work at the same time；High speed bilateral
Road signal acquisition module 2 include two signal sampling channels, be respectively AD acquisition CH_3 and AD acquisition CH_4, AD acquire CH_3 and
AD acquisitions CH_4 can individually work, and the two can also work at the same time.
FPGA master controllers 4 control High-Speed Double-Channel signal acquisition module 2 to the first of input according to preset sample rate
Analog voltage signal carries out data acquisition, and gathered data is uploaded to host computer 1 and carries out waveform parameter measurement analysis and display,
FPGA master controllers 4 are by the LABVIEW software communications of communication interface and host computer 1, control command and ginseng in the present embodiment
Number is assigned by LABVIEW host computers, and order return value and data are also handled by LABVIEW softwares.High-Speed Double-Channel is believed
Number acquisition module 2 is used as high-speed AD sampling system, when the first analog voltage signal to input carries out data acquisition, input
First analog voltage signal is decayed by passive attenuation network, and 1 times, 1/10,1/20 attenuation degree, direct current or friendship may be selected
Flow coupled modes.Because passive attenuation network is pure resistance network, for back-end circuit the output resistance of this network compared with
Greatly, meanwhile, these resistance are likely to be coupled in operational amplifier circuit, it is therefore desirable to realize that impedance converts using voltage follower.Resistance
Input signal can only be fixed the decaying of gear in network, in order to carry out finer control, data acquisition to input signal
Card is further decayed or is amplified to input signal using controllable gain amplifier.Analog-digital converter is defeated using differential signal
Enter, can be configured as single ended input, and it is positive voltage signal that single ended input pattern, which can only measure voltage value, to measure negative electricity
Press signal, it is necessary to input signal be moved to the midpoint of input range, while the data exported will also be translated, using addition
Circuit may be implemented.But the method for using voltage shifts must assure that the precision of translation, difficulty is higher, therefore data collecting card
In use the mode of Differential Input, single-ended signal is converted into differential signal and is input in ADC chips, can both be measured in this way
Positive voltage signal also can measure negative voltage signal, while the data format exported need not deviate, and directly export the complement of two's two's complement
?.
Meanwhile the Wave data that sends also according to host computer 1 of FPGA master controllers 4 and high-speed data control command, by wave
Graphic data stores in the memory 5, and controls High-Speed Double-Channel signal generating module 3 according to high-speed data control command and generate mould
Quasi- voltage excitation signals.High-Speed Double-Channel signal generating module 3 is used as high speed D/A signal generating system, the waveform number of host computer 1
It is sent in the memory 5 of FPGA master controllers 4 according to by communication interface, under the control of host computer 1, FPGA master controllers 4
Wave data is sent to DAC chip according to the rate of preset requirement, the rate and sample rate of transmission, which determine, generates waveform
Frequency generates the current waveform signal of corresponding frequencies.High-speed DAC chip is mostly current-output type, and is difference output, exports energy
Power is stronger, and due to being difference output, is easy to obtain ambipolar voltage signal by resistance.Filter circuit is to disappear
Except quantization error design, using passive filter circuit.Finally output signal is amplified to suitable model using high speed amplifier
It encloses, such as setting voltage range is -15V to+15V.Due to the output resistance very little of amplifier, will appear when exporting high-frequency signal
Impedance mismatching and lead to signal reflection phenomenon, it is therefore desirable to amplifier output end series resistance carry out impedance matching, such as connect
50 Europe resistance carry out impedance matching, and it is 50 Europe or so to make output impedance.
Low speed multi-channel signal acquiring module 7 and low speed multi channel signals occur module 9 and are controlled by microcontroller, use respectively
In outputting and inputting for analog controller, it is connect with the simulation input output channel of external equipment.Low speed multi channel signals occur
Module 9 needs that output voltage range is adjusted to a certain range using second signal modulate circuit 10, such as adjusts to 0V to 5V,
Fan-out capability is not less than 20mA, and low speed multi-channel signal acquiring module 7 then needs to use the first signal conditioning circuit 8 by input
Voltage range is adjusted to the suitable range to match with microcontroller, such as adjusts to 0V to 3.3V.In addition, for stabilization
Property consider, external interface is kept apart with signal conditioning circuit using linear isolator, to prevent external electromagnetic noise pair
Microcontroller impacts.Low speed multi-channel signal acquiring module 7 receives the second mould after the conditioning of the first signal conditioning circuit 8
Quasi- voltage signal simultaneously will by output to ARM microprocessor 6, ARM microprocessor 6 after the second analog voltage signal progress analog-to-digital conversion
Digital voltage signal is uploaded to host computer 1 and is shown and analyzed.
Microcontroller in the present invention mainly controls multichannel low speed signal and occurs and the acquisition of multichannel low speed signal, and upper
Machine 1 completes the transmission of slow channels information, and controls the coupled modes in high speed acquisition channel, signal attenuation multiple, programme-controlled gain
Amplification factor.Microcontroller is connected to FPGA master controllers 4 by 8 parallel-by-bit buses, by FPGA master controllers 4 and communication interface
Realize the communication of microcontroller and host computer 1.
Preferably, in order to improve the message transmission rate of host computer 1 and acquisition channel, the channels adjustment AD and DA are paid the utmost attention to
Data transmission, FPGA master controllers 4 are communicated by USB interface with host computer 1, such as are realized by USB-CY68013 chips
USB interface realizes the communication between FPGA master controllers 4 and LABVIEW host computers 1, transmits the data of high-speed channel, at this point,
Microcontroller is connected to FPGA master controllers 4 by 8 parallel-by-bit buses, is generated with signal in control high-speed channel data acquisition same
When, the usb communication of microcontroller and host computer 1 is realized by the interface of FPGA master controllers 4 and USB-CY68013.
Low speed multi channel signals occur module 9 and export analog voltage according to the low speed data control command that host computer 1 is sent
Signal is controlled, analog voltage controls signal and exported to external equipment after the conditioning of second signal modulate circuit 10.Low speed is mostly logical
Road signal acquisition module 7 and low speed multi channel signals occur module 9 and are controlled by microcontroller, for analog voltage signal reception and mould
Quasi- voltage control signal output, including 8 road low speed A D interfaces and 8 road low speed DA interfaces, can external various industrial instruments.
Motor driving interface 11 is used for output motor drive signal, can be used for driving direct current by external power amplification circuit
Motor, alternating current generator, stepper motor etc. can select the motor type of control to be configured by host computer 1.
External data communication interface 12 is used to be communicated with external equipment, including common various communication interfaces, such as CAN
Bus interface, RS232 interface, RS485 interfaces, IIC interfaces, Serial Peripheral Interface (SPI) (SPI), UART Universal Asynchronous Receiver Transmitter (UART) connect
Mouth, gpib interface and network interface etc..
The time domain and frequency domain combined tester that the present embodiment is proposed has the following technical effects：
(1) method that FPGA firmware programs use hardware and software combination, it is specific using user-defined hardware realization
Data acquisition function, efficiency is than software higher.Meanwhile hardware circuit is for various control instructions and dumb, and
It realizes that control function workload is larger with hardware circuit in FPGA, therefore uses the soft cores of NIOS II, it will be user-defined
Hardware is connected to as peripheral hardware on processor core, realizes hardware-accelerated purpose, the software and hardware division of labor is clear, collaborative design, most
It improves to limits system performance and improves design efficiency；
(2) patterned programming language greatly facilitates the Programming of the tester of Non-computer Majors, by
This quick graphical programs language, the tester of professional domain can fast construction test platform, carry out test job,
Time and cost have been saved, efficiency is improved；
(3) data acquisition, signal generator, filter, frequency characteristic analyzer, spectrum analysis, oscillograph etc. are realized
Multiple functions, and one-dimensional time-domain signal can be mapped to two-dimensional time-frequency plane, reflect the time-frequency combination of non-stationary signal comprehensively
Feature has many advantages, such as that friendly interface, performance are stable, operable maintainability is strong.
As a kind of specific embodiment, as shown in Fig. 2, High-Speed Double-Channel signal acquisition module 2 includes two signals
Acquisition channel, each signal sampling channel include input end of analog signal 13, coupling unit 14, voltage follower 15, first
Programme-controlled gain unit 16, single-ended transfer difference circuit 17 and analog-digital converter 18, and input end of analog signal 13, coupling unit
14, voltage follower 15, the first programme-controlled gain unit 16, single-ended transfer difference circuit 17, analog-digital converter 18 and FPGA main controls
Device 4 is sequentially connected.Specifically, input end of analog signal 13 is the port for inputting analog signal；Direct current can be used in coupling unit 14
Coupled modes or AC coupled mode, dc-couple mode refer to leading directly to, and do not remove AC compounent, and AC coupled mode refers to
It is coupled by capacitance, eliminates DC component；Voltage follower 15 utilizes comparator/operational amplifier, keeps input terminal voltage
Do not change with rear class circuit load and changes；First programme-controlled gain unit 16 carries out gain amplification by software, poor using a pair
Analog signals are divided to control its gain amplification factor, gain amplification factor can be put analog signals in -11dB between 45dB
The big amplitude to most suitable measurement；Since selected high-speed AD converter 18 inputs for differential signal, it is therefore desirable to single-ended turn
The single-ended analog amount signal of front end is converted to differential signal by difference channel 17.Preferably, coupling unit 14 utilizes passive attenuation
The analog voltage signal that network inputs input end of analog signal 13 is decayed, such as 1 times, 1/10,1/20 decaying may be selected
Degree, using 2 grades of π type attenuator circuits, every grade is decayed 4.9 times, and input, output-resistor is 50 Ω, is set by the way that two double-poles are double
Resistance attenuator is realized in relay switching.
In the present embodiment, the first analog voltage signal is inputted by analog input end 13, by coupling unit 14, electricity
After pressing follower 15, the first programme-controlled gain unit 16 and single-ended transfer difference circuit 17 to handle, the voltage signal for being converted into difference is sent
To analog-digital converter 18, analog-digital converter 18 converts analog signals to digital quantity signal, and FPGA master controllers 4 acquire modulus
The digital signal that converter 18 exports.In Fig. 2 coupling unit 14 with relay control break-make, to selection signal via channel
It is dc-couple channel or AC coupled channel.Signal decaying selection is mainly used to control the decaying of signal amplitude, makes to be measured
Signal is within the acquisition range of analog-digital converter 18.Voltage follower 15 has the characteristics that high input impedance, low output impedance,
Its role is to the isolation to front stage circuit, prevent late-class circuit from loading the influence to front stage circuits signal.First program-controlled increasing
In the range of the effect of beneficial unit 16 is that the Signal Regulation after prime decays is measured to most suitable analog-digital converter 18,
Gain-adjusted may range from -9dB to 35dB.Because the analog-digital converter 18 of high speed is generally differential signal input, single
The effect of end slip parallel circuit 17 is to convert single-ended measured signal to by mirror image the signal of difference, send to modulus and turn
The differential signal input of parallel operation 18 measures.FPGA master controllers 4 can control analog-to-digital conversion according to the sample rate of user setting
Device 18 acquires, and gathered data is uploaded to host computer 1 by communication interface and carries out waveform parameter measurement analysis and display.
As a kind of specific embodiment, as shown in figure 3, High-Speed Double-Channel signal generating module 3 includes two signals
Occur channel, each signal occur channel include digital analog converter 19, electric current turn voltage amplifier circuit 20, filter circuit 21,
Second programme-controlled gain unit 22, amplifying stage 23 and analog signal output 24, FPGA master controllers 4, digital analog converter 19, electric current
Turn voltage amplifier circuit 20, filter circuit 21, the second programme-controlled gain unit 22, amplifying stage 23 and analog signal output 24 successively
Connection.In the present embodiment, host computer 1 is by by communication interface, such as USB communication interface is to lower computer FPGA main control
Device 4 sends Wave data and control command, and lower computer FPGA master controller 4 stores Wave data in sram, according to user
It works in the control command control digital analog converter 19 of host computer setting, digital quantity signal is converted simulation letter by digital analog converter 19
Number by modulate circuit signal is handled after output.Detailed process is：Digital analog converter 19 exports two-way current signal,
Electric current turns the voltage signal that voltage amplifier circuit 20 converts the two-way current signal to by load resistance difference, then will be electric
Pressure signal is converted into single-ended voltage signal；Filter circuit 21 is filtered single-ended voltage signal, the effect master of filter circuit 21
It is smooth waveform, eliminates the ladder after digital analog converter 19 converts, it is preferable that filter circuit 21 is passive filter circuit,
Such as the passive Bezier filter circuit of seven ranks can be used and be filtered, so that output waveform signals are more smooth；Second journey
It is mainly the amplification factor for controlling signal to control gain unit 22, its amplitude is adjusted to the numerical value of user setting；Amplifying stage 23 is logical
Amplitude amplification is crossed, improves the driving capability of output, analog signals are after scaling circuit in the same direction from analog signal output
24 output of end, analog signal output 24 is the port of analog signal output.
As a kind of specific embodiment, motor driving interface 11 includes PWM output signal interface and encoder interfaces.
Specifically, PWM output signal interface is drawn by the PWM output channels of the advanced timer of microcontroller, can at most be generated
Three pairs of complementary PWM waveforms with dead zone are controlled for three phase electric machine.Host computer 1 can control the way of output of PWM, including output to lead to
Road number, output polarity control, exports Power MOSFET, carrier frequency, modulation waveform etc..Consider for stability, PWM outputs
Signaling interface is isolated the waveform signal of output using optical coupling isolator, to prevent external electromagnetic noise from being caused to circuit
Harmful effect.Motor driving interface 11 in present embodiment can provide the pwm signal of 3.3V, and when driving motor needs external
Corresponding power amplification circuit.
Encoder interfaces are isolated using optical coupling isolator, and carry out waveform shaping using Schmidt trigger.Coding
Device is counted to be realized using the counter inside microcontroller, is counted as clock signal actuation counter using the encoder pulse signal of input
Number calculates the encoder pulse number counting down within a certain period of time, actual tachometer value is conversed further according to the line number of encoder.
Each technical characteristic of embodiment described above can be combined arbitrarily, to keep description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of time domain and frequency domain combined tester, which is characterized in that host computer (1), high speed including being equipped with LABVIEW softwares are double
Channel signal acquisition module (2), High-Speed Double-Channel signal generating module (3), FPGA master controllers (4), memory (5), ARM are micro-
Mould occurs for processor (6), low speed multi-channel signal acquiring module (7), the first signal conditioning circuit (8), low speed multi channel signals
Block (9), second signal modulate circuit (10), motor driving interface (11) and external data communication interface (12)；
The FPGA master controllers (4) pass through the LABVIEW software communications of communication interface and the host computer (1), the high speed
Double-channel signal acquisition module (2), the High-Speed Double-Channel signal generating module (3) and the memory (5) respectively with it is described
FPGA master controllers (4) connect, and the FPGA master controllers (4) are connect by data/address bus with the ARM microprocessor (6)；
Module (9) occurs for the low speed multi-channel signal acquiring module (7), the low speed multi channel signals, the motor drives
Mobile interface (11) and the external data communication interface (12) are connect with the ARM microprocessor (6) respectively, first signal
Modulate circuit (8) is connect with the low speed multi-channel signal acquiring module (7), the second signal modulate circuit (10) with it is described
Low speed multi channel signals occur module (9) and connect；
The FPGA master controllers (4) control the High-Speed Double-Channel signal acquisition module (2) to defeated according to preset sample rate
The first analog voltage signal entered carries out data acquisition, and gathered data is uploaded to the host computer (1) and carries out waveform parameter
Measure analysis and display, the Wave data and high-speed data that the FPGA master controllers (4) send also according to the host computer (1)
The Wave data is stored in the memory (5) by control command, and controls institute according to the high-speed data control command
It states High-Speed Double-Channel signal generating module (3) and generates analog voltage pumping signal；
The low speed multi-channel signal acquiring module (7) receives second after first signal conditioning circuit (8) improves
Analog voltage signal, and exported to the ARM microprocessor (6) after second analog voltage signal is carried out analog-to-digital conversion,
Digital voltage signal is uploaded to the host computer (1) and is shown and analyzed by the ARM microprocessor；
The low speed multi channel signals occur module (9) and are exported according to the low speed data control command that the host computer (1) is sent
Analog voltage controls signal, and the analog voltage control signal exports after second signal modulate circuit (10) conditioning to outside
Equipment.
2. a kind of time domain and frequency domain combined tester according to claim 1, which is characterized in that the High-Speed Double-Channel signal is adopted
It includes two signal sampling channels to collect module (2), and each signal sampling channel includes input end of analog signal (13), coupling
Unit (14), voltage follower (15), the first programme-controlled gain unit (16), single-ended transfer difference circuit (17) and analog-digital converter
(18)；
The input end of analog signal (13), the coupling unit (14), the voltage follower (15), the first program-controlled increasing
Beneficial unit (16), the single-ended transfer difference circuit (17), the analog-digital converter (18) and the FPGA master controllers (4) are successively
Connection.
3. a kind of time domain and frequency domain combined tester according to claim 2, which is characterized in that
The coupling unit (14) believes the analog voltage that the input end of analog signal (13) inputs using passive attenuation network
Number decay.
4. a kind of time domain and frequency domain combined tester according to claims 1 to 3 any one, which is characterized in that the high speed
It includes that channel occurs for two signals that module (3), which occurs, for double-channel signal, and it includes digital analog converter that channel, which occurs, for each signal
(19), electric current turns voltage amplifier circuit (20), filter circuit (21), the second programme-controlled gain unit (22), amplifying stage (23) and mould
Quasi- signal output end (24)；
The FPGA master controllers (4), the digital analog converter (19), the electric current turn voltage amplifier circuit (20), the filter
Wave circuit (21), the second programme-controlled gain unit (22), the amplifying stage (23) and the analog signal output (24) according to
Secondary connection.
5. a kind of time domain and frequency domain combined tester according to claim 4, which is characterized in that
The filter circuit (21) is passive filter circuit.
6. a kind of time domain and frequency domain combined tester according to claims 1 to 3 any one, which is characterized in that
The motor driving interface (11) includes PWM output signal interface and encoder interfaces.
7. a kind of time domain and frequency domain combined tester according to claim 6, which is characterized in that
The PWM output signal interface is isolated the waveform signal of output using optical coupling isolator.
8. a kind of time domain and frequency domain combined tester according to claim 6, which is characterized in that
The encoder interfaces are isolated using optical coupling isolator, and carry out waveform shaping using Schmidt trigger.
9. a kind of time domain and frequency domain combined tester according to claims 1 to 3 any one, which is characterized in that
The external data communication interface (12) includes CAN interface, RS232 interface, RS485 interfaces, IIC interfaces, serial
Peripheral Interface, UART Universal Asynchronous Receiver Transmitter interface, gpib interface and network interface.
10. a kind of time domain and frequency domain combined tester according to claims 1 to 3 any one, which is characterized in that
The FPGA master controllers (4) are communicated by USB interface with the host computer (1).
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| CN110109853A (en) * | 2019-04-04 | 2019-08-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing (DAP) device and method |
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