CN114995586A - Multi-channel signal source based on digital logic chip - Google Patents
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Abstract
The application relates to the field of signal sources, and provides a multi-channel signal source based on a digital logic chip, which comprises: a signal generation module; the signal generating module comprises a digital logic chip and a plurality of converter chips, wherein the digital logic chip comprises a plurality of paths of parallel multi-bit direct digital frequency synthesis DDS modules; the digital logic chip determines the phase increment value of the multipath parallel signals; inputting the phase increment value into a multi-path parallel multi-bit direct digital frequency synthesis DDS module, and outputting multi-path serialized high-speed digital signals through a high-speed transmission interface; the converter chip outputs a plurality of analog signals with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement under the control of the digital logic chip. The multi-channel signal source based on the digital logic chip provided by the embodiment of the application realizes the output of multi-channel signals with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement.
Description
Technical Field
The application relates to the field of signal sources, in particular to a multi-channel signal source based on a digital logic chip.
Background
In the field of test and measurement, signal sources are widely used, and the test of many systems requires the signal sources as excitation or reference; however, a conventional signal source generally generates one signal by one device, and when multiple signal sources are needed, multiple devices are needed to be built together, which results in increased cost and complicated system structure. Meanwhile, the early frequency synthesis technology is unstable in work, not easy to debug, low in precision and low in reliability.
Disclosure of Invention
The application provides a multichannel signal source based on a digital logic chip, and aims to output a plurality of analog signals with independent frequencies, continuously adjustable phases and frequency resolution and phase resolution meeting preset precision requirements.
The application provides a multi-channel signal source based on a digital logic chip, which comprises a signal generating module;
the signal generation module comprises a digital logic chip and a plurality of converter chips, and the digital logic chip is connected with the converter chips, wherein the digital logic chip comprises a plurality of paths of parallel multi-bit direct digital frequency synthesis (DDS) modules;
the digital logic chip determines a phase increment value of a plurality of paths of parallel signals according to the initial phase and the phase variation of the plurality of paths of parallel signals; inputting the phase increment value into the multi-path parallel multi-bit direct digital frequency synthesis DDS module, and outputting multi-path serialized high-speed digital signals through a high-speed transmission interface of the digital logic chip;
and the converter chip performs digital-to-analog conversion on the plurality of paths of serialized high-speed digital signals under the control of the digital logic chip, and outputs a plurality of paths of analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement.
According to the multi-channel signal source based on the digital logic chip, the multi-channel signal source based on the digital logic chip further comprises a display control module; the digital logic chip comprises a Field Programmable Gate Array (FPGA), the converter chip comprises a digital-to-analog conversion (DA) chip, the multi-path parallel multi-bit direct digital frequency synthesis (DDS) module comprises 16 paths of parallel 48-bit direct digital frequency synthesis (DDS) modules, and the multi-path parallel signals comprise 16 paths of parallel signals;
the display control module is connected with the signal generation module and is used for displaying the state information of the signal generation module;
the FPGA determines a phase increment value of the 16 paths of parallel signals according to the initial phase and the phase variation of the 16 paths of parallel signals; inputting the phase increment value into the 16-channel parallel 48-bit direct digital frequency synthesis DDS module, and outputting a plurality of paths of serialized high-speed digital signals through a high-speed transmission interface of the field programmable gate array FPGA;
and the digital-to-analog conversion DA chip performs digital-to-analog conversion on a plurality of paths of serialized high-speed digital signals under the control of the field programmable gate array FPGA, and outputs a plurality of paths of analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement.
According to the multi-channel signal source based on the digital logic chip, when the 16-channel parallel 48-bit direct digital frequency synthesis DDS module adjusts the phase corresponding to the frequency of the 16-channel parallel signal, the phase variation of the current moment is calculated according to the newly output phase; and on the basis of the phase variation of the current moment, updating the phase increment values of the changes together, and continuously accumulating the phases of other moments except the current moment according to the original phase increment values of the phases so as to ensure that the phases are continuously adjustable.
According to the multi-channel signal source based on the digital logic chip, the signal generation module further comprises a power supply unit, a clock unit, a storage chip and a plurality of signal conditioning units;
the output end of the power supply unit is respectively connected with the clock unit, the field programmable gate array FPGA, the plurality of digital-to-analog conversion DA chips, the storage chip and the plurality of signal conditioning units;
the field programmable gate array FPGA is connected with the clock unit and the storage chip; the plurality of digital-to-analog conversion DA chips are connected with the plurality of signal conditioning units.
According to the multi-channel signal source based on the digital logic chip, the field programmable gate array FPGA controls various peripheral interfaces and generates various output signals through the 16-channel parallel 48-bit direct digital frequency synthesis DDS module;
the field programmable gate array FPGA controls the plurality of digital-to-analog conversion DA chips in an SPI mode, and transmits a plurality of paths of serialized high-speed digital signals for the plurality of digital-to-analog conversion DA chips through a JESD204B high-speed transmission interface.
According to the multi-channel signal source based on the digital logic chip, the signal conditioning units are used for filtering and amplifying the analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement, and outputting the filtered and amplified analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement.
According to the multi-channel signal source based on the digital logic chip, the clock unit provides a working clock for the field programmable gate array FPGA and various required clocks for the JESD204B high-speed transmission interface;
the clock unit generates various clock signals required by a plurality of digital-to-analog conversion DA chips under the control of the field programmable gate array FPGA.
According to the multi-channel signal source based on the digital logic chip, the power supply unit generates various voltages required by the FPGA, the clock unit, the storage chip, the DA chips and the signal conditioning units according to the voltage provided by the power supply module;
the memory chip is used for solidifying and storing the program.
According to the multi-channel signal source based on the digital logic chip, the multi-channel signal source based on the digital logic chip further comprises a power module, wherein the input end of the power module is connected with an alternating current power supply;
the first output end of the power supply module is connected with the display control module and used for providing a first preset amplitude voltage for the display control module;
and the second output end of the power supply module is connected with the signal generating module and used for providing a second preset amplitude voltage for the signal generating module.
According to the multi-channel signal source based on the digital logic chip, the display control module is a human-computer interaction module of the multi-channel signal source based on the digital logic chip;
and the display control module determines the input frequency value and the input phase value selected in the human-computer interaction interface and the on-off control of each output channel.
The application provides a multichannel signal source based on digital logic chip, digital logic chip include multichannel parallel multidigit direct digital frequency synthesis DDS module, and the digital signal that has exported multichannel frequency continuously adjustable and the phase place is continuous when changing the frequency, can not produce the breakpoint has realized promptly that output frequency continuously adjustable and phase place continuously adjustable's digital signal, the high-speed digital signal of rethread high-speed transmission interface output multichannel serialization. Meanwhile, the multi-channel high-speed digital signals are subjected to digital-to-analog conversion through a plurality of converter chips, and a plurality of independent analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement are output.
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In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce embodiments or drawings in the description of the prior art, and it is obvious that the drawings described below are some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive effort.
FIG. 1 is a schematic diagram of a digital logic chip based multi-channel signal source provided herein;
FIG. 2 is a second schematic diagram of a digital logic chip based multi-channel signal source provided in the present application;
fig. 3 is a third schematic diagram of a multipath signal source based on a digital logic chip provided in the present application.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The digital logic chip-based multipath signal source provided by the present application is further described with reference to fig. 1 to 3. FIG. 1 is a schematic diagram of a digital logic chip based multi-channel signal source provided herein; FIG. 2 is a second schematic diagram of a digital logic chip based multi-channel signal source provided in the present application; fig. 3 is a third schematic diagram of a multipath signal source based on a digital logic chip provided in the present application.
While the embodiments of the present application provide an example of a multi-channel signal source based on a digital logic chip, it should be noted that although a logic sequence is shown in the flow chart, under certain data, the steps shown or described may be performed in a different sequence than that shown here.
Referring to fig. 1, fig. 1 is a schematic diagram of a digital logic chip based multi-channel signal source provided in the present application. The multi-channel signal source based on the digital logic chip comprises a signal generating module;
the signal generation module comprises a digital logic chip and a plurality of converter chips, and the digital logic chip is connected with the converter chips, wherein the digital logic chip comprises a plurality of paths of parallel multi-bit direct digital frequency synthesis (DDS) modules;
the digital logic chip determines a phase increment value of a plurality of paths of parallel signals according to the initial phase and the phase variation of the plurality of paths of parallel signals; inputting the phase increment value into the multi-path parallel multi-bit direct digital frequency synthesis DDS module, and outputting multi-path serialized high-speed digital signals through a high-speed transmission interface of the digital logic chip;
and the converter chip performs digital-to-analog conversion on the plurality of paths of serialized high-speed digital signals under the control of the digital logic chip, and outputs a plurality of paths of analog signals with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement.
In this embodiment, the digital logic chip-based multi-channel signal source uses a 2U chassis, and is controlled by a front panel key display, and a basic architecture of the digital logic chip and a plurality of converter chips is adopted in the 2U chassis. Therefore, in one embodiment, the digital logic chip-based multipath signal source comprises a signal generation module, and the signal generation module comprises a digital logic chip and a plurality of converter chips. Further, the digital logic chip is connected with the plurality of converter chips, and the digital logic chip comprises a plurality of parallel multi-bit direct digital frequency synthesis DDS modules.
Further, the digital logic chip determines the initial phase and the phase variation of the multi-path parallel signals, and determines the phase increment value of the multi-path parallel signals according to the initial phase and the phase variation of the multi-path parallel signals. Furthermore, the digital logic chip inputs the obtained phase increment value into a multi-path parallel multi-bit direct digital frequency synthesis DDS module, and outputs a multi-path serialized high-speed digital signal through a high-speed transmission interface of the digital logic chip.
Further, the digital logic chip transmits the multiplexed serialized high-speed digital signals to the plurality of converter chips and controls the plurality of converter chips. Furthermore, under the control of the digital logic chip, the multiple converter chips perform digital-to-analog conversion on the multiple serialized high-speed digital signals, and output multiple analog signals with continuously adjustable frequency and phase, and the frequency resolution and the phase resolution meet the preset precision requirement.
Further, referring to fig. 2, fig. 2 is a second schematic diagram of the digital logic chip-based multi-channel signal source provided in the present application. In one embodiment, the digital logic chip-based multi-channel signal source further comprises a display control module. The digital logic chip comprises a Field Programmable Gate Array (FPGA), the converter chip comprises a digital-to-analog conversion (DA) chip, the multi-path parallel multi-bit direct digital frequency synthesis (DDS) module comprises 16 paths of parallel 48-bit direct digital frequency synthesis (DDS) modules, and the multi-path parallel signals comprise 16 paths of parallel signals.
Therefore, it can be understood that the 2U chassis used by the multiple signal sources based on the Digital logic chip adopts a basic architecture of a Field programmable Gate Array FPGA (Field-programmable Gate Array) and a plurality of Digital-to-analog conversion DA chips, wherein the Field programmable Gate Array FPGA (Field-programmable Gate Array) can adopt XCKU085-2FLVA1517I of XILINX corporation, the Digital-to-analog conversion DA chip can adopt AD9162 of ADI corporation, and one of the expressions of the Digital-to-analog conversion DA chips can be a Digital-to-analog converter dac (analog-to-Digital converter).
It can be further understood that the signal generating module includes a field programmable gate array FPGA and a plurality of digital-to-analog conversion DA chips, and in an embodiment, a 16-channel parallel 48-bit direct digital frequency synthesis DDS module is implemented inside the field programmable gate array FPGA, so that the output digital signal can be continuously frequency-modulated, and the phase is continuously maintained without interruption when the frequency is changed, so that the phase of the digital signal frequency is continuously adjustable, and meanwhile, the frequency resolution and the phase resolution of the output digital signal can meet the preset precision requirement.
Further, the 16-path parallel 48-bit direct digital frequency synthesis DDS module enables the frequency of the signal to be continuously adjustable, and the highest frequency is 2.5GHz (Hertz) under the condition of direct output; under the condition of 2 times of non-return-to-zero NRZ mode, the highest frequency is 6 GHz; under the condition of a mixed mode, the highest frequency is 1.5 to 7.5GHz, and the phase is kept continuous without interruption when the frequency is changed, so that the phase of the frequency is continuously adjustable, a digital signal with continuously adjustable frequency and continuously adjustable phase can be output, and meanwhile, the frequency resolution and the phase resolution of the output digital signal can meet the preset precision requirement.
Further, the FPGA calculates a phase increment value of the 16 paths of parallel signals by adopting an accumulation method according to the initial phase and the phase variation of the 16 paths of parallel signals. Meanwhile, the FPGA transmits the phase increment value of the 16 paths of parallel signals to a 16-path parallel 48-bit direct digital frequency synthesis DDS module to generate digital signals with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement. In one embodiment, the frequency resolution of the output signal of the DDS module with 48 bits direct digital frequency synthesis can reach 0.0000178Hz, and the phase resolution can reach 360/2 Hz 48 Frequency resolution 0.0000178Hz and phase resolution 360/2 48 The requirements of preset precision are met, so that multiple paths of independent digital signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirements can be output through 16 paths of parallel 48-bit direct digital frequency synthesis DDS modules. Thus, it is possible to provideIt can be understood that the field programmable gate array FPGA outputs multiple independent frequency continuous adjustability, phase continuous adjustability, frequency resolution of 0.0000178Hz and phase resolution of 360/2 Hz through 16 paths of parallel 48-bit direct digital frequency synthesis DDS modules 48 The digital signal of (2).
Further, the field programmable gate array FPGA accesses the digital signal with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement into the JESD204B high-speed transmission interface of the field programmable gate array FPGA, and outputs a multi-path serialized high-speed digital signal.
Further, the operating frequency of the 16-channel parallel 48-bit direct digital frequency synthesis DDS module inside the field programmable gate array FPGA is one sixteenth of the operating frequency of the digital-to-analog converter DAC, so that the 16-channel parallel 48-bit direct digital frequency synthesis DDS module maintains a preset interval on the initial phase, where the preset interval is one sixteenth of the phase variation of a single direct digital frequency synthesis DDS module.
Further, the PHASE variation PHASE _ DELTA of the 16-channel parallel 48-bit direct digital frequency synthesis DDS module is calculated according to the input frequency of the 16-channel parallel signals, so the initial PHASEs of the 16 direct digital frequency synthesis DDS are as follows: PHASE1= 0; PHASE2= PHASE _ DELTA × 1/16; PHASE3= PHASE _ DELTA × 2/16; PHASE4= PHASE _ DELTA × 3/16; PHASE5= PHASE _ DELTA × 4/16; PHASE6= PHASE _ DELTA × 5/16; PHASE7= PHASE _ DELTA × 6/16; PHASE8= PHASE _ DELTA × 7/16; PHASE9= PHASE _ DELTA × 8/16; PHASE10= PHASE _ DELTA × 9/16; PHASE11= PHASE _ DELTA × 10/16; PHASE12= PHASE _ DELTA × 11/16; PHASE13= PHASE _ DELTA × 12/16; PHASE14= PHASE _ DELTA 13/16; PHASE15= PHASE _ DELTA × 14/16; PHASE16= PHASE _ DELTA × 15/16.
Further, when the 16-channel parallel 48-bit direct digital frequency synthesis DDS module adjusts the PHASE corresponding to the frequency of the 16-channel parallel signal, the PHASE change amount PHASE _ DELTA _ NEW at the current time is calculated from the newly output PHASE. When the write enable comes, the phase increment value of the change is updated together on the basis of the phase change amount of the current moment, namely the phase increment value of the change is updated on the basis of the phase change amount of the current moment, and the phases at other moments except the current moment are continuously accumulated according to the original phase increment value of the phases, so that the phase is continuously adjustable.
Further, the FPGA transmits the multi-path high-speed digital signals to a plurality of DA (digital to analog) conversion chips. The plurality of digital-to-analog conversion DA chips receive the high-speed digital signals transmitted by the field programmable gate array FPGA, perform digital-to-analog conversion on the high-speed digital signals under the control of the field programmable gate array FPGA, and output a plurality of independent analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting preset precision requirements.
It can be understood that the field programmable gate array FPGA is connected to a plurality of digital-to-analog conversion DA chips, that is, one field programmable gate array FPGA is connected to a plurality of digital-to-analog conversion DA chips. Referring to fig. 2, the field programmable gate array FPGA in the signal generating module is connected to the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2, and the digital-to-analog conversion DA chip n, each of which can perform digital-to-analog conversion on the high-speed digital signal, therefore, each digital-to-analog conversion DA chip can output an analog signal with continuously adjustable frequency and phase, and the frequency resolution and the phase resolution meet the preset precision requirement, the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2 and the digital-to-analog conversion DA chip n are mutually independent and do not interfere with each other, therefore, the multi-channel signal source based on the digital logic chip in the embodiment of the application can output a plurality of independent analog signals with continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement.
It should be further noted that, because a hardware interface between the FPGA and the DA chip is limited, and cannot be increased without limitation, n number of the DA chip in this embodiment is at most 5, that is, n is less than or equal to 5, this embodiment may be exemplified by n number of the DA chip being 4, that is, 4 independent analog signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting preset precision requirements are finally output by the multi-channel signal source based on the digital logic chip in this embodiment.
Furthermore, the display control module is a human-computer interaction part of the whole digital logic chip-based multi-channel signal source, that is, the display control module can also be used as a human-computer interaction module of the digital logic chip-based multi-channel signal source, a user can input a frequency value and a phase value on a human-computer interaction interface of the digital logic chip-based multi-channel signal source through keys of the front panel, and each channel can be independently controlled and does not interfere with each other. Therefore, the display control module can determine the input frequency value and the input phase value selected by the user in the man-machine interaction interface. Further, the display control module has a display function, and in one embodiment, the display control module is connected to the signal generation module, and the display control module can acquire the real-time status information from the signal generation module and display the real-time status information from the signal generation module in real time on the interface. Further, the display control module can also control the switch of each output channel.
In the multi-channel signal source based on the digital logic chip provided by this embodiment, the field programmable gate array FPGA includes 16 parallel 48-bit direct digital frequency synthesis DDS modules, outputs a multi-channel digital signal with continuously adjustable frequency and continuous phase when changing frequency, and does not generate a breakpoint, that is, outputs a multi-channel serialized high-speed digital signal with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting the preset precision requirement through the high-speed transmission interface. Meanwhile, the multiple paths of high-speed digital signals are subjected to digital-to-analog conversion through the multiple digital-to-analog conversion DA chips, and multiple paths of independent analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting preset precision requirements are output.
Referring to fig. 3, fig. 3 is a third schematic diagram of a multipath signal source based on a digital logic chip provided in the present application. The signal generating module in the multi-channel signal source based on the digital logic chip further comprises a power supply unit, a clock unit, a storage chip and a plurality of signal conditioning units. The output end of the power supply unit is respectively connected with the FPGA, the clock unit, the DA chips, the memory chip and the signal conditioning units, wherein one expression form of the memory chip can be FLASH memory FLASH. It should be noted that, in order to make fig. 3 clear, the connection between the output end of the power supply unit and the field programmable gate array FPGA, the clock unit, the plurality of digital-to-analog conversion DA chips, the memory chip, and the plurality of signal conditioning units is omitted; the field programmable gate array FPGA is connected with the clock unit and the storage chip; a plurality of digital-to-analog conversion DA chips are connected with a plurality of signal conditioning units, as shown in fig. 3, one digital-to-analog conversion DA chip is connected with one signal conditioning unit, that is, the digital-to-analog conversion DA chip 1 is connected with the signal conditioning unit 1, the digital-to-analog conversion DA chip 2 is connected with the signal conditioning unit 2, the digital-to-analog conversion DA chip n is connected with the signal conditioning unit n, and the digital-to-analog conversion DA chip 1 and the signal conditioning unit 1, the digital-to-analog conversion DA chip 2 and the signal conditioning unit 2, and the digital-to-analog conversion DA chip n and the signal conditioning unit n are independent from each other and do not interfere with each other.
Furthermore, the multi-channel signal source based on the digital logic chip further comprises a power module, wherein an input end of the power module is connected with an alternating current power supply, the alternating current power supply is generally 220V (volt), and therefore the input of the power module is 220V alternating current power supply. Furthermore, the output end of the power supply module is respectively connected with the display control module and the signal generation module, and can supply power to the display control module and the signal generation module. In an embodiment, the first output terminal of the power module is connected to the display control module and provides a first preset amplitude voltage to the display control module, and in an embodiment, the first preset amplitude voltage is 5 volts and 3.3 volts, that is, the power module provides 5 volts and 3.3 volts to the display control module. Further, a second output end of the power module is connected to the signal generating module, and provides a second preset amplitude voltage for the signal generating module, in an embodiment, the second preset amplitude voltage is 12 volts and 6 volts, that is, the power module provides 12 volts and 6 volts for the signal generating module.
Furthermore, the power supply unit generates voltages required by the field programmable gate array FPGA, the clock unit, the storage chip, the plurality of digital-to-analog conversion DA chips and the plurality of signal conditioning units according to the voltage provided by the power supply module, and simultaneously supplies power to the field programmable gate array FPGA, the clock unit, the storage chip, the plurality of digital-to-analog conversion DA chips and the plurality of signal conditioning units through the required voltages. In one embodiment, the power supply unit generates voltages required by the field programmable gate array FPGA, the clock unit, the memory chip, the plurality of digital-to-analog conversion DA chips, and the plurality of signal conditioning units according to the 12V voltage and the 6V voltage provided by the external power supply module.
Further, the clock unit can provide various clocks required by the high-speed transmission interface of the JESD204B and the working clock on the one hand, and can also provide a clock signal for the digital-to-analog conversion DA chip on the other hand. In one embodiment, the clock unit provides the working clock and various clocks required by the JESD204B high-speed transmission interface for the field programmable gate array FPGA on the one hand; on the other hand, the clock unit generates various clock signals CLK required by a plurality of digital-to-analog conversion DA chips under the control of the field programmable gate array FPGA, that is, for the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2 to the digital-to-analog conversion DA chip n, the clock unit generates the clock signals CLK1, CLK2 to the clock signals CLKn corresponding to the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2 to the digital-to-analog conversion DA chip n, respectively, under the control of the field programmable gate array FPGA. Furthermore, the memory chip in the multi-channel signal source based on the digital logic chip is mainly used for solidified storage of the program.
Furthermore, the field programmable gate array FPGA can control various interfaces on one hand, and can output various output signals on the other hand, and control a plurality of digital-to-analog conversion DA chips and send high-speed digital signals to the plurality of digital-to-analog conversion DA chips.
In an embodiment, the signal generating module includes a field programmable gate array FPGA and a plurality of digital-to-analog conversion DA chips, and in an embodiment, a 16-channel parallel 48-bit direct digital frequency synthesis DDS module is implemented inside the field programmable gate array FPGA, so that the output digital signal can be continuously frequency-modulated, and the phase is kept continuous without interruption when the frequency is changed, so that the phase of the digital signal frequency is continuously adjustable, and meanwhile, the frequency resolution and the phase resolution of the output digital signal can meet the preset precision requirement. Further, the 16-path parallel 48-bit direct digital frequency synthesis DDS module enables the frequency of the signal to be continuously adjustable, and the highest frequency is 2.5GHz (Hertz) under the condition of direct output; under the condition of 2 times of non-return-to-zero NRZ mode, the highest frequency is 6 GHz; under the condition of a mixed mode, the highest frequency is 1.5 to 7.5GHz, the phase is kept continuous without interruption when the frequency is changed, so that the phase of the frequency is continuously adjustable, digital signals with continuously adjustable frequency and continuously adjustable phase can be output, and meanwhile, the frequency resolution and the phase resolution of the output digital signals can meet the preset precision requirement.
Furthermore, the field programmable gate array FPGA controls the plurality of digital-to-analog conversion DA chips in an SPI manner, that is, the field programmable gate array FPGA controls the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2, and the digital-to-analog conversion DA chip n in the SPI manner. In addition, the field programmable gate array FPGA transmits high-speed digital signals for the plurality of digital-to-analog conversion DA chips through the JESD204B high-speed transmission interface, that is, the field programmable gate array FPGA transmits high-speed digital signals with continuously adjustable frequency and continuously adjustable phase for the digital-to-analog conversion DA chip 1, the digital-to-analog conversion DA chip 2 and the digital-to-analog conversion DA chip n through the JESD204B high-speed transmission interface. It should be noted that, in order to make fig. 3 clear, the connection of the field programmable gate array FPGA to the JESD204B high-speed transmission interface between the digital-to-analog conversion DA chip 1 and the digital-to-analog conversion DA chip 2 to the digital-to-analog conversion DA chip n is omitted.
Further, a plurality of digital-to-analog conversion DA chips (digital-to-analog conversion DA chip 1, digital-to-analog conversion DA chip 2 to digital-to-analog conversion DA chip n) receive the high-speed digital signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution transmitted by the field programmable gate array FPGA through the JESD204B high-speed transmission interface, perform digital-to-analog conversion on the high-speed digital signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution under the control of the field programmable gate array FPGA, and output a plurality of independent analog signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting preset precision requirements. Meanwhile, the plurality of digital-to-analog conversion DA chips send the plurality of independent analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement to the corresponding plurality of signal conditioning units. It can be understood that the digital-to-analog conversion DA chip 1 sends the analog signal whose frequency is continuously adjustable, phase is continuously adjustable, and frequency resolution and phase resolution meet the preset accuracy requirement to the signal conditioning unit 1, the digital-to-analog conversion DA chip 2 sends the analog signal whose frequency is continuously adjustable, phase is continuously adjustable, and frequency resolution and phase resolution meet the preset accuracy requirement to the signal conditioning unit 2, and the digital-to-analog conversion DA chip n sends the analog signal whose frequency is continuously adjustable, phase is continuously adjustable, and frequency resolution and phase resolution meet the preset accuracy requirement to the signal conditioning unit n.
Furthermore, the plurality of signal conditioning units receive the analog signals which are transmitted by the plurality of digital-to-analog conversion DA chips and have continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement, filter and amplify the analog signals which are transmitted by the plurality of digital-to-analog conversion DA chips and have continuously adjustable frequency and continuously adjustable phase, and the frequency resolution and the phase resolution meet the preset precision requirement, and output a plurality of independent filtered and amplified analog signals which have continuously adjustable frequency and continuously adjustable phase, and have frequency resolution and phase resolution meeting the preset precision requirement.
In an embodiment, it can be understood that the signal conditioning unit 1 receives an analog signal which is transmitted by the digital-to-analog conversion DA chip 1 and has a continuously adjustable frequency and a continuously adjustable phase, and has a frequency resolution and a phase resolution meeting a preset precision requirement, and filters and amplifies the analog signal to output a first filtered and amplified analog signal which has a continuously adjustable frequency and a continuously adjustable phase, and has a frequency resolution and a phase resolution meeting a preset precision requirement. The signal conditioning unit 2 receives the analog signal which is transmitted by the digital-to-analog conversion DA chip 2 and has continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement, filters and amplifies the analog signal, and outputs a second path of filtered and amplified analog signal which has continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement. The signal conditioning unit n receives an analog signal which is transmitted by the digital-to-analog conversion DA chip n and has continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting preset precision requirements, filters and amplifies the analog signal, and outputs an nth analog signal which has continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirements, wherein the signals from the first path, the second path to the nth path are independent and do not interfere with each other, so that the n independent analog signals which have continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirements and are filtered and amplified are output.
In the multi-channel signal source based on the digital logic chip provided by this embodiment, the field programmable gate array FPGA includes 16 parallel 48-bit direct digital frequency synthesis DDS modules, outputs a multi-channel digital signal with continuously adjustable frequency and continuous phase when changing frequency, and does not generate a breakpoint, that is, outputs a multi-channel serialized high-speed digital signal with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting the preset precision requirement through the high-speed transmission interface. Meanwhile, the multiple paths of high-speed digital signals are subjected to digital-to-analog conversion through the multiple digital-to-analog conversion DA chips, and multiple paths of independent analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting preset precision requirements are output.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A multipath signal source based on a digital logic chip is characterized in that the multipath signal source based on the digital logic chip comprises a signal generating module;
the signal generation module comprises a digital logic chip and a plurality of converter chips, and the digital logic chip is connected with the converter chips, wherein the digital logic chip comprises a plurality of paths of parallel multi-bit direct digital frequency synthesis (DDS) modules;
the digital logic chip determines a phase increment value of a plurality of paths of parallel signals according to the initial phase and the phase variation of the plurality of paths of parallel signals; inputting the phase increment value into the multi-path parallel multi-bit direct digital frequency synthesis DDS module, and outputting multi-path serialized high-speed digital signals through a high-speed transmission interface of the digital logic chip;
and the converter chip performs digital-to-analog conversion on the plurality of paths of serialized high-speed digital signals under the control of the digital logic chip, and outputs a plurality of paths of analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement.
2. The digital logic chip-based multi-channel signal source of claim 1, further comprising a display control module; the digital logic chip comprises a Field Programmable Gate Array (FPGA), the converter chip comprises a digital-to-analog conversion (DA) chip, the multi-path parallel multi-bit direct digital frequency synthesis (DDS) module comprises 16 paths of parallel 48-bit direct digital frequency synthesis (DDS) modules, and the multi-path parallel signals comprise 16 paths of parallel signals;
the display control module is connected with the signal generation module and is used for displaying the state information of the signal generation module;
the FPGA determines a phase increment value of the 16 paths of parallel signals according to the initial phase and the phase variation of the 16 paths of parallel signals; inputting the phase increment value into the 16-channel parallel 48-bit direct digital frequency synthesis DDS module, and outputting a plurality of channels of serialized high-speed digital signals through a high-speed transmission interface of the field programmable gate array FPGA;
and the digital-to-analog conversion DA chip performs digital-to-analog conversion on a plurality of paths of serialized high-speed digital signals under the control of the field programmable gate array FPGA, and outputs a plurality of paths of analog signals with continuously adjustable frequency, continuously adjustable phase and frequency resolution and phase resolution meeting the preset precision requirement.
3. The digital logic chip-based multi-channel signal source of claim 2, wherein the 16-channel parallel 48-bit direct digital frequency synthesis DDS module calculates a phase variation at a current time according to a newly output phase when adjusting a phase corresponding to a frequency of the 16-channel parallel signal; and on the basis of the phase variation of the current moment, updating the phase increment values of the changes of the current moment together, and continuously accumulating the phases of other moments except the current moment according to the original phase increment values of the phases so as to ensure that the phases are continuously adjustable.
4. The digital-logic-chip-based multi-channel signal source of claim 2, wherein the signal generation module further comprises a power supply unit, a clock unit, a memory chip and a plurality of signal conditioning units;
the output end of the power supply unit is respectively connected with the clock unit, the field programmable gate array FPGA, the plurality of digital-to-analog conversion DA chips, the storage chip and the plurality of signal conditioning units;
the field programmable gate array FPGA is connected with the clock unit and the storage chip; the plurality of digital-to-analog conversion DA chips are connected with the plurality of signal conditioning units.
5. The digital-logic-chip-based multipath signal source of claim 4, wherein the field-programmable gate array FPGA controls various peripheral interfaces and generates various output signals through the 16-channel parallel 48-bit direct digital frequency synthesis DDS module;
the field programmable gate array FPGA controls the plurality of digital-to-analog conversion DA chips in an SPI mode, and transmits a plurality of paths of serialized high-speed digital signals for the plurality of digital-to-analog conversion DA chips through a JESD204B high-speed transmission interface.
6. The digital-logic-chip-based multi-channel signal source of claim 4, wherein the plurality of signal conditioning units filter and amplify the plurality of analog signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting a predetermined accuracy requirement, and output a plurality of filtered and amplified analog signals with continuously adjustable frequency, continuously adjustable phase, and frequency resolution and phase resolution meeting a predetermined accuracy requirement.
7. The digital-logic-chip-based multipath signal source of claim 4, wherein the clock unit provides an operating clock for the field programmable gate array FPGA and various clocks required for the JESD204B high-speed transmission interface;
the clock unit generates various clock signals required by a plurality of digital-to-analog conversion DA chips under the control of the field programmable gate array FPGA.
8. The digital-logic-chip-based multi-channel signal source of claim 4, wherein the power supply unit generates various voltages required by the FPGA, the clock unit, the memory chip, the DA chips and the signal conditioning units according to a voltage provided by a power supply module;
the memory chip is used for solidifying and storing the program.
9. The digital logic chip-based multi-channel signal source of claim 4, wherein the digital logic chip-based multi-channel signal source further comprises a power module, and an input end of the power module is connected to an alternating current power supply;
the first output end of the power supply module is connected with the display control module and used for providing a first preset amplitude voltage for the display control module;
and the second output end of the power supply module is connected with the signal generating module and used for providing a second preset amplitude voltage for the signal generating module.
10. The digital logic chip-based multi-channel signal source of claim 4, wherein the display control module is a human-computer interaction module of the digital logic chip-based multi-channel signal source;
and the display control module determines the input frequency value and the input phase value selected in the human-computer interaction interface and the on-off control of each output channel.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116500551A (en) * | 2023-06-21 | 2023-07-28 | 中国科学院空天信息创新研究院 | Frequency modulation signal output method for multiband synthetic aperture radar |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268594B1 (en) * | 2005-05-13 | 2007-09-11 | Xilinx, Inc. | Direct digital synthesis with low jitter |
| CN202929519U (en) * | 2012-09-27 | 2013-05-08 | 北京工业大学 | Multichannel phase adjustable signal generator |
| CN104034928A (en) * | 2014-05-28 | 2014-09-10 | 中北大学 | Multi-path signal source based on PCI and FPGA |
| CN108462524A (en) * | 2018-03-29 | 2018-08-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital Satellite Signal Source |
-
2022
- 2022-08-08 CN CN202210942487.XA patent/CN114995586A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268594B1 (en) * | 2005-05-13 | 2007-09-11 | Xilinx, Inc. | Direct digital synthesis with low jitter |
| CN202929519U (en) * | 2012-09-27 | 2013-05-08 | 北京工业大学 | Multichannel phase adjustable signal generator |
| CN104034928A (en) * | 2014-05-28 | 2014-09-10 | 中北大学 | Multi-path signal source based on PCI and FPGA |
| CN108462524A (en) * | 2018-03-29 | 2018-08-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital Satellite Signal Source |
Non-Patent Citations (3)
| Title |
|---|
| 付豪等: "基于FPGA的4路信号发生器的设计", 《湖北民族学院学报(自然科学版)》 * |
| 孙永亮等: "基于DDS技术的多路同步信号源的设计", 《现代电子技术》 * |
| 黄沛昱: "《EDA技术与VHDL设计实验指导》", 31 August 2012 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116500551A (en) * | 2023-06-21 | 2023-07-28 | 中国科学院空天信息创新研究院 | Frequency modulation signal output method for multiband synthetic aperture radar |
| CN116500551B (en) * | 2023-06-21 | 2023-09-12 | 中国科学院空天信息创新研究院 | Frequency modulation signal output method for multiband synthetic aperture radar |
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