CN109239423B - Arbitrary waveform current signal source based on FPGA - Google Patents
Arbitrary waveform current signal source based on FPGA Download PDFInfo
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Abstract
The embodiment of the invention discloses an arbitrary waveform current signal source based on an FPGA. The current signal source comprises a control device, an FPGA, a memory, a buffer, a DAC circuit and an analog channel circuit, wherein the control device is connected with the FPGA control signal, the FPGA is connected with the memory, the buffer, the DAC circuit and the analog channel circuit control signal, the FPGA is connected with the buffer data signal, the buffer is connected with the memory and the DAC circuit data signal, the memory is connected with the DAC circuit data signal, and the DAC circuit is connected with the analog channel circuit analog signal; the DAC circuit is used for converting the waveform digital signal into an analog current signal; the analog channel circuit is used for amplifying the amplitude of the analog current signal output by the DAC circuit to the amplitude specified by a user and filtering. The current signal source can realize current signals with arbitrary waveforms, and the waveforms can be switched at any time.
Description
Technical Field
The invention relates to the technical Field of electronic measurement, in particular to an arbitrary waveform current signal source based on a Field programmable gate array (Field-Programable GateArray, abbreviated as FPGA).
Background
In the fields of aerospace, communication, automatic control, electronic precision instruments, basic physics and other leading edge scientific research, a known signal is often required to be used as an excitation source. The most common signal sources already present are arbitrary waveform generators and constant current sources. The arbitrary waveform generator can generate various function waveform signals and user-defined arbitrary waveform signals according to user needs besides common standard waveform signals. The existing arbitrary waveform generator outputs signals in the form of voltages, namely, under the same setting, when the instrument is connected with different loads, the currents are different and the voltages are unchanged.
However, in practical applications, a current-type signal source is often required, i.e. the current waveform of the output of the signal source is required to remain unchanged during the measurement process, such as a tunable laser. The current arbitrary waveform generator cannot meet the current output requirement. Although the constant current source can meet the current output requirement, the constant current source can only output constant current or can be switched among different constant currents, and the function of any waveform cannot be realized.
Therefore, there is a strong need in the market for a signal source that can produce both arbitrary waveforms and current output.
Disclosure of Invention
The embodiment of the invention aims to provide an arbitrary waveform current signal source based on an FPGA, which is used for solving the problem that the existing signal source cannot output an arbitrary waveform current signal.
In order to achieve the above object, an embodiment of the present invention provides an arbitrary waveform current signal source based on an FPGA, where the current signal source includes a control device, an FPGA, a memory, a buffer, a DAC circuit, and an analog channel circuit, the control device is connected to the FPGA control signal, the FPGA is connected to the memory, the buffer, the DAC circuit, and the analog channel circuit control signal, the FPGA is connected to the buffer data signal, the buffer is connected to the memory and the DAC circuit data signal, the memory is connected to the DAC circuit data signal, and the DAC circuit is connected to the analog channel circuit; wherein,
The control device is used for obtaining a user input instruction, converting the user input instruction into a control command and transmitting the control command to the FPGA;
The FPGA is used for executing the control command, storing waveform data of one period in the periodic signal in the memory when the executed control command is a periodic signal, controlling the DAC circuit according to the frequency and waveform of the periodic signal, and controlling the analog channel circuit according to the amplitude designated by a user; when the executed control command is to generate an aperiodic signal, the FPGA controls the DAC circuit to directly execute the control command;
the buffer is used for storing the waveform data in the memory;
The DAC circuit is used for converting waveform data into analog current signals;
The analog channel circuit is used for amplifying the amplitude of the analog current signal output by the DAC circuit to a user-specified amplitude.
The control device comprises an input unit and an ARM processor, wherein the input unit is connected with the ARM processor in a control signal manner; wherein,
The input unit is used for inputting a user instruction;
the ARM processor is used for converting the user instruction into a control command and transmitting the control command to the FPGA.
The input unit is a human-computer interface and/or an upper computer.
The FPGA executes a direct digital frequency synthesis algorithm according to the frequency and the waveform of the periodic signal, and circularly looks up the reading of the memory by using a frequency control word so as to output the reading to the DAC circuit and the analog channel circuit.
The analog channel circuit comprises a current-to-voltage circuit, a controllable gain amplifier and a voltage-to-current circuit, wherein the input end of the current-to-voltage circuit is connected with the output end of the DAC circuit, and the output end of the current-to-voltage circuit is sequentially connected with the controllable gain amplifier and the voltage-to-current circuit; wherein,
The current-to-voltage circuit is used for converting an analog current signal output by the DAC circuit into a voltage signal;
The controllable gain amplifier is used for amplifying the voltage signal obtained by the current-to-voltage circuit according to the amplification factor designated by a user;
The voltage-to-current circuit is used for converting the amplified voltage signal into a current signal.
Preferably, the analog channel circuit further comprises a first selector switch, a fixed gain amplifier and a second selector switch, wherein the input end of the first selector switch is connected with the output end of the current-to-voltage circuit, and the first output end and the second output end of the first selector switch are respectively connected with the second input ends of the fixed gain amplifier and the second selector switch; the output end of the fixed gain amplifier is connected with the first input end of the second selection switch, and the fixed gain amplifier is used for amplifying the voltage signal obtained by the current-to-voltage circuit according to fixed amplification factor; the output end of the second selection switch is connected with the input end of the voltage-to-current circuit, and the control end of the first selection switch and the control end of the second selection switch are connected with the FPGA control signal.
Preferably, the analog channel circuit further includes a filter, and an input end and an output end of the filter are respectively connected with the output end of the controllable gain amplifier and the input end of the voltage-to-current circuit, and the filter is used for filtering burrs and noise in the voltage signal.
The voltage-to-current circuit comprises an operational amplifier A1 and an operational amplifier A2, wherein a resistor R1 is connected in series between an inverting input end N 1 of the operational amplifier A1 and the ground, a resistor R2 is connected in series between an inverting input end N 1 of the operational amplifier A1 and an output end U 01, a resistor R3 is connected in series between a non-inverting input end P 1 of the operational amplifier A1 and a voltage input end U 1, and a resistor R 0 is connected in series between an output end U 01 of the operational amplifier A1 and a current output end I 0 of the voltage-to-current circuit;
the resistor R4 is connected in series between the inverting input terminal N 2 of the operational amplifier A2 and the non-inverting input terminal P 2 of the operational amplifier A1, the non-inverting input terminal P 2 of the operational amplifier A2 is electrically connected with the current output terminal I 0 of the voltage-to-current circuit, and the output terminal U 02 of the operational amplifier A2 is electrically connected with the inverting input terminal N 2 of the operational amplifier A2.
The voltage-to-current circuit comprises an operational amplifier OP1 and a triode Q1, wherein a resistor R2 is connected in series between a normal phase input end and a voltage input end Vi of the operational amplifier OP1, a resistor R5 is connected in series between an opposite phase input end of the operational amplifier OP1 and an emitter of the triode Q1, an output end of the operational amplifier OP1 is connected in series with a base of the triode Q1, a resistor R7 is connected in series between an emitter of the triode Q1 and a current output end, a resistor R6 is connected in series between the current output end and the normal phase input end of the operational amplifier OP1, and a collector of the triode Q1 is electrically connected with a direct-current voltage source.
Preferably, the voltage-to-current circuit further includes a resistor R1, a resistor R4, a capacitor C1, and a diode D1, where the resistor R1 is connected in series between the voltage input terminal Vi and ground, the resistor R4 is connected in series between the inverting input terminal of the operational amplifier OP1 and ground, the capacitor C1 is connected in series between the voltage input terminal Vi and ground, the positive electrode of the diode D1 is electrically connected to the base electrode of the triode Q1, and the negative electrode of the diode D1 is grounded.
The embodiment of the invention has the following advantages:
According to the FPGA-based arbitrary waveform current signal source, the control command is obtained through the control device according to the user command, the FPGA is utilized to execute the control command, the DAC circuit is used for converting data into the analog current signal, the DAC circuit is used for switching the output waveform at any time according to the control of the FPGA, the analog channel circuit is used for amplifying the amplitude of the analog current signal output by the DAC circuit to the amplitude appointed by the user, so that the current signal amplitude can be flexibly set, and the current signal of arbitrary waveform is obtained. In addition, the internal programming of the FPGA can achieve fine frequency resolution, thereby improving the frequency resolution of the current signal source. The amplification mode of combining the fixed gain amplifier and the controllable gain amplifier ensures the larger amplitude dynamic range of the signal source output and can improve the amplitude dynamic range.
As a preferred embodiment of the invention, the current signal source may improve the dynamic range and resolution of the amplitude of the current signal by a combination of a fixed gain amplifier and a controllable gain amplifier.
Drawings
Fig. 1 is a schematic diagram of an FPGA-based arbitrary waveform current signal source according to embodiment 1 of the present invention (in the drawing, solid arrows indicate transmission directions of control signals, and open arrows indicate transmission directions of waveform signals).
Fig. 2 is a block diagram of a voltage-to-current circuit in an FPGA-based arbitrary waveform current signal source according to embodiment 1 of the present invention.
Fig. 3 is a control flow chart of the arbitrary waveform current signal source based on the FPGA provided in embodiment 1 of the present invention.
Fig. 4 is a block diagram of another voltage-to-current circuit in the FPGA-based arbitrary waveform current signal source according to embodiment 2 of the present invention.
In the figure: the device comprises a 1-control device, an 11-input unit, a 12-ARM processor, a 2-FPGA, a 3-memory, a 4-buffer, a 5-DAC circuit, a 6-analog channel circuit, a 61-current-to-voltage circuit, a 62-controllable gain amplifier, a 63-voltage-to-current circuit, a 64-first selection switch, a 65-fixed gain amplifier, a 66-second selection switch and a 67-filter.
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the disclosure of the present invention, which is described by the following specific examples.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the invention, are not intended to be critical to the essential characteristics of the invention, but are intended to fall within the spirit and scope of the invention. Also, the terms such as "upper", "lower", "left", "right", "middle" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the invention for which the invention may be practiced or for which the relative relationships may be altered or modified without materially altering the technical context.
Example 1
The embodiment provides an arbitrary waveform current signal source based on an FPGA. As shown in fig. 1, the current signal source includes a control device 1, an FPGA2, a memory 3, a buffer 4, a DAC circuit 5, and an analog channel circuit 6. The control device 1 is connected with FPGA2 control signals, the FPGA2 is connected with a memory 3, a buffer 4, a DAC circuit 5 and an analog channel circuit 6 control signals, the FPGA2 is connected with the buffer 4 data signals, the buffer 4 is connected with the memory 3 and the DAC circuit 5 data signals, the memory 3 is connected with the DAC circuit 5 data signals, and the DAC circuit 5 is connected with the analog channel circuit 6. Wherein,
The control device 1 is used for obtaining control commands. The control device 1 comprises an input unit 11 and an ARM processor 12, wherein the input unit 11 is in control signal connection with the ARM processor 12. Wherein the input unit 11 is used for inputting user instructions; ARM processor 12 is used to translate user instructions into control commands that are then sent to FPGA2. The ARM processor 12 writes not only the waveform input by the user into the FPGA2, but also the frequency and amplitude required by the user into the FPGA2 in the form of frequency control words and amplitude control words.
In the present embodiment, the input unit 11 adopts, but is not limited to, a human-machine interface or an upper computer. The input unit 11 may be one of a human-computer interface and an upper computer, or may be both a human-computer interface and an upper computer. The human-machine interface may be a touch screen or a key. The user can input the required waveforms through a human-computer interface, and the user can edit the waveforms through an upper computer and then send the waveforms to the ARM processor 12 through a USB interface.
The FPGA2 receives control commands of the ARM processor 12, and controls the memory 3, the buffer 4, the DAC circuit 5, and the analog channel circuit 6 to execute the control commands.
When the FPGA2 executes the control command to be a periodic signal, the FPGA2 stores one period data in the periodic signal in the memory 3 in the form of a lookup table, and controls the DAC circuit 5 according to the frequency and waveform of the periodic signal, that is, performs a direct digital frequency synthesis algorithm (DDS-Direct DigitalFrequency Synthesis) according to the frequency and waveform of the periodic signal, and controls the DAC circuit 5 to convert the waveform data into an analog current signal by looking up the table reading in a corresponding step. Meanwhile, the FPGA2 controls the analog channel circuit 6 according to the amplitude specified by the user, so that the amplitude of the analog current signal reaches the amplitude specified by the user.
When the control command executed by the FPGA2 is an aperiodic signal, the FPGA2 controls the DAC circuit 5 to directly execute the control command, that is, the FPGA2 controls the DAC circuit 5 to directly convert the current waveform data into a current signal and output the current signal.
It should be noted that the direct digital synthesis algorithm adopted in this embodiment belongs to common general knowledge in the art, and is not described in detail herein.
Memory 3 employs, but IS not limited to, RAM memory of model IS61LV12816L, which has 128k, 16-bit memory space.
The buffer 4 is used to store the periodic data in the memory 3, i.e. the buffer 4 is just a bridge for storing the periodic data, and the digital signal is input into the memory. When the FPGA stores data in the memory 3, the buffer 4 is opened, and a bridge between the FPGA2 and the memory 3 is established, so that digital signals can be input into the memory 3. When the FPGA2 reads the data in the memory 3 to the DAC circuit, the buffer 4 is closed, so that the data in the memory 3 is directly transferred to the DAC circuit 4, so as to avoid the data in the memory 3 from affecting the input/output port of the FPGA. When the control command executed by the FPGA2 is an aperiodic signal, the buffer 4 is opened, and the FPGA2 controls the data to be directly transferred to the DAC circuit.
The DAC circuit 5 is configured to convert a digital waveform signal into an analog current signal, that is, when a control command executed by the FPGA2 is a periodic signal, the DAC circuit 5 converts periodic data into a periodic analog current signal; when the control command executed by the FPGA2 is an aperiodic signal, the DAC circuit 5 converts the present data waveform signal into an analog current signal.
The analog channel circuit 6 is for amplifying the amplitude of the analog current signal output from the DAC circuit 5 to a user-specified amplitude. The analog channel circuit 6 comprises a current-to-voltage circuit 61, a controllable gain amplifier 62 and a voltage-to-current circuit 63, wherein the input end of the current-to-voltage circuit 61 is connected with the output end of the DAC circuit 5, and the output end of the current-to-voltage circuit 61 is sequentially connected with the controllable gain amplifier 62 and the voltage-to-current circuit 63; wherein,
The current-to-voltage circuit 61 is used for converting the analog current signal output from the DAC circuit 5 into a voltage signal. The controllable gain amplifier 62 is used for amplifying the voltage signal obtained by the current-to-voltage circuit 61 by a user-specified amplification factor. The amplification factor of the controllable gain amplifier 62 can be calculated according to the amplitude requirement of the customer, and the voltage-to-current circuit 63 is used for converting the amplified voltage signal into a current signal.
As a preferred embodiment of the present embodiment, the analog channel circuit 6 further includes a first selection switch 64, a fixed gain amplifier 65, and a second selection switch 66, wherein an input terminal of the first selection switch 64 is connected to an output terminal of the current-to-voltage circuit 61, and a first output terminal and a second output terminal of the first selection switch 64 are respectively connected to second input terminals of the fixed gain amplifier 65 and the second selection switch 66; the output end of the fixed gain amplifier 65 is connected with the first input end of the second selection switch 66, and the fixed gain amplifier 65 is used for amplifying the voltage signal obtained by the current-to-voltage circuit 61 according to a fixed amplification factor; an output terminal of the second selection switch 66 is connected to the controllable gain amplifier 62, and a control terminal of the first selection switch 64 and a control terminal of the second selection switch 66 are connected to an output terminal of the FPGA 2. When the waveform amplitude of the customer is large, the first output terminal of the first selection switch 64 is connected to the fixed gain amplifier 65, the second output terminal of the first selection switch 64 is disconnected from the second input terminal of the second selection switch 66, and the fixed gain amplifier 65 is connected to the first input terminal of the second selection switch 66. When the customer's waveform amplitude is small, the first output of the first selection switch 64 is disconnected from the fixed gain amplifier 65 and the second output of the first selection switch 64 is directly connected to the second input of the second selection switch 66.
As another preferred embodiment of the present embodiment, the analog channel circuit 6 further includes a filter 67, wherein an input end and an output end of the filter 67 are respectively connected to the output end of the controllable gain amplifier 62 and the input end of the voltage-to-current circuit 63, and the filter 67 is used for filtering burrs and noise in the voltage signal.
As shown in fig. 2, in the present embodiment, the voltage-to-current circuit includes an operational amplifier A1 and an operational amplifier A2, a resistor R1 is connected in series between an inverting input terminal N 1 of the operational amplifier A1 and ground, a resistor R2 is connected in series between an inverting input terminal N 1 of the operational amplifier A1 and an output terminal U 01, a resistor R3 is connected in series between a non-inverting input terminal P 1 of the operational amplifier A1 and a voltage input terminal U 1, and a resistor R 0 is connected in series between an output terminal U 01 of the operational amplifier A1 and a current output terminal I 0 of the voltage-to-current circuit.
The resistor R4 is connected in series between the inverting input terminal N 2 of the operational amplifier A2 and the non-inverting input terminal P 2 of the operational amplifier A1, the non-inverting input terminal P 2 of the operational amplifier A2 is electrically connected to the current output terminal I 0 of the voltage-to-current circuit, and the output terminal U 02 of the operational amplifier A2 is electrically connected to the inverting input terminal N 2 of the operational amplifier A2.
The voltage-to-current circuit 63 further includes a resistor R1, a resistor R4, a capacitor C1, and a diode D1, where the resistor R1 is connected in series between the voltage input terminal Vi and ground, the resistor R4 is connected in series between the inverting input terminal of the operational amplifier OP1 and ground, the capacitor C1 is connected in series between the voltage input terminal Vi and ground, the positive electrode of the diode D1 is electrically connected to the base of the triode Q1, and the negative electrode of the diode D1 is grounded.
As shown in fig. 3, the workflow of the FPGA-based arbitrary waveform current signal source provided in this embodiment includes:
Step S1, a user inputs an instruction.
The user can input the instruction through the human-computer interface, can also input the instruction through the upper computer, and transmit to the ARM processor through the USB interface. The user inputs the amplitude and frequency of the waveform through a human-machine interface or an upper computer.
Step S2, the ARM processor decodes.
The ARM processor decodes the instruction input by the user.
Step S3, judging whether the instruction is a periodic signal, if so, executing step S4; if not, step S91 is performed.
Step S4, calculating waveform data.
The ARM processor calculates waveform data of one period in the periodic signal.
Step S51, the periodic data is stored in the memory.
After the ARM processor obtains one period data in the period signal, the FPGA control buffer stores the period data in the memory.
Step S61, calculating a frequency control word according to the waveform frequency.
The ARM processor calculates a frequency control word based on the frequency of the waveform input by the user.
In step S71, the FPGA performs cyclic accumulation on the frequency control words.
The FPGA performs cyclic accumulation on the frequency control words to control the memory.
Step S81, performing cyclic addressing reading to the memory.
The FPGA controls the memory to perform cyclic addressing readings, i.e., to read waveform data stored in the memory.
In step S91, the DAC circuit is controlled to convert the data into an analog current signal.
The FPGA controls the DAC circuit to convert the waveform data into an analog current signal.
In addition, after step S5, further comprising:
Step S62, judging whether the amplitude of the waveform is larger, if so, executing step S72; if not, executing step S82;
The processor decodes the signal amplitude set by the user into an amplitude control word and transmits the amplitude control word to the FPGA. The FPGA judges whether the stored amplitude is larger according to the amplitude control word, the judging standard can be based on a preset value preset in the FPGA, if the amplitude exceeds the preset value, the amplitude of the waveform is considered to be larger, a high-gain channel is selected, and if the amplitude exceeds the preset value, a low-gain channel is selected.
Step S72, selecting a high gain channel.
The FPGA controls the analog channel circuit to select the fixed gain amplifier, namely, the first output end of the first selection switch is connected with the fixed gain amplifier, the second output end of the first selection switch is disconnected with the second input end of the second selection switch, and the voltage signal is amplified according to the fixed gain and then amplified again in the controllable gain amplifier.
Step S82, selecting a low gain channel.
The FPGA controls the analog channel circuit to select the controllable gain amplifier, namely, the first output end of the first selection switch is disconnected with the fixed gain amplifier, the second output end of the first selection switch is connected with the second input end of the second selection switch, and the voltage signal is amplified by the controllable gain amplifier only.
Step S92, controlling the controllable gain amplifier according to the amplitude control word.
And the FPGA controls the amplification factor of the controllable gain amplifier according to the amplitude control word.
Example 2
The embodiment provides an arbitrary waveform current signal source based on an FPGA. As shown in fig. 1, the current signal source includes a control device 1, an FPGA2, a memory 3, a buffer 4, a DAC circuit 5, and an analog channel circuit 6. The control device 1 is connected with FPGA2 control signals, the FPGA2 is connected with a memory 3, a buffer 4, a DAC circuit 5 and an analog channel circuit 6 control signals, the FPGA2 is connected with the buffer 4 data signals, the buffer 4 is connected with the memory 3 and the DAC circuit 5 data signals, the memory 3 is connected with the DAC circuit 5 data signals, and the DAC circuit 5 is connected with the analog channel circuit 6.
In this embodiment, the structures and functions of the control device 1, the FPGA2, the memory 3, the buffer 4, and the DAC circuit 5 are the same as those of embodiment 1, and will not be described again.
The analog channel circuit 6 is for amplifying the amplitude of the analog current signal output from the DAC circuit 5 to a user-specified amplitude. The analog channel circuit 6 comprises a current-to-voltage circuit 61, a controllable gain amplifier 62 and a voltage-to-current circuit 63, wherein the input end of the current-to-voltage circuit 61 is connected with the output end of the DAC circuit 5, and the output end of the current-to-voltage circuit 61 is sequentially connected with the controllable gain amplifier 62 and the voltage-to-current circuit 63. Preferably, the analog channel circuit 6 further comprises a first selection switch 64, a fixed gain amplifier 65 and a second selection switch 66. More preferably, the analog channel circuit 6 further comprises a filter 67. The current-to-voltage circuit 61, the controllable gain amplifier 62, the first selection switch 64, the fixed gain amplifier 65, the second selection switch 66 and the filter 67 are identical to those of embodiment 1, and will not be described again here. The difference is only that the voltage-to-current circuit is used, and the current is constant by using emitter feedback of the triode. Specifically:
As shown in fig. 4, the voltage-to-current circuit includes an operational amplifier OP1 and a triode Q1, a resistor R2 is connected in series between a normal phase input terminal and a voltage input terminal Vi of the operational amplifier OP1, a resistor R5 is connected in series between an inverting input terminal of the operational amplifier OP1 and an emitter of the triode Q1, an output terminal of the operational amplifier OP1 is connected in series with a base of the triode Q1 by a resistor R3, a resistor R7 is connected in series between an emitter of the triode Q1 and a current output terminal, a resistor R6 is connected in series between the current output terminal and the normal phase input terminal of the operational amplifier OP1, and a collector of the triode Q1 is electrically connected with a dc voltage source.
According to the FPGA-based arbitrary waveform current signal source, the control command is obtained through the control device according to the user command, the FPGA is utilized to execute the control command, the DAC circuit is used for converting data into an analog current signal, the DAC circuit is used for switching the output waveform at any time according to the control command of the FPGA, the analog channel circuit is used for amplifying the amplitude of the analog current signal output by the DAC circuit to the user-specified amplitude, and therefore the current signal amplitude can be flexibly set, and the arbitrary waveform current signal is obtained. In addition, the internal programming of the FPGA can realize fine frequency resolution of the current signal, so that the frequency resolution of the current signal source is improved.
While the invention has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (7)
1. The current signal source is characterized by comprising a control device, an FPGA, a memory, a buffer, a DAC circuit and an analog channel circuit, wherein the control device is connected with the FPGA control signal, the FPGA is connected with the memory, the buffer, the DAC circuit and the analog channel circuit control signal, the FPGA is connected with the buffer data signal, the buffer is connected with the memory and the DAC circuit data signal, the memory is connected with the DAC circuit data signal, and the DAC circuit is connected with the analog channel circuit analog signal; wherein,
The control device is used for obtaining the control command and transmitting the control command to the FPGA;
The FPGA is used for executing the control command, storing waveform data of one period in the periodic signal in the memory when the executed control command is a periodic signal, controlling the DAC circuit according to the frequency and waveform of the periodic signal, and controlling the analog channel circuit according to the amplitude designated by a user; when the executed control command is to generate an aperiodic signal, the FPGA controls the DAC circuit to directly execute the control command;
the buffer is used for storing the waveform data in the memory;
The DAC circuit is used for converting waveform data into analog current signals;
The analog channel circuit is used for amplifying the amplitude of the analog current signal output by the DAC circuit to the amplitude appointed by a user; the analog channel circuit comprises a current-to-voltage circuit, a controllable gain amplifier and a voltage-to-current circuit, wherein the input end of the current-to-voltage circuit is connected with the output end of the DAC circuit, and the output end of the current-to-voltage circuit is sequentially connected with the controllable gain amplifier and the voltage-to-current circuit; wherein:
The current-to-voltage circuit is used for converting an analog current signal output by the DAC circuit into a voltage signal;
The controllable gain amplifier is used for amplifying the voltage signal obtained by the current-to-voltage circuit according to the amplification factor designated by a user;
The voltage-to-current circuit is used for converting the amplified voltage signal into a current signal;
The analog channel circuit further comprises a first selection switch, a fixed gain amplifier and a second selection switch, wherein the input end of the first selection switch is connected with the output end of the current-to-voltage circuit, the first output end and the second output end of the first selection switch are respectively connected with the second input ends of the fixed gain amplifier and the second selection switch, and the control end of the first selection switch is connected with the output end control signal of the FPGA; the output end of the fixed gain amplifier is connected with the first input end of the second selection switch, and the fixed gain amplifier is used for amplifying the voltage signal obtained by the current-to-voltage circuit according to fixed amplification factor; the output end of the second selection switch is connected with the input end of the voltage-to-current circuit, and the control end of the second selection switch is connected with the output end of the FPGA through a control signal;
The analog channel circuit further comprises a filter, wherein the input end and the output end of the filter are respectively connected with the output end of the controllable gain amplifier and the input end of the voltage-to-current circuit, and the filter is used for filtering burrs and noise in a voltage signal.
2. The FPGA-based arbitrary waveform current signal source of claim 1, wherein the control device comprises an input unit and an ARM processor, the input unit is in control signal connection with the ARM processor; wherein,
The input unit is used for inputting a user instruction;
the ARM processor is used for converting the user instruction into a control command and transmitting the control command to the FPGA.
3. The FPGA-based arbitrary waveform current signal source of claim 2, wherein the input unit is a human-machine interface and/or an upper computer.
4. The FPGA-based arbitrary waveform current signal source of claim 1, wherein the FPGA performs a direct digital frequency synthesis algorithm based on the frequency and waveform of the periodic signal and loops look-up table readings from the memory with a frequency control word for output to the DAC circuit.
5. The FPGA-based arbitrary waveform current signal source according to claim 1, wherein the voltage-to-current circuit comprises an operational amplifier A1 and an operational amplifier A2, a resistor R1 is connected in series between an inverting input terminal N 1 of the operational amplifier A1 and ground, a resistor R2 is connected in series between an inverting input terminal N 1 of the operational amplifier A1 and an output terminal U 01, a resistor R3 is connected in series between a non-inverting input terminal P 1 of the operational amplifier A1 and a voltage input terminal U 1, and a resistor R 0 is connected in series between an output terminal U 01 of the operational amplifier A1 and a current output terminal I 0 of the voltage-to-current circuit;
the resistor R4 is connected in series between the inverting input terminal N 2 of the operational amplifier A2 and the non-inverting input terminal P 2 of the operational amplifier A1, the non-inverting input terminal P 2 of the operational amplifier A2 is electrically connected with the current output terminal I 0 of the voltage-to-current circuit, and the output terminal U 02 of the operational amplifier A2 is electrically connected with the inverting input terminal N 2 of the operational amplifier A2.
6. The FPGA-based arbitrary waveform current signal source according to claim 1, wherein the voltage-to-current circuit comprises an operational amplifier OP1 and a triode Q1, a resistor R2 is connected in series between a positive input terminal and a voltage input terminal Vi of the operational amplifier OP1, a resistor R5 is connected in series between an inverting input terminal of the operational amplifier OP1 and an emitter of the triode Q1, an output terminal of the operational amplifier OP1 is connected in series with a base of the triode Q1 by a resistor R3, a resistor R7 is connected in series between an emitter of the triode Q1 and a current output terminal, a resistor R6 is connected in series between a current output terminal and a positive input terminal of the operational amplifier OP1, and a collector of the triode Q1 is electrically connected with a dc voltage source.
7. The FPGA-based arbitrary waveform current signal source of claim 6, wherein the voltage-to-current circuit further comprises a resistor R1, a resistor R4, a capacitor C1, and a diode D1, the resistor R1 is connected in series between the voltage input terminal Vi and ground, the resistor R4 is connected in series between the inverting input terminal of the operational amplifier OP1 and ground, the capacitor C1 is connected in series between the voltage input terminal Vi and ground, the positive electrode of the diode D1 is electrically connected to the base electrode of the transistor Q1, and the negative electrode of the diode D1 is grounded.
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| CN117055440A (en) * | 2023-09-21 | 2023-11-14 | 和光精电(重庆)科技有限公司 | Current source signal generation method and device of any non-ideal waveform |
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