CN104022117A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104022117A
CN104022117A CN201310349323.7A CN201310349323A CN104022117A CN 104022117 A CN104022117 A CN 104022117A CN 201310349323 A CN201310349323 A CN 201310349323A CN 104022117 A CN104022117 A CN 104022117A
Authority
CN
China
Prior art keywords
mentioned
semiconductor chip
support
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310349323.7A
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English (en)
Chinese (zh)
Inventor
前田竹识
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN104022117A publication Critical patent/CN104022117A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
CN201310349323.7A 2013-02-28 2013-08-12 半导体装置及其制造方法 Pending CN104022117A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013039217A JP2014167973A (ja) 2013-02-28 2013-02-28 半導体装置およびその製造方法
JP039217/2013 2013-02-28

Publications (1)

Publication Number Publication Date
CN104022117A true CN104022117A (zh) 2014-09-03

Family

ID=51438790

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310349323.7A Pending CN104022117A (zh) 2013-02-28 2013-08-12 半导体装置及其制造方法

Country Status (3)

Country Link
JP (1) JP2014167973A (ja)
CN (1) CN104022117A (ja)
TW (1) TW201434096A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204297A (zh) * 2016-03-17 2017-09-26 东芝存储器株式会社 半导体装置及形成半导体装置的方法
CN108152298A (zh) * 2017-12-21 2018-06-12 京信通信系统（中国）有限公司 一种焊点的检测方法及装置
CN112490223A (zh) * 2019-09-12 2021-03-12 铠侠股份有限公司 半导体装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6515047B2 (ja) 2016-03-11 2019-05-15 東芝メモリ株式会社 半導体装置及びその製造方法
JP7042713B2 (ja) 2018-07-12 2022-03-28 キオクシア株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040050571A1 (en) * 2002-09-13 2004-03-18 Sang-Yeop Lee Semiconductor chip package having an adhesive tape attached on bonding wires
JP2007081127A (ja) * 2005-09-14 2007-03-29 Sharp Corp 半導体装置及び半導体装置の製造方法
US20090121327A1 (en) * 2007-11-08 2009-05-14 Nec Electronics Corporation Semiconductor device having spacer formed on semiconductor chip connected with wire
CN102142398A (zh) * 2010-01-08 2011-08-03 瑞萨电子株式会社 制造半导体器件的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007023852A1 (ja) * 2005-08-24 2007-03-01 Fujitsu Limited 半導体装置及びその製造方法
JP5543084B2 (ja) * 2008-06-24 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置の製造方法
JP5373713B2 (ja) * 2010-07-23 2013-12-18 三菱電機株式会社 半導体装置
JP5601282B2 (ja) * 2011-06-01 2014-10-08 株式会社デンソー 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040050571A1 (en) * 2002-09-13 2004-03-18 Sang-Yeop Lee Semiconductor chip package having an adhesive tape attached on bonding wires
JP2007081127A (ja) * 2005-09-14 2007-03-29 Sharp Corp 半導体装置及び半導体装置の製造方法
US20090121327A1 (en) * 2007-11-08 2009-05-14 Nec Electronics Corporation Semiconductor device having spacer formed on semiconductor chip connected with wire
CN102142398A (zh) * 2010-01-08 2011-08-03 瑞萨电子株式会社 制造半导体器件的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204297A (zh) * 2016-03-17 2017-09-26 东芝存储器株式会社 半导体装置及形成半导体装置的方法
CN108152298A (zh) * 2017-12-21 2018-06-12 京信通信系统（中国）有限公司 一种焊点的检测方法及装置
CN112490223A (zh) * 2019-09-12 2021-03-12 铠侠股份有限公司 半导体装置
CN112490223B (zh) * 2019-09-12 2023-11-21 铠侠股份有限公司 半导体装置

Also Published As

Publication number Publication date
TW201434096A (zh) 2014-09-01
JP2014167973A (ja) 2014-09-11

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Application publication date: 20140903