CN104009082B - 晶体管、包含晶体管的可变电阻存储器件及其制造方法 - Google Patents

晶体管、包含晶体管的可变电阻存储器件及其制造方法 Download PDF

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CN104009082B
CN104009082B CN201310446378.XA CN201310446378A CN104009082B CN 104009082 B CN104009082 B CN 104009082B CN 201310446378 A CN201310446378 A CN 201310446378A CN 104009082 B CN104009082 B CN 104009082B
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gate electrode
layer
electrode
active cylinder
channel region
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CN104009082A (zh
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朴南均
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

一种可变电阻存储器件，包括垂直晶体管，该垂直晶体管包括：有源柱体，有源柱体包括沟道区、形成于沟道区的一端的源极、以及形成于沟道区的另一端的轻掺杂漏极(LDD)区和漏极；第一栅电极，被形成为围绕轻掺杂漏极(LDD)区的外围，且具有第一功函数；以及第二栅电极，被形成为连接至第一栅电极并围绕沟道区，且具有高于第一功函数的第二功函数。

Description

晶体管、包含晶体管的可变电阻存储器件及其制造方法
相关申请的交叉引用
本申请要求2013年2月27日向韩国知识产权局提交的申请号为10-2013-0021164的韩国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本发明的示例性具体实施例关于一种半导体集成电路器件，尤其关于一种晶体管、包含晶体管的可变电阻存储器件和其制造方法。
背景技术
随着移动装置、数字信息通信和消费电子产业的快速发展，预期现有电子电荷控制器件的研究会面临到限制。因此，需要开发与现有电子电荷器件不同的新概念的新功能型存储器件，尤其需要具有大容量、超高速以及超低功耗的的下一代存储器件。
现在，把电阻器件当作存储介质来使用的电阻存储器件已被建议作为下一代存储器件，一些例子为︰相变随机存取存储器(phase-change random access memories,PCRAMs)、电阻随机存取存储器(resistance RAMs,ReRAMs)和磁阻随机存取存储器(magentoresistive RAMs,MRAMs)
电阻存储器件基本上可以被配置有开关器件和电阻器件，并根据电阻器件的状态来储存数据“0”或“1”。
即使在电阻存储器件中，最优先的是提高集成密度并将最多的存储器单元集成于狭窄的区域。
为了满足这些需求，电阻存储器件采已经用了三维(three-dimensional,3D)垂直晶体管结构。
然而，即使在3D垂直晶体管中，薄的栅极层仍是可能被需要的。因此，当高电压供应至栅极时，高电场被施加至轻掺杂漏极(lightly doped drain,LDD)区，并且可能造成栅致漏极泄漏(gate induced drain leakage,GIDL)。
发明内容
根据本发明的示例性具体实施例的一方面，一种晶体管可以包括：有源柱体，包括沟道区、形成于沟道区的一端的源极、以及形成于沟道区的另一端的轻掺杂漏极区和漏极；第一栅电极，被形成为围绕轻掺杂漏极区的外围，且具有第一功函数；以及第二栅电极，被形成为连接至第一栅电极并围绕沟道区，且具有高于第一功函数的第二功函数。
根据本发明的示例性具体实施例的另一方面，一种可变电阻存储器件可以包括垂直晶体管和连接至垂直晶体管的漏极的电阻存储结构，垂直晶体管包括：有源柱体，包括沟道区、形成于沟道区的一端的源极、以及形成于沟道区的另一端的轻掺杂漏极区和漏极；第一栅电极，被形成为围绕轻掺杂漏极区的外围，且具有第一功函数；以及第二栅电极，被形成为连接至第一栅电极并围绕沟道区，且具有高于第一功函数的第二功函数。
根据本发明的示例性具体实施例的再另一方面，一种可变电阻存储器件的制造方法可以包括：在半导体衬底中形成源极区；在源极区上形成半导体层；将半导体层图案化以形成有源柱体；形成第一栅极来围绕有源柱体；用绝缘层围绕第一栅极的上部区而暴露第一栅极的下部区；以及通过增大暴露的第一栅极的功函数来形成第二栅电极。
这些和其它本发明的特征、方面、具体实施例将被描述于下面的“具体实施方式”。
附图说明
将配合所附的附图从以下详细描述中更加清楚地理解本发明公开的主题的上述和其它方面、特征和其它优点，其中：
图1示出根据本发明的示例性具体实施例的一种包括垂直晶体管的可变电阻存储器件的示意剖视图；
图2至图5依序示出根据本发明的示例性具体实施例的一种可变存储器件的垂直晶体管的制程的示意剖视图；
图6示出根据本发明的另一示例性具体实施例的一种包括垂直晶体管的可变电阻存储器件的示意剖视图；
图7和图8依序示出图6的垂直晶体管的制程的示意性剖视图；
图9示出根据本发明的另一示例性具体实施例的垂直晶体管的示意图；以及
图10示出根据本发明的另一示例性具体实施例的垂直晶体管的示意剖视图。
具体实施方式
在下文中，本发明的各种示例性具体实施例将参考所附的附图来更详细地描述。
这里参考示例性具体实施例(和中间结构)的示意的剖面图描述示例性具体实施例。故，可以以预期缘于例如制造技术和/或公差的各种形状变化和可以。因此，示例性具体实施例不应解释为局限于这里所示的区域的特定形状，而是可以包括缘于例如制造的形状误差。在附图中，为了清楚起见，层与区的长度和尺寸可以被夸大。在附图中的相同的附图标记标记着相同的部件。
应该容易被理解的是，在本文中的“在…上”与“在...之上”应以最广泛的方式解释。“在…上”指的不只是“直接在…上”，亦可以指在其间有中间特征或层的某东西上，且“在...之上”指的不只是“直接在…的顶部”，亦可以指在其间由中间特征或层的某东西之上。应注意的是，于本说明书中的“连接/耦接”代表的不只是一构件直接耦接另一构件，亦可以代表的是通过中间构件间接耦接另一构件。此外，只要句子中没特定的提到，单数形包括多形。
参见图1，根据本发明的示例性具体实施例的一种可变电阻存储器件100可以包括垂直晶体管101和电阻存储结构185。
垂直晶体管101可以包括有源柱体120、第一栅电极140和第二栅电极160。
源极S可以被提供于有源柱体120之下并且漏极D可以被提供于有源柱体120之上。在源极S与漏极D之间的有源柱体120用作垂直晶体管101的沟道区。此时，有源柱体120可以被解释为包括源极S的一种结构，或是有源柱体120可以具有独立地形成在源极S上的一种结构。源极S以及有源柱体120可以为半导体层。另外，轻掺杂漏极区LDD，其为低浓度的杂质区，可以被形成在有源柱体120中并介于有源柱体120的用作沟道区的部分与漏极D之间，因此短沟道效应可以被减轻。
第一栅电极140可以被形成为围绕有源柱体120的上部(轻掺杂漏极区LDD形成在其中)的周围。第一栅电极140可以部分地与漏极D的一部分重叠，但第一栅电极140可以被实质地形成于有源柱体120的对应于轻掺杂漏极区LDD的位置。
第二栅电极160可以被连接至第一栅电极140，并且围绕有源柱体120的沟道区。例如，第二栅电极160可以与第一栅电极140接触且位于第一栅电极140之下。此时，第一栅电极140可以包括功函数低于第二栅电极160的材料。也就是说，当重叠轻掺杂漏极区LDD的第一栅电极140的功函数降低时，高电场特性所造成的GIDL可以被减轻，故可以改善轻掺杂漏极区LDD和邻近轻掺杂漏极区LDD的漏极D的GIDL特性。
此时，栅极绝缘层135可以被插入于第一栅电极140、第二栅电极160与有源柱体120之间。各种绝缘层(例如金属氧化物层和硅氧化物层)可以被用作栅极绝缘层135。
电阻存储结构185可以被配置下部电极170和电阻存储层180。下部电极170可以为形成于漏极D上的导电层，且提供电流和电压至电阻存储层180。虽然图1并未示出，可以基于下部电极170的材料特性而在下部电极170与漏极D之间插入欧姆层。电阻存储层180可以是其电阻根据下部电极170提供的电流和电压而改变的层。作为电阻存储层180，可以多样地使用用于电阻随机存取存储器(ReRAM)的材料的PCMO层、用于相变随机存取存储器(PCRAM)的材料的硫族化合物层、用于磁阻随机存取存储器(MRAM)的材料的磁性层、用于自旋转移力矩随机存取存储器(STTMRAM)的材料的磁性反转器件层、或用于聚合物随机存取存储器(PoRAM)的材料的聚合物层等。
在该具体实施例的垂直晶体管中，相比于在沟道区的栅电极，在轻掺杂漏极区LDD的栅电极由具有相对低的功函数的材料所形成，其中该轻掺杂漏极区LDD具有较低GIDL阻障并且施加有高电场。
如上所述，具有相对低的功函数的栅电极围绕轻掺杂漏极区LDD而设置以补偿跟随高电场的施加的低GIDL阻障，从而可以减少漏电流。
一种包括垂直晶体管的可变电阻存储器件的制造方法将参考图2至图5而被详细描述。
参照图2，通过将杂质注入半导体衬底105的上部中而在半导体衬底105中形成源极110。半导体层形成在形成有源极110的半导体衬底105上。例如，半导体层可以为杂质掺杂的多晶硅层或是外延生长的半导体衬底105(其中形成有源极)的层。硬质掩膜层130(例如氮化硅层)沉积于半导体层。硬质掩膜层130的预定部分与半导体层的预定部分图案化以形成多个有源柱体120。栅极绝缘层135形成于所述多个有源柱体120的表面以及半导体衬底105的表面。作为栅极绝缘层135，可以使用其中化诸如硅(Si)、钽(Ta)、钛(Ti)、钡钛(BaTi)、锆酸钡(BaZr)、锆(Zr)、铪(Hf)、镧(La)、铝(Al)、钇(Y)、或硅化锆(ZrSi)的导电材料被氧化的层。第一导电层沉积在包含栅极绝缘层135的半导体衬底105上，且被非等向性地刻蚀来围绕有源柱体120。因此，第一栅电极140形成在每一覆盖有栅极绝缘层135的有源柱体120的外部周缘之上。此时，通过非等向性过度刻蚀，第一栅电极140可以被形成具有小于有源柱体120的高度。例如，作为第一栅电极140，可以使用过渡金属层，其包括诸如钛(Ti)、钽(Ta)、钴(Co)或铂(Pt)的金属。
如第3图所示，第一绝缘层145形成以填充所述有源柱体120间的空间。接着，第一绝缘层145凹陷以暴露第一栅电极140的上部区。此时，第一绝缘层145的上表面可以定位成对应于有源柱体120的沟道形成区。第二绝缘层150形成以覆盖第一栅电极140暴露的上部区。第二绝缘层150可以由具有不同于第一绝缘层145的刻蚀选择率的材料所形成。
参照图4，第一绝缘层145被选择性地移除以暴露第一栅电极140的下部区。接着，氮离子被注入至暴露的第一栅电极140中以形成由金属氮化物层所形成的第二栅电极160，例如图5所示的氮化钛(TiN)层。如所周知，诸如钛层的耐火金属层具有低于诸如TiN层的金属氮化物层的功函数。因此，栅电极的对应于轻掺杂漏极区LDD的部分由具有相对低的功函数的材料所形成，从而减少因GIDL造成的漏电流。
接着，回去参照图1，有源柱体120上的硬质掩膜层130被移除，并且轻掺杂漏极区LDD通过向有源柱体120中注入低浓度的杂质而形成。接着，高浓度的杂质被注入形成有轻掺杂漏极区LDD的有源柱体120中以定义漏极D。
下部电极170和电阻存储层180依序形成在漏极D上以制成可变电阻存储器件。
与金属氮化物层不同的金属硅化物层可以被用作第二栅电极160。
也就是，如图6所示，围绕轻掺杂漏极区LDD的第一栅电极140可以由过渡金属层（如上述的示例性具体实施例中的示例）所形成，且第二栅电极165可以由位于第一栅电极140之下且具有高于第一栅电极140的功函数的过渡金属硅化物层所形成。此时，第二栅电极165的厚度b可以大于第一栅电极140的厚度a。
由于过渡金属层亦具有低于过渡金属硅化物层的功函数，围绕在具有微弱GIDL特性的轻掺杂漏极区LDD的漏电流可以被减少。
在图6中所示的一种垂直晶体管的制造方法将参考图7和图8而详述。在这里，该示例性具体实施例中的可变电阻存储器件的制造方法中某些与前述的示例性具体实施例中的可变电阻存储器件的制造方法中的图1至图3的过程实质地相同。因此，将描述图3过程之后的过程。
参照图7，第一绝缘层(图3的145)被选择地移除以暴露第一栅电极140的侧壁。硅层163以预定厚度沉积在第一栅电极140的暴露表面上。硅层163可以被形成位于第二绝缘层150的下方。
参照图8，对半导体衬底105进行热处理，使得第一栅电极140与接触该第一栅电极140的硅层163反应，以形成由过渡金属硅化物层形成的第二栅电极165。此时，由于第二栅电极165是通过第一栅电极140与硅层163的热反应而形成的层，硅层163的厚度可以被提供当做第二栅电极165的厚度。因此，第二栅电极165的厚度可以大于第一栅电极140的厚度。
如图9所示，第一栅电极142和第二栅电极167可以被依序地形成来围绕有源柱体120。
也就是，第一栅电极142被形成为围绕覆盖有栅极绝缘层135的有源柱体120的外部周缘。此时，重要的是栅电极142被形成不重叠轻掺杂漏极区LDD。
接着，第二栅极167被形成为围绕第一栅电极142的外部周缘。此时，第二栅极167可以超过第一栅电极而延伸预定长度c，使得第二栅极167重叠轻掺杂漏极区LDD的一部分。因此，举例来说，只有绝缘层135的一部分存在于轻掺杂漏极区LDD与第二栅极167之间而未插有第一栅电极142。在这里，第二栅电极167可以具有高于第一栅电极142的功函数。然而，在某些情况下，第二栅电极167可以由功函数相近于或低于第一栅电极142的功函数的材料所形成。
具有上述结构的垂直晶体管中，由于第一栅电极142被形成为具有相对低的功函数、并且介于轻掺杂漏极区LDD与重叠轻掺杂漏极区LDD的第二栅电极167之间的距离增大，施加至轻掺杂漏极区LDD的高电场可以被减缓并且由低GIDL造成的漏电流可以被降低。
除了垂直晶体管结构外，双栅电极结构也可以应用于埋入式栅电极结构。
也就是，如图10所示，沟槽210形成在半导体衬底200中。源极S和漏极D形成在沟槽210两侧的半导体衬底200中。
第一电极220和第二电极230可以被形成在形成有栅极绝缘层215的沟槽210中。第一栅电极220可以被形成在沟槽210的内表面。第一栅电极220可以被形成以实质位于沟槽210的下部，使得第一栅电极220可以不重叠源极S和漏极D。
第二栅电极230可以被形成为填充围绕有第一栅电极220的沟槽210的内部。此时，第二栅电极230可以被形成为具有长于第一栅电极220的高度的高度，使得第二栅电极230可以重叠源极S和漏极D的一部分。
虽然图10未示出，但对所属领域普通技术人员显而易见的是，如图2和图6所示的电组存储结构185可以被附加地形成。附图标记240和250代表绝缘层。
进而，围绕漏极D的区域重叠第二栅电极230而无第一栅电极220的插入。因此，受高电场影响的围绕漏极的区域到栅电极的距离实质增大，使得GIDL效应可以被减少。
此外，由于第一栅电极220由功函数低于第二栅电极230的材料所形成，所以电场对围绕漏极D的区域（也就是对应于轻掺杂漏极区LDD的区域）的影响可以进步地被减轻。
另外，第二栅电极230可以被形成为填充围绕有第一栅电极220的沟槽210内部。
具体如上所述，根据所述具体实施例，由于栅电极具有相对低的功函数形成于轻掺杂漏极区LDD周围，因高电场施加而造成的低GIDL阻障可以被补偿且漏电流可以被减少。
本发明在上文中的具体实施例是说明性的，本发明不被上述具体实施例所限制。各种替代物或等效物都是可能的，本发明并不限于任何特定种类的半导体器件。鉴于本发明公开，可以进行其它添加、删除或调整，并且都将落入所附权利要求的范围内。
通过以上实施例可以看出，本申请提供了如下的技术方案。
1.一种晶体管，包括：
有源柱体，所述有源柱体包括沟道区、形成于所述沟道区的一端的源极、以及形成于所述沟道区的另一端的轻掺杂漏极区和漏极；
第一栅电极，所述第一栅电极被形成为围绕所述轻掺杂漏极区的外围，且具有第一功函数；以及
第二栅电极，所述第二栅电极被形成为连接至所述第一栅电极并围绕所述沟道区，且具有高于所述第一功函数的第二功函数。
2.如技术方案1所述的晶体管，其中，所述第一栅电极包括过渡金属层，所述过渡金属层包括选自包括钛Ti、钽Ta、钴Co和铂Pt的群组中的一种。
3.如技术方案2所述的晶体管，其中，所述第二栅电极包括金属氮化物层。
4.如技术方案2所述的晶体管，其中，所述第二栅电极包括过渡金属硅化物层。
5.如技术方案4所述的晶体管，其中，所述第二栅电极被形成为厚度大于所述第一栅电极的厚度。
6.如技术方案1所述的晶体管，其中，所述第一栅电极形成于所述有源柱体的外部周缘，且所述第二栅电极形成于所述第一栅电极的外部周缘。
7.如技术方案6所述的晶体管，其中，所述第一栅电极被形成为高度小于所述第二栅电极的高度，且所述第二栅电极被形成为重叠于所述有源柱体而没有所述第一栅电极插入。
8.一种可变电阻存储器件，包括：
垂直晶体管，所述垂直晶体管包括：
有源柱体，所述有源柱体包括沟道区、形成于所述沟道区的一端的源极、以及形成于所述沟道区的另一端的轻掺杂漏极区和漏极；
第一栅电极，所述第一栅电极被形成为围绕所述轻掺杂漏极区的外围，且具有第一功函数；以及
第二栅电极，所述第二栅电极被形成为连接至所述第一栅电极并围绕所述沟道区，且具有高于所述第一功函数的第二功函数；以及
电阻存储结构，所述电阻存储结构连接至所述垂直晶体管的漏极。
9.如技术方案8所述的可变电阻存储器件，其中，所述第一栅电极包括过渡金属层，所述过渡金属层包括选自包括钛Ti、钽Ta、钴Co和铂Pt的群组中的任何一种。
10.如技术方案8所述的可变电阻存储器件，其中，所述第二栅电极包括金属氮化物层。
11.如技术方案8所述的可变电阻存储器件，其中，所述第二栅电极包括过渡金属硅化物层。
12.如技术方案8所述的可变电阻存储器件，其中，所述第二栅电极被形成为厚度大于所述第一栅电极的厚度。
13.如技术方案8所述的可变电阻存储器件，其中，所述第一栅电极形成于所述有源柱体的外部周缘，且所述第二栅电极形成于所述第一栅电极的外部周缘。
14.如技术方案13所述的可变电阻存储器件，其中，所述第一栅电极被形成为高度小于所述第二栅电极的高度，且所述第二栅电极被形成为重叠于所述有源柱体而没有所述第一栅电极插入。
15.如技术方案8所述的可变电阻存储器件，其中，所述电阻存储结构包括：
下部电极，所述下部电极形成于所述漏极上；以及
电阻存储层，所述电阻存储层形成于所述下部电极上。
16.如技术方案15所述的可变电阻存储器件，其中，所述电阻存储层包括选自以下群组中的一种，所述群组包括：包含用于电阻随机存取存储器ReRAM的材料的PCMO层、包含用于相变随机存取存储器PCRAM的材料的硫族化合物层、包含用于磁阻随机存取存储器MRAM的材料的磁性层、包含用于自旋转移力矩随机存取存储器STTMRAM的材料的磁性反转器件层、以及包含用于聚合物随机存取存储器PoRAM的材料的聚合物层。
17.一种可变电阻存储器件的制造方法，包括：
在半导体衬底中形成源极区；
在所述源极区上形成半导体层；
将所述半导体层图案化以形成有源柱体；
形成第一栅电极来围绕所述有源柱体；
用绝缘层围绕所述第一栅电极的上部区而暴露所述第一栅电极的下部区；以及
通过增大暴露的第一栅电极的功函数来形成第二栅电极。
18.如技术方案17所述的制造方法，其中，形成所述第二栅电极包括向暴露的所述第一栅电极的下部区中注入氮离子。
19.如技术方案17所述的制造方法，其中，形成所述第二栅电极包括：
于暴露的所述第一栅电极的下部区上形成硅层；以及
通过使所述第一栅电极与所述硅层反应而形成硅化物层。
20.如技术方案17所述的制造方法，还包括：
于所述有源柱体上形成下部电极；以及
于所述下部电极上形成电阻存储层。
21.一种晶体管，包括：
有源柱体，所述有源柱体包括沟道区、形成于所述沟道区的一端的源极、以及形成于所述沟道区的另一端的漏极与轻掺杂漏极区；
第一栅电极，所述第一栅电极被形成为围绕所述轻掺杂漏极区，且具有第一功函数；以及
第二栅电极，所述第二栅电极被形成为围绕所述沟道区，且具有高于所述第一功函数的第二功函数。

Claims (14)

1.一种晶体管，包括：
有源柱体，所述有源柱体包括沟道区、形成于所述沟道区的一端的源极、以及形成于所述沟道区的另一端的轻掺杂漏极区和漏极；
第一栅电极，所述第一栅电极被形成为围绕所述轻掺杂漏极区的外围，且具有第一功函数；以及
第二栅电极，所述第二栅电极被形成为连接至所述第一栅电极并围绕所述沟道区，且具有高于所述第一功函数的第二功函数，
其中，所述第一栅电极形成于所述有源柱体的外部周缘，且所述第二栅电极形成于所述第一栅电极的外部周缘，以及
其中，所述第一栅电极被形成为高度小于所述第二栅电极的高度，使得所述第二栅电极被形成为重叠于所述有源柱体而所述第二栅电极的一部分与所述有源柱体之间没有所述第一栅电极插入。
2.如权利要求1所述的晶体管，其中，所述第一栅电极包括过渡金属层，所述过渡金属层包括选自包括钛Ti、钽Ta、钴Co和铂Pt的群组中的一种。
3.如权利要求2所述的晶体管，其中，所述第二栅电极包括金属氮化物层。
4.如权利要求2所述的晶体管，其中，所述第二栅电极包括过渡金属硅化物层。
5.一种可变电阻存储器件，包括：
垂直晶体管，所述垂直晶体管包括：
有源柱体，所述有源柱体包括沟道区、形成于所述沟道区的一端的源极、以及形成于所述沟道区的另一端的轻掺杂漏极区和漏极；
第一栅电极，所述第一栅电极被形成为围绕所述轻掺杂漏极区的外围，且具有第一功函数；以及
第二栅电极，所述第二栅电极被形成在所述第一栅电极之下而直接连接至所述第一栅电极并围绕所述沟道区，且具有高于所述第一功函数的第二功函数；以及
电阻存储结构，所述电阻存储结构连接至所述垂直晶体管的漏极，
其中，所述第一栅电极形成于所述有源柱体的外部周缘，且所述第二栅电极形成于所述第一栅电极的外部周缘，以及
其中，所述第一栅电极被形成为高度小于所述第二栅电极的高度，使得所述第二栅电极被形成为重叠于所述有源柱体而所述第二栅电极的一部分与所述有源柱体之间没有所述第一栅电极插入。
6.如权利要求5所述的可变电阻存储器件，其中，所述第一栅电极包括过渡金属层，所述过渡金属层包括选自包括钛Ti、钽Ta、钴Co和铂Pt的群组中的任何一种。
7.如权利要求5所述的可变电阻存储器件，其中，所述第二栅电极包括金属氮化物层。
8.如权利要求5所述的可变电阻存储器件，其中，所述第二栅电极包括过渡金属硅化物层。
9.如权利要求5所述的可变电阻存储器件，其中，所述电阻存储结构包括：
下部电极，所述下部电极形成于所述漏极上；以及
电阻存储层，所述电阻存储层形成于所述下部电极上。
10.如权利要求9所述的可变电阻存储器件，其中，所述电阻存储层包括选自以下群组中的一种，所述群组包括：包含用于电阻随机存取存储器ReRAM的材料的PCMO层、包含用于相变随机存取存储器PCRAM的材料的硫族化合物层、包含用于磁阻随机存取存储器MRAM的材料的磁性层、包含用于自旋转移力矩随机存取存储器STTMRAM的材料的磁性反转器件层、以及包含用于聚合物随机存取存储器PoRAM的材料的聚合物层。
11.一种可变电阻存储器件的制造方法，包括：
在半导体衬底中形成源极区；
在所述源极区上形成半导体层；
将所述半导体层图案化以形成有源柱体；
形成第一栅电极来围绕所述有源柱体；
用绝缘层围绕所述第一栅电极的上部区而暴露所述第一栅电极的下部区；以及
通过增大暴露的第一栅电极的功函数来形成第二栅电极。
12.如权利要求11所述的制造方法，其中，形成所述第二栅电极包括向暴露的所述第一栅电极的下部区中注入氮离子。
13.如权利要求11所述的制造方法，其中，形成所述第二栅电极包括：
于暴露的所述第一栅电极的下部区上形成硅层；以及
通过使所述第一栅电极与所述硅层反应而形成硅化物层。
14.如权利要求11所述的制造方法，还包括：
于所述有源柱体上形成下部电极；以及
于所述下部电极上形成电阻存储层。
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