US20140239247A1 - Transistor, resistance variable memory device including the same, and manufacturing method thereof - Google Patents
Transistor, resistance variable memory device including the same, and manufacturing method thereof Download PDFInfo
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- US20140239247A1 US20140239247A1 US13/948,490 US201313948490A US2014239247A1 US 20140239247 A1 US20140239247 A1 US 20140239247A1 US 201313948490 A US201313948490 A US 201313948490A US 2014239247 A1 US2014239247 A1 US 2014239247A1
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Abstract
A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function.
Description
- The present application claims priority under 35 U.S.C, 119(a) to Korean application number 10-2013-0021164, filed on Feb. 27, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
- 1. Technical Field
- Exemplary embodiments of the present invention relate to a semiconductor integrated circuit device, and more particularly, to a transistor, and a resistance variable memory device including the same, and a manufacturing method thereof.
- 2. Related Art
- With the rapid development of mobile and digital information communication and consumer-electronic industry, studies on existing electronic charge controlled-devices are expected to encounter the limitation. Thus, new functional memory devices of new concept other than the existing electronic charge devices need to be developed. In particular, next-generation memory devices with large capacity, ultra-high speed, and ultra-low power are in demand.
- Currently, resistive memory devices using a resistance device as a memory medium have been suggested as the next generation memory devices, and some of the examples are phase-change random access memories (PCRAMs), resistance RAMs (ReRAMs), and magentoresistive RAMS (MRAMs).
- The resistive memory devices may be basically configured of a switching device and a resistance device and store data “0” or “1” according to a state of the resistance device.
- Even in the resistive memory devices, the first priority is to improve an integration density and to integrate most memory cells in a narrow area
- To meet these demands, the resistive memory devices have also adopted three-dimensional (3D) vertical transistor structures.
- However, even in the 3D vertical transistors, thin gate insulating layers may be required. Thus, when a high voltage is supplied to a gate, a high electric field is applied to a lightly doped drain (LDD) region and gate induced drain leakage (GIRL) may be caused.
- According to one aspect of an exemplary embodiment of the present invention, a transistor may include an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region, and having a second work function that is higher than the first work function.
- According to another aspect of an exemplary embodiment of the present invention, a resistance variable memory device may include a vertical transistor including an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function higher than the first work function, and a resistive memory structure connected to the drain of the vertical transistor.
- According to still another aspect of an exemplary embodiment of the present invention, a method of manufacturing a resistance variable semiconductor device may include forming a source region in a semiconductor substrate, forming a semiconductor layer on the source region, patterning the semiconductor layer to form an active pillar, forming a first gate electrode to surround the active pillar, surrounding an upper region of the first gate electrode with an insulating layer while exposing a lower region of the first gate electrode, and forming a second gate electrode by increasing a work function of the exposed first gate electrode.
- These and other features, aspects, and embodiments of the present invention are described below in the section entitled “DETAILED DESCRIPTION”.
- The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a schematic cross-sectional view illustrating a resistance variable memory device including a vertical transistor according to an exemplary implementation of the inventive concept; -
FIGS. 2 to 5 are cross-sectional views sequentially illustrating a process of manufacturing a vertical transistor of a resistance variable memory device according to an exemplary implementation of the inventive concept; -
FIG. 6 is a schematic cross-sectional view illustrating a resistance variable memory device including a vertical transistor according to another exemplary implementation of the inventive concept; -
FIGS. 7 and 8 are cross-sectional views sequentially illustrating a process of manufacturing a vertical transistor ofFIG. 6 ; -
FIG. 9 is a schematic diagram illustrating a vertical transistor according to another exemplary implementation of the inventive concept; and -
FIG. 10 is a schematic cross-sectional view illustrating a vertical transistor according to another exemplary implementation of the inventive concept. - Hereinafter, various exemplary embodiments of the present invention will be described in greater detail with reference to the accompanying drawings.
- Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.
- It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” means not only “directly on” but also “on” something with an intermediate feature(s) or a layer(s) therebetween, and that “over” means not only directly on top but also on top of something with an intermediate feature(s) or a layer(s) therebetween. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.
- Referring to
FIG. 1 , a resistancevariable memory device 100 according to an exemplary embodiment may include avertical transistor 101 and aresistive memory structure 185. - The
vertical transistor 101 may include anactive pillar 120, afirst gate electrode 140, and asecond gate electrode 160. - A source S may be provided below the
active pillar 120 and a drain D is provided on theactive pillar 120. Theactive pillar 120 between the source S and the drain D serves as a channel region of thevertical transistor 101. At this time, theactive pillar 120 may be interpreted as a structure including the source S, or theactive pillar 120 may have a structure separately formed on the source S. The source S and theactive pillar 120 may be semiconductor layers. Further, a lightly doped drain (LDD) region LDD, which is a low concentration impurity region, may be formed in theactive pillar 120 between a portion of theactive pillar 120 serving as the channel region and the drain D, and thus a short channel effect may be alleviated. - The
first gate electrode 140 may be formed to surround around an upper portion of theactive pillar 120 in which the LDD region LDD is formed. Thefirst gate electrode 140 may partially overlap a portion of the drain D, but thefirst gate electrode 140 may be formed substantially on a location of theactive pillar 120 corresponding to the LDD region LDD. - The
second gate electrode 160 may be connected to thefirst gate electrode 140 and surround the channel region of theactive pillar 120. For example, thesecond gate electrode 160 may be in contact with thefirst gate electrode 140 and located below thefirst gate electrode 140. At this time, thefirst gate electrode 140 may include a material having a work function lower than that of thesecond gate electrode 160. That is, when the work function of thefirst gate electrode 140 overlapping the LDD region LDD is lowered, high electric field characteristics causing GIDL may be alleviated, and thus the GIDL characteristics of the LDD region LDD and the drain D adjacent to the - LDD region LDD may be improved.
- At this time, a
gate insulating layer 135 may be interposed between the first andsecond gate electrodes active pillar 120. Various insulating layers such a metal oxide layer and a silicon oxide layer may be used as thegate insulating layer 135. - The
resistive memory structure 185 may be configured of alower electrode 170 and aresistive memory layer 180. Thelower electrode 170 may be a conductive layer formed on the drain D and provide a current and a voltage to theresistive memory layer 180. Although not illustrated inFIG. 1 , an ohmic layer may be interposed between thelower electrode 170 and the drain D depending on material properties of thelower electrode 170. Theresistive memory layer 180 may be a layer of which a resistance value is changed according to the voltage and current provided from thelower electrode 170. As theresistive memory layer 180, a PCMO layer that is a material for a ReRAM, a chalcogenide layer that is a material for a PCRAM, a magnetic layer that is a material for a MRAM, a magnetization reversal device layer that is a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), a polymer layer that is a material for a polymer RAM (PoRAM), or the like, may be variously used. - In the vertical transistor according to the exemplary embodiment, the gate electrode is formed of a material having a relatively lower work function in the LDD region LDD, which has a lower GIDL barrier and a high electric field is applied to, than in the channel region.
- As described above, the gate electrode having a relatively low work function is disposed around the LDD region LDD to compensate the low GIDL barrier according to application of the high electric field, and thus leakage current may be reduced.
- A method of manufacturing a resistance variable memory device including a vertical transistor will be described in detail with reference to
FIGS. 2 to 5 . - Referring to
FIG. 2 , asource 110 is formed in asemiconductor substrate 105 by implementing impurities into an upper portion of thesemiconductor substrate 105. A semiconductor layer is formed on thesemiconductor substrate 105 in which thesource 110 is formed. For example, the semiconductor layer may be an impurity-doped polysilicon layer or a layer that epitaxially grows thesemiconductor substrate 105 in which the source is formed. Ahard mask layer 130, for example, a silicon nitride layer is deposited on the semiconductor layer. Predetermined portions of thehard mask layer 130 and the semiconductor layer are patterned to form a plurality ofactive pillars 120. Agate insulating layer 135 is formed on surfaces of the plurality ofactive pillars 120 and thesemiconductor substrate 105. As thegate insulating layer 135, a layer in which a conductive material such as silicon (Si) tantalum (Ta), titanium (Ti), barium titanium (BaTi), barium zirconium (BaZr), zirconium (Zr), hafnium (Hf), lanthanum (La), aluminum (Al), yttrium (Y), or zirconium silicide (ZrSi) is oxidized, may be used. A first conductive layer is deposited on thesemiconductor substrate 105 including thegate insulating layer 135, and anisotropically etched to surround theactive pillar 120. Therefore, afirst gate electrode 140 is formed over an outer circumference of each of theactive pillar 120 covered with thegate insulating layer 135. At this time, by anisotropic over-etching, thefirst gate electrode 140 may be formed to have a height lower than that of theactive pillar 120. For example, as thefirst gate electrode 140, a transition metal layer including a metal such as Ti, Ta, cobalt (co), or platinum (Pt) may be used. - As illustrated in
FIG. 3 , a first insulatinglayer 145 is formed to fill a space between theactive pillars 120. Next, the first insulatinglayer 145 is recessed to expose an upper region of thefirst gate electrode 140. At this time, an upper surface of the first insulatinglayer 145 may be located to correspond to a channel formation region of theactive pillar 120. A second insulatinglayer 150 is formed to cover the exposed upper region of thefirst gate electrode 140. The secondinsulating layer 150 may be formed of a material having an etch selectivity different from that of the first insulatinglayer 145. - Referring to
FIG. 4 , the first insulatinglayer 145 is selectively removed to expose a lower region of thefirst gate electrode 140. Next, nitrogen ions are implanted into the exposedfirst gate electrode 140 to form asecond gate electrode 160 formed of a metal nitride layer, for example, a titanium nitride (TiN) layer as illustrated inFIG. 5 . As known, a refractory metal layer such as a Ti layer has a work function lower than that of a metal nitride layer such as a TiN layer. Therefore, a portion of the gate electrode corresponding to an LDD region LDD is formed of a material having a relatively low work function, and thus leakage current due to GIDL may be reduced. - Next, referring back to
FIG. 1 , thehard mask layer 130 on theactive pillar 120 is removed, and the LDD region LDD is formed by implanting impurities having a low concentration into theactive pillar 120. Subsequently, impurities having a high concentration are implanted in theactive pillar 120 in which the LDD region LDD is formed to define a drain D. - A
lower electrode 170 and aresistive memory layer 180 are sequentially formed on the drain D to fabricate the resistance variable memory device. - A metal silicide layer other than the metal nitride layer may be used as the
second gate electrode 160. - That is, as illustrated in
FIG. 6 , afirst gate electrode 140 surrounding the LDD region LDD may be formed of a transition metal layer like examples in the above-described exemplary embodiment, and asecond gate electrode 165 may be formed of a transition metal silicide layer located below thefirst gate electrode 140 and having a work function higher than that of thefirst gate electrode 140. At this time, a thickness b of thesecond gate electrode 165 may be larger than a thickness a of thefirst gate electrode 140. - Since the transition metal layer also has a work function lower than that of the transition metal silicide layer, leakage current around the LDD region LDD having weak GIDL characteristic may be reduced.
- A method of manufacturing the vertical transistor illustrated in
FIG. 6 will be described in detail with reference toFIGS. 7 and 8 . Here, some of the manufacturing method of the resistance variable memory device in the exemplary embodiment are substantially the same as the processes ofFIGS. 1 to 3 in the manufacturing method of the resistance variable memory device in the above-described exemplary embodiment, and thus processes subsequent to the process ofFIG. 3 will be described. - Referring to
FIG. 7 , the first insulating layer (145 ofFIG. 3 ) is selectively removed to expose a sidewall of thefirst gate electrode 140. Asilicon layer 163 is deposited on an exposed surface of thefirst gate electrode 140 to a predetermined thickness. Thesilicon layer 163 may be formed to be located below a second insulatinglayer 150. - Referring to
FIG. 8 , a heat treatment is performed on thesemiconductor substrate 105 so that thefirst gate electrode 140 is reacted with thesilicon layer 163 in contact with thefirst gate electrode 140 to form thesecond gate electrode 165 formed of a transition metal silicide layer. At this time, since thesecond gate electrode 165 is a layer formed through the heat reaction of thefirst gate electrode 140 with thesilicon layer 163, a thickness of thesilicon layer 163 may be provided as a thickness of thesecond gate electrode 165. Therefore, thesecond gate electrode 165 may have a thickness larger than that of thefirst gate electrode 140. - As illustrated in
FIG. 9 , first andsecond gate electrodes active pillar 120. - That is, the
first gate electrode 142 is formed to surround an outer circumference of theactive pillar 120 covered with thegate insulating layer 135. At this time, it is important that thefirst gate electrode 142 is formed not to overlap an LDD region LDD. - Next, the
second gate electrode 167 is formed to surround an outer circumference of thegate electrode 142. At this time, thesecond gate electrode 167 may extend by a predetermined length c more than thefirst gate electrode 142 so that thesecond gate electrode 167 overlap a portion of the LDD region LDD. Therefore, for example, only a portion of the insulatinglayer 135 is present between the LDD region LDD and thesecond gate electrode 167 without interposing of thefirst gate electrode 142. Here, thesecond gate electrode 167 may have a work function higher than that of thefirst gate electrode 142. However, in some cases, thesecond gate electrode 167 may be formed of a material having a work function similar to or lower than that of thefirst gate electrode 142. - In the vertical transistor having the above-described structure, since the
first gate electrode 142 is formed to have a relatively low work function and a distance between the LDD region LDD and thesecond gate electrode 167 overlapping the LDD region LDD is increased, a high electric field applied to the LDD region LDD may be alleviated and leakage current due to low GIDL may be reduced. - In addition to the vertical transistor structure, the dual gate electrode structure may be applied to a buried gate electrode structure.
- That is, as illustrated in
FIG. 10 , atrench 210 is formed in asemiconductor substrate 200. A source S and a drain D are formed in thesemiconductor substrate 200 at both sides of thetrench 210. - A
first electrode 220 and asecond electrode 230 may be formed in thetrench 210 in which agate insulating layer 215 is formed. Thefirst gate electrode 220 may be formed on an inner surface of thetrench 210. Thefirst gate electrode 220 may be formed to be located substantially in a lower portion of thetrench 210 so that thefirst gate electrode 220 may not overlap the source S and the drain D. - The
second gate electrode 230 may be formed to fill the inside of thetrench 210 surrounded with thefirst gate electrode 220. At this time, thesecond gate electrode 230 may be formed to have a height longer than that of thefirst gate electrode 220 so that thesecond gate electrode 230 may overlap portions of the source S and the drain D. - Although not shown in
FIG. 10 , it would have been obvious to a person having ordinary skill in the art that theresistive memory structure 185 illustrated inFIGS. 2 and 6 may be additionally formed. Thereference numerals - Therefore, a region around the drain D overlaps the
second gate electrode 230 without interposing of thefirst gate electrode 220 Accordingly, a distance of the region around the drain affected by the high electric field to the gate electrode is substantially increased so that the GIDL effect may be reduced. - Further, since the
first gate electrode 220 is formed of a material having a work function lower than that of thesecond gate electrode 230, an effect of the electric field on the region around the drain D, that is, a region corresponding to the LDD region LDD may be further alleviated. - Further, the
second gate electrode 230 may be formed to fill the inside of thetrench 210 surrounded with thefirst gate electrode 220. - As specifically described above, according to the exemplary embodiments, since the gate electrode having a relatively low work function is formed around the LDD region LDD, the low GIDL barrier due to application of a high electric field may be compensated and the leakage current may be reduced.
- The above embodiments of the present invention are illustrative, and the invention is not limited by the embodiments described above. Various alternatives and equivalents are possible, and the invention is not limited to any specific type of semiconductor device. Other additions, subtractions, or modifications may be made in view of the present disclosure and are intended to fall within the scope of the following claims.
Claims (21)
1. A transistor, comprising:
an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region;
a first gate electrode formed to surround a periphery of the LDD region and having a first work function; and
a second gate electrode formed to be connected to the first gate electrode and to surround the channel region, and having a second work function that is higher than the first work function.
2. The transistor of claim wherein the first gage electrode includes a transition metal layer including one selected from the group comprising titanium (Ti), tantalum (Ta), cobalt (Co), and platinum (Pt).
3. The transistor of claim 2 , wherein the second gate electrode includes a metal nitride layer.
4. The transistor of claim 2 , wherein the second gate electrode includes a transition metal silicide layer.
5. The transistor of claim 4 , wherein the second gate electrode is formed to have a thickness larger than a thickness of the first gate electrode.
6. The transistor of claim 1 , wherein the first gate electrode is formed on an outer circumference of the active pillar, and the second gate electrode is formed on an outer circumference of the first gate electrode.
7. The transistor of claim 6 , wherein the first gate electrode is formed to have a height shorter than that of the second gate electrode, and the second gate electrode is formed to overlap the active pillar without interposing of the first gate electrode.
8. A resistance variable memory device, comprising:
a vertical transistor including
an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region,
a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and
a second gate electrode formed to be connected to the first gate electrode and to surround the channel region, and having a second work function that is higher than the first work function; and
a resistive memory structure connected to the drain of the vertical transistor.
9. The resistance variable memory device of claim 8 , wherein the first gage electrode includes a transition metal layer including any one selected from the group comprising titanium (Ti), tantalum (Ta), cobalt (Co), and platinum (Pt).
10. The resistance variable memory device of claim wherein the second gate electrode includes a metal nitride layer.
11. The resistance variable memory device of claim 8 , wherein the second gate electrode includes a transition metal silicide layer.
12. The resistance variable memory device of claim 8 , wherein the second gate electrode is formed to have a thickness larger than a thickness of the first gate electrode.
13. The resistance variable memory device of claim 8 , wherein the first gate electrode is formed on an outer circumference of the active pillar, and the second gate electrode is formed on an outer circumference of the first gate electrode.
14. The resistance variable memory device of claim 13 , wherein the first gate electrode is formed to have a height shorter than that of the second gate electrode, and the second gate electrode is formed to overlap the active pillar without interposing of the first gate electrode.
15. The resistance variable memory device of claim 8 , wherein the resistive memory structure includes:
a lower electrode formed on the drain; and
a resistive memory layer formed on the lower electrode.
16. The resistance variable memory device of claim 15 , wherein the resistive memory layer includes one selected from the group comprising a PCMO layer including a material for a resistance random access memory (ReRAM), a chalcogenide layer including a material for a phase-change RAM (PCRAM), a magnetic layer including a material for a magentoresistive RAM (MRAM), a magnetization reversal device layer including a material for a spin-transfer torque magnetoresistive RAM (STTMRAM), and a polymer layer including a material for a polymer RAM (PoRAM).
17. A method of manufacturing a resistance variable memory device, comprising:
forming a source region in a semiconductor substrate;
forming a semiconductor layer on the source region;
patterning the semiconductor layer to form an active pillar;
forming a first gate electrode to surround the active pillar;
surrounding an upper region of the first gate electrode with an insulating layer while exposing a lower region of the first gate electrode; and
forming a second gate electrode by increasing a work function of the exposed first gate electrode.
18. The method of claim 17 , wherein the forming of the second gate electrode includes implanting nitrogen ions into the exposed lower region of the first gate electrode.
19. The method of claim 17 , wherein the forming of the second gate electrode includes:
forming a silicon layer on the exposed lower region of the first gate electrode; and
forming a silicide layer by reacting the first gate electrode and the silicon layer.
20. The method of claim 17 , further comprising
forming a lower electrode on the active pillar; and
forming a resistive memory layer on the lower electrode.
21. A transistor, comprising:
an active pillar including a channel region, a source formed at one an end of the channel region, a drain and a lightly doped drain (LDD) region formed at the other end of the channel region;
a first gate electrode formed to surround the LDD region and having a first work function; and
a second gate electrode formed to surround the channel region and having a second work function higher than the first work function.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/634,121 US9196655B2 (en) | 2013-02-27 | 2015-02-27 | Transistor, resistance variable memory device including the same, and manufacturing method thereof |
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US14/920,622 US9431461B2 (en) | 2013-02-27 | 2015-10-22 | Transistor having a vertical channel |
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Also Published As
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US9419055B2 (en) | 2016-08-16 |
KR20140106903A (en) | 2014-09-04 |
US9196655B2 (en) | 2015-11-24 |
CN104009082B (en) | 2018-03-30 |
TW201434154A (en) | 2014-09-01 |
US20150171143A1 (en) | 2015-06-18 |
TWI595658B (en) | 2017-08-11 |
US9431461B2 (en) | 2016-08-30 |
US20160049446A1 (en) | 2016-02-18 |
US20160043139A1 (en) | 2016-02-11 |
CN104009082A (en) | 2014-08-27 |
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