CN103985627B - 提高tmbs良率的工艺方法 - Google Patents

提高tmbs良率的工艺方法 Download PDF

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CN103985627B
CN103985627B CN201410198290.5A CN201410198290A CN103985627B CN 103985627 B CN103985627 B CN 103985627B CN 201410198290 A CN201410198290 A CN 201410198290A CN 103985627 B CN103985627 B CN 103985627B
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王西政
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Shanghai Advanced Semiconductor Manufacturing Co Ltd
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Abstract

本发明提出了一种提高TMBS良率的工艺方法，栅极形成之后，在栅极的表面依次形成第一阻挡介质层、第二阻挡介质层和层间介质层，因此刻蚀去除较厚的层间介质层时，由第一阻挡介质层和第二阻挡介质层保护，不会对栅介质层造成损伤，再依次刻蚀去除第二阻挡介质层和第一阻挡介质层时，由于第一阻挡介质层较薄，一方面形成第一阻挡介质层的均匀性差异较小，另一方面刻蚀时间得以大大缩短，避免了沟槽侧壁栅介质层过刻蚀或介质层残留的问题。形成较薄的第一阻挡介质层能够降低对设备机台要求，同时减少了沟槽侧壁栅介质层的损伤，增大工艺窗口，能够提高TMBS的良率。

Description

提高TMBS良率的工艺方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种提高TMBS良率的工艺方法。
背景技术
势垒肖特基二极管(Trench Mos Barrier Schottky，TMBS)，又称为金属-半导体二极管，是近年来间世的低功耗、大电流、超高速半导体器件。TMBS用某些金属和半导体相接触，在它们的交界面处便会形成一个势垒区(通常称为“表面势垒”或“肖特基势垒”)，产生整流、检波作用。由于肖特基二极管中少数载流子的存贮效应甚微，所以其频率响应仅被RC时间常数限制，因而，它是高频和快速开关的理想器件。
请参考图1至图5，图1至图5为现有技术中TMBS制作过程中形成栅介质层和栅极的剖面示意图。形成栅介质层和栅极的步骤包括：
S1：提供半导体衬底10，所述半导体衬底10可以为硅衬底；
S2：在所述半导体衬底10上形成硬掩模层20；
S3：依次刻蚀所述硬掩模层20和半导体衬底10，在所述半导体衬底10内形成多个沟槽(Trench)11，如图1所示；
S4：在所述沟槽11的侧壁表面形成栅介质层30，其中，形成栅介质层30的步骤包括：先在所述沟槽11的侧壁表面形成牺牲氧化层(图未示出)，接着对所述牺牲氧化层进行氢氟酸清洗(HF Dip)，去除所述牺牲氧化层，接着再形成栅介质层30，如图2所示；
S5：在所述沟槽11内、所述栅介质层30以及硬掩模层20的表面上形成栅极层，接着对栅极层进行刻蚀形成栅极40，刻蚀暴露出硬掩模层20并且使所述栅极40与所述栅介质层30顶部保持相同高度，如图3所示；
S6：在所述硬掩膜层20、栅介质层30以及栅极40的表面形成层间介质层50，并且对层间介质层50进行致密化处理(Densify)，如图4所示；
S7：依次刻蚀所述层间介质层50和硬掩模层20，形成通孔连线区，所述通孔连线区暴露出所述栅极40以及部分半导体衬底10，以方便后续形成通孔连线，如图5所示。
在步骤S7中，采用的是干法刻蚀依次刻蚀层间介质层50和硬掩模层20，干法刻蚀即采用刻蚀气体的等离子体(Plasma)进行刻蚀。然而，常规的Plasma刻蚀在刻蚀表面的10000埃的介质层时需要刻蚀180s，由于设备机台反应腔室中的Plasma分布不均匀，位于反应腔室中心区域的Plasma浓度高于位于边缘区域的浓度，因此，导致Plasma在刻蚀中心区域介质层的速率高于刻蚀边缘区域介质层的速率，这就造成Plasma刻蚀介质层时每分钟有200埃左右的均匀性差异，那么180s的刻蚀将会造成至少600埃均匀性的偏差。
通常情况下，形成的层间介质层50较厚，通常为10000埃，由于设备机台的限制，导致形成如此厚的层间介质层50本身就存在一定的均匀性问题，生长10000埃的层间介质层50会有800埃的均匀性偏差，加上刻蚀带来的600埃的偏差，这样累计后将会有1400埃的均匀性偏差。这也就是说，在在步骤S7中刻蚀去除层间介质层50和硬掩模层20后，半导体衬底10上要么会存在1400埃的介质层的残留，要么一部分介质层被过刻蚀1400埃。请参考图5，为了完全刻蚀通孔区域的层间介质层50和硬掩模层20，采用了过刻蚀法，即延长刻蚀时间，然而，却对沟槽11侧壁的栅介质层30过刻蚀，如图5中虚线圈所示。
而沟槽11侧壁的栅介质层30不允许超过1200埃的过刻，否则会影响器件的良率；若减少刻蚀量，会存在介质层的残留，同样会影响良率。
发明内容
本发明的目的在于提供一种提高TMBS良率的工艺方法，能够解决沟槽侧壁栅介质层过刻蚀或介质层残留的问题，提高TMBS的良率。
为了实现上述目的，本发明提出了一种提高TMBS良率的工艺方法，所述方法包括步骤：
提供半导体衬底，所述半导体衬底上形成有多个沟槽；
在所述半导体衬底的表面及沟槽内表面均形成栅介质层；
在所述沟槽内形成栅极，所述栅极形成于沟槽内栅介质层的表面并且与沟槽顶部高度一致；
在所述栅极表面依次形成第一阻挡介质层、第二阻挡介质层以及层间介质层；
依次刻蚀所述层间介质层、第二阻挡介质层和第一阻挡介质层，形成通孔区域。
进一步的，所述沟槽的形成步骤包括：
在所述半导体衬底表面形成硬掩模层；
在所述硬掩模层上形成图案化的光阻层；
以所述图案化的光阻层和硬掩模层为掩模，刻蚀形成多个沟槽。
进一步的，在形成多个沟槽之后，去除所述硬掩模层，暴露出所述沟槽的顶部。
进一步的，在所述半导体衬底的表面及沟槽内表面均形成栅介质层的步骤包括：
在所述半导体衬底的表面及沟槽内表面均形成一层牺牲介质层；
使用酸液清洗去除所述牺牲介质层；
在所述半导体衬底的表面及沟槽内表面均形成栅介质层。
进一步的，所述牺牲介质层的材质为氧化硅，所述酸液为氢氟酸。
进一步的，所述栅介质层的材质为氧化硅，采用热氧化法形成。
进一步的，在所述沟槽内形成栅极的步骤包括：
在所述栅介质层表面形成栅极层；
刻蚀所述栅极层，形成栅极，刻蚀暴露出所述沟槽的顶部。
进一步的，所述第一阻挡介质层的材质为氧化硅，采用热氧化法在所述栅极的表面形成。
进一步的，所述第一阻挡介质层的厚度范围是500埃～1000埃。
进一步的，采用干法刻蚀对所述第一阻挡介质层进行刻蚀。
进一步的，所述第二阻挡介质层的材质为氮化硅，采用化学气相沉积形成。
进一步的，所述第二阻挡介质层的厚度范围是500埃～700埃。
进一步的，采用干法刻蚀对所述第二阻挡介质层进行刻蚀。
进一步的，所述层间介质层的材质为氧化硅，采用化学气相沉积形成。
进一步的，所述层间介质层的厚度范围是3000埃～5000埃。
进一步的，采用湿法刻蚀对所述层间介质层进行刻蚀。
与现有技术相比，本发明的有益效果主要体现在：栅极形成之后，在栅极的表面依次形成第一阻挡介质层、第二阻挡介质层和层间介质层，因此刻蚀去除较厚的层间介质层时，由第一阻挡介质层和第二阻挡介质层保护，不会对栅介质层造成损伤，再依次刻蚀去除第二阻挡介质层和第一阻挡介质层时，由于第一阻挡介质层较薄，一方面形成第一阻挡介质层的均匀性差异较小，另一方面刻蚀时间得以大大缩短，避免了沟槽侧壁栅介质层过刻蚀或介质层残留的问题。形成较薄的第一阻挡介质层能够降低对设备机台要求，同时减少了沟槽侧壁栅介质层的损伤，增大工艺窗口，能够提高TMBS的良率。
附图说明
图1至图5为现有技术中TMBS制作过程中的剖面示意图；
图6为本发明一实施例中提高TMBS良率工艺方法的流程图；
图7至图13为发明一实施例中TMBS制作过程中的剖面示意图。
具体实施方式
下面将结合示意图对本发明的提高TMBS良率的工艺方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图6，在本实施例中，提出了一种提高TMBS良率的工艺方法，所述方法包括步骤：
S100：提供半导体衬底100，所述半导体衬底100上形成有多个沟槽110；
S200：在所述半导体衬底100的表面及沟槽110内表面均形成栅介质层300；
S300：在所述沟槽110内形成栅极400，所述栅极400形成于沟槽110内栅介质层300的表面并且与沟槽110顶部高度一致；
S400：在所述栅极400表面依次形成第一阻挡介质层510、第二阻挡介质层520以及层间介质层600；
S500：依次刻蚀所述层间介质层600、第二阻挡介质层520和第一阻挡介质层510，形成通孔区域700。
在步骤S100中，所述半导体衬底100可以为单晶硅、多晶硅或绝缘体上硅等衬底，所述沟槽110的形成步骤包括：
在所述半导体衬底100的表面形成硬掩模层(Hard mask)200，如图7所示，所述硬掩模层200可以为热氧化法形成的氧化硅和采用四乙氧基硅烷(TEOS)形成的氧化硅的复合层；
在所述硬掩模层200上形成图案化的光阻层；
以所述图案化的光阻层和硬掩模层200为掩模，刻蚀所述半导体衬底100形成多个沟槽110。
在本实施例中，所述沟槽110形成之后，可以刻蚀去除所述硬掩模层200，暴露出所述沟槽110的顶部，即所述硬掩模层200之前覆盖的区域。去除所述硬掩模层200能够减少后续形成的层间介质层和硬掩模层200叠加的厚度，减少两者均匀性差异的叠加，即提高后续形成的层间介质层的均匀性。
在步骤S200中，在所述半导体衬底100的表面及沟槽110内表面均形成栅介质层300的步骤包括：
在所述半导体衬底100的表面及沟槽110内表面均形成一层牺牲介质层，所述牺牲介质层的材质为氧化硅，可以采用热氧化法形成；
使用酸液清洗去除所述牺牲介质层，在本实施例中，所述酸液为氢氟酸；
在所述半导体衬底100的表面及沟槽110内表面均形成栅介质层300，如图8所示，所述栅介质层300的材质为氧化硅，采用热氧化法形成。
形成牺牲氧化层后，接着去除牺牲氧化层，最后再形成栅介质层300的目的是，采用此种方式能够对沟槽110的侧壁以及底部进行缺陷修复，便于更好的形成栅介质层300，得到可靠性较高的栅介质层300。
在步骤S300中，在所述沟槽110内形成栅极400的步骤包括：
在所述栅介质层300的表面形成栅极层；
刻蚀所述栅极层，形成栅极400，如图9所示，刻蚀暴露出所述沟槽110的顶部，确保所述栅极400位于所述沟槽110内，并且与所述沟槽110的顶部高度一致。
在步骤S400中，先采用热氧化法在所述栅极400的表面形成第一阻挡介质层510，所述第一阻挡介质层510的材质为氧化硅，其厚度范围是500埃～1000埃，例如是800埃；然后再采用化学气相沉积在所述第一阻挡介质层510和部分栅介质层300的表面形成第二阻挡介质层520，所述第二阻挡介质层520的材质为氮化硅，其厚度范围是500埃～700埃，例如是600埃；然后在所述第二阻挡介质层520的表面采用化学气相沉积形成层间介质层600，如图10所示，所述层间介质层600的材质为氧化硅，其厚度范围是3000埃～5000埃，例如是4000埃，在形成层间介质层600后，再对其进行致密化处理。
由于所述栅极400上有第一阻挡介质层510和第二阻挡介质层520保护，因此，所述层间介质层600无需生长过厚，这也有利于提高其表面的均匀性，降低均匀性差异。接着，在步骤S500中，先在所述层间介质层600的表面涂覆图案化的光阻，再以所述图案化的光阻为掩模，采用湿法刻蚀对所述层间介质层600进行刻蚀，形成通孔区域700，如图11所示。同样的，所述第二阻挡介质层520能够作为层间介质层600的刻蚀阻挡层。
在去除通孔区域700的层间介质层600之后，再采用干法刻蚀去除所述第二阻挡介质层520，如图12所示，同样的，所述第一阻挡介质层510可以作为刻蚀阻挡层，保护所述栅极400。
在去除通孔区域700的第二阻挡介质层520之后，再使用干法刻蚀去除位于栅极400表面的第一阻挡介质层510以及位于半导体衬底100表面的部分栅介质层300，如图13所示，由于所述第一阻挡介质层510和栅介质层300的材质均为氧化硅，因此可以同时去除，并且，由于第一阻挡介质层510的厚度不足1000埃，刻蚀时间大大缩短，并且其均匀性差异较小，这样刻蚀较为均匀，能够减少对位于沟槽110侧壁处的栅介质层300(如图13中虚线框所示)造成的损伤，同时也可以避免刻蚀不足导致位于半导体衬底100表面的介质层存在残留的现象，因而能够提高形成的TMBS器件的良率。
综上，在本发明实施例提供的提高TMBS良率的工艺方法中，栅极形成之后，在栅极的表面依次形成第一阻挡介质层、第二阻挡介质层和层间介质层，因此刻蚀去除较厚的层间介质层时，由第一阻挡介质层和第二阻挡介质层保护，不会对栅介质层造成损伤，再依次刻蚀去除第二阻挡介质层和第一阻挡介质层时，由于第一阻挡介质层较薄，一方面形成第一阻挡介质层的均匀性差异较小，另一方面刻蚀时间得以大大缩短，避免了沟槽侧壁栅介质层过刻蚀或介质层残留的问题。形成较薄的第一阻挡介质层能够降低对设备机台要求，同时减少了沟槽侧壁栅介质层的损伤，增大工艺窗口，能够提高TMBS的良率。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (16)

1.一种提高TMBS良率的工艺方法，所述方法包括步骤：
提供半导体衬底，所述半导体衬底上形成有多个沟槽；
在所述半导体衬底的表面及沟槽内表面均形成栅介质层；
在所述沟槽内形成栅极，所述栅极形成于沟槽内栅介质层的表面并且与沟槽顶部高度一致；
在所述栅极表面依次形成第一阻挡介质层、第二阻挡介质层以及层间介质层；
依次刻蚀所述层间介质层、第二阻挡介质层和第一阻挡介质层，形成通孔区域，其中，在所述第一阻挡层的刻蚀工艺中，其对栅介质层的刻蚀速率大于对半导体衬底和栅极的刻蚀速率。
2.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，所述沟槽的形成步骤包括：
在所述半导体衬底表面形成硬掩模层；
在所述硬掩模层上形成图案化的光阻层；
以所述图案化的光阻层和硬掩模层为掩模，刻蚀形成多个沟槽。
3.如权利要求2所述的提高TMBS良率的工艺方法，其特征在于，在形成多个沟槽之后，去除所述硬掩模层，暴露出所述沟槽的顶部。
4.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，在所述半导体衬底的表面及沟槽内表面均形成栅介质层的步骤包括：
在所述半导体衬底的表面及沟槽内表面均形成一层牺牲介质层；
使用酸液清洗去除所述牺牲介质层；
在所述半导体衬底的表面及沟槽内表面均形成栅介质层。
5.如权利要求4所述的提高TMBS良率的工艺方法，其特征在于，所述牺牲介质层的材质为氧化硅，所述酸液为氢氟酸。
6.如权利要求4所述的提高TMBS良率的工艺方法，其特征在于，所述栅介质层的材质为氧化硅，采用热氧化法形成。
7.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，在所述沟槽内形成栅极的步骤包括：
在所述栅介质层表面形成栅极层；
刻蚀所述栅极层，形成栅极，刻蚀暴露出所述沟槽的顶部。
8.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，所述第一阻挡介质层的材质为氧化硅，采用热氧化法在所述栅极的表面形成。
9.如权利要求8所述的提高TMBS良率的工艺方法，其特征在于，所述第一阻挡介质层的厚度范围是500埃～1000埃。
10.如权利要求9所述的提高TMBS良率的工艺方法，其特征在于，采用干法刻蚀对所述第一阻挡介质层进行刻蚀。
11.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，所述第二阻挡介质层的材质为氮化硅，采用化学气相沉积形成。
12.如权利要求11所述的提高TMBS良率的工艺方法，其特征在于，所述第二阻挡介质层的厚度范围是500埃～700埃。
13.如权利要求12所述的提高TMBS良率的工艺方法，其特征在于，采用干法刻蚀对所述第二阻挡介质层进行刻蚀。
14.如权利要求1所述的提高TMBS良率的工艺方法，其特征在于，所述层间介质层的材质为氧化硅，采用化学气相沉积形成。
15.如权利要求14所述的提高TMBS良率的工艺方法，其特征在于，所述层间介质层的厚度范围是3000埃～5000埃。
16.如权利要求15所述的提高TMBS良率的工艺方法，其特征在于，采用湿法刻蚀对所述层间介质层进行刻蚀。
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