CN103956333A - 基于中通孔制作方法的tsv、m1、ct金属层一次成型方法 - Google Patents

基于中通孔制作方法的tsv、m1、ct金属层一次成型方法 Download PDF

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CN103956333A
CN103956333A CN201410191709.4A CN201410191709A CN103956333A CN 103956333 A CN103956333 A CN 103956333A CN 201410191709 A CN201410191709 A CN 201410191709A CN 103956333 A CN103956333 A CN 103956333A
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李恒甫
张文奇
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

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Abstract

本发明公开了一种基于中通孔制作方法的TSV、M1、CT金属层一次成型方法，包括TSV的光刻和蚀刻，TSV光刻胶的去除和清洗；进行表面平坦化处理之后沉积接触孔CT氧化层；TSV绝缘层氧化物沉积；第一次BARC填充及刻蚀；接触孔CT光刻和蚀刻；接触孔CT光刻胶的去除和清洗；第二次BARC填充及刻蚀；金属线层M1的光刻和蚀刻；扩散阻挡层和种子层的沉积；金属导电物的填充；表面平坦化处理的步骤。本发明能够同时实现接触孔CT、硅通孔TSV和金属线层制作过程中扩散阻挡层、种子层、金属填充物的同步完成以及一次性平坦化处理，不仅提高了材料的利用率，降低了生产成本，还提高了生产效率。

Description

基于中通孔制作方法的TSV、M1、CT金属层一次成型方法
技术领域
本发明涉及微电子技术领域，特别是一种集成电路中TSV、M1、CT金属层一次成型的工艺方法。
背景技术
随着集成电路工艺的发展,除了对器件本身提出的高速、低功耗、高可靠性的性能要求之外,互连技术的发展也在越来越大的程度上影响了器件的总体性能,减少RC延迟时间（其中R是互连金属的电阻，C是和介质相关的电容）、达到和器件延迟相当的水平是一个很大的挑战。而硅通孔技术（简称TSV技术）则可有效的降低RC延时，TSV技术是通过芯片与芯片、晶圆与晶圆的之间的垂直导通来实现芯片的互连，因而它成为先进的三维系统级封装（3D SIP）集成技术乃至三维集成电路（3D IC）集成技术的核心。
当前，TSV的填充过程一般包括氧化物、阻挡层、种子层的沉积和导电物质的填充，氧化物一般用二氧化硅、氮化硅或者TEOS，阻挡层一般用Ti、TiN、Ta或TaN，导电填充物以铜为主。
在TSV制作工艺中，氧化物的沉积可在种子层形成绝缘膜，用于防止后形成的导电材料（如铜）扩散入衬底造成互连材料铜和硅基底之间形成导电通道现象的发生。
但是，由于铜在硅或其他介质中都有较好的电子迁移率，一旦铜原子进入硅器件，便会成为深能级受主杂质，从而产生复合中心使载流子寿命降低，质的介电性能严重退化，最终导致器件性能退化甚至失效。另外铜和介质的粘附性能较弱，也较易受到腐蚀。为了避免铜互连电路中的合金化，阻止填充金属（如铜）向绝缘层扩散，在种子层和绝缘膜之间必须加入一扩散阻挡层，从而提高芯片的电学可靠性和稳定性。
大多数情况下绝缘膜采用SiO2层，SiO2的形成一般采用PECVD技术。扩散阻挡层一般选择Ti、Ta及他们的氮化物等材料，可以采用溅射、PVD、ALD 等方法生长。
通常情况下，有MOS 器件的中通孔（via middle）方法做硅通孔TSV 和金属线层M1，需要在接触孔CT刻蚀、填充、机械研磨之后，再单独完成硅通孔TSV 和金属线层M1工艺，存在生产周期长、工艺步骤繁琐、成本高的缺点。
发明内容
本发明解决的技术问题是提供一种工艺简单的基于中通孔制作方法的TSV、M1、CT金属层一次成型方法。
为解决上述技术问题，本发明所采取的技术方案如下。
基于中通孔制作方法的TSV、M1、CT金属层一次成型方法，主要包括以下步骤：
步骤一：TSV的光刻和蚀刻，TSV光刻胶的去除和清洗；
步骤二：进行表面平坦化处理之后沉积接触孔CT氧化层；
步骤三：TSV 绝缘层氧化物沉积；
步骤四：第一次 BARC 填充及刻蚀；
步骤五：接触孔CT光刻和蚀刻；
步骤六：接触孔CT光刻胶的去除和清洗；
步骤七：第二次BARC 填充及刻蚀；
步骤八：金属线层M1的光刻和蚀刻；
步骤九：扩散阻挡层和种子层的沉积；
步骤十：金属导电物的填充；
步骤十一：表面平坦化处理。
由于采用了以上技术方案，本发明所取得技术进步如下。
本发明引入了类似于光刻胶非光敏性的BARC 物质，与氧化层比较，由于BARC的存在，RDL 刻蚀时， TSV不会被刻蚀影响，很好了保护了TSV的性能，因此对等离子体来说具有较高的选择比。采用本发明所述的工艺与传统的有MOS 器件的中通孔（via middle）方法做硅通孔TSV 和金属线层M1方法相比，工艺步骤减少近30%，同时实现了接触孔CT、硅通孔TSV和金属线层制作过程中扩散阻挡层、种子层、金属填充物的同步完成，实现了接触孔CT、硅通孔TSV和金属线层的一次性平坦化处理，不仅提高了材料的利用率，缩短了生产周期，降低了生产成本，还提高了生产效率。
附图说明
图1为本发明步骤三完成后形成的产品结构示意图。
图2为本发明步骤四第一次BARC 填充完成后形成的产品结构示意图。
图3为本发明第一次BARC刻蚀完成后形成的产品结构示意图。
图4为本发明步骤五完成后形成的产品结构示意图。
图5为本发明步骤七完成后形成的产品结构示意图。
图6为本发明步骤八完成后形成的产品结构示意图。
图7为本发明步骤十完成后形成的产品结构示意图。
具体实施方式
下面将结合附图和具体实施例对本发明进行进一步详细说明。
基于中通孔制作方法的TSV、M1、CT金属层一次成型方法，主要包括以下步骤：
步骤一：TSV的光刻和蚀刻，TSV光刻胶的去除和清洗：在硅衬底100上通过光刻和干蚀刻工艺，形成硅通孔TSV201；去除硅衬底上硅通孔TSV中的光刻胶，并进行清洗。
步骤二：进行表面平坦化处理之后沉积接触孔CT氧化层202。
步骤三：TSV 绝缘层氧化物沉积：在TSV硅通孔内采用PECVD方法沉积一层绝缘氧化层TEOS。此步骤完成后产品的结构如图1所示，图1中301为TSV硅通孔内绝缘氧化层，302为表面绝缘氧化层。
步骤四：第一次BARC 填充及刻蚀：在TSV硅通孔内以及硅衬底上端面填充物质BRAC，在TSV硅通孔内的物质BRAC如图2中的401所示，在硅衬底上端面的物质BRAC如图2中的402所示。然后再对物质BRAC进行刻蚀，此步骤完成后的产品结构如图3所示。
此步骤中物质BRAC可以完全填充TSV硅通孔，也可以不完全填充，但是在填充过程中应保证物质BRAC在刻蚀之后，TSV硅通孔底部的绝缘氧化层不被刻蚀，即刻蚀完成后，TSV硅通孔底部应留有足够的物质BRAC。图3中的403即为表面BARC刻蚀之后TSV硅通孔内剩余的BARC。
本发明中的物质BRAC是bottom anti-reflection coating的缩写, 多为有机物，是一种光阻类非光敏性物质，一般采用旋涂方式。
步骤五：接触孔CT 光刻和蚀刻：在步骤四所形成的产品上进行接触孔CT光刻、干蚀刻形成接触孔CT。此步骤完成后形成的产品如图4所示，其中501为接触孔CT。
步骤六：接触孔CT光刻胶的去除和清洗：去除接触孔CT上的光刻胶，并进行清洗。清洗时，连同TSV硅通孔内剩余的BRAC物质一起清洗干净。
步骤七：第二次BARC 填充及刻蚀；在TSV硅通孔内以及接触孔CT内填充物质BRAC，在TSV硅通孔内的物质BRAC如图5中的602所示，在接触孔CT内的物质BRAC如图5中的601所示。然后再对物质BRAC进行刻蚀。
步骤八：金属线层M1的光刻和蚀刻；在TSV硅通孔以及接触孔CT上方的硅衬底上进行金属线层M1的光刻、干刻蚀；完成后，进行光刻胶去除及清洗，从而形成金属线层图样，如图6所示，图6中701为与TSV硅通孔相连的金属线层，702为与CT接触孔相连的金属线层。
步骤九：扩散阻挡层和种子层的沉积：在TSV硅通孔内、CT接触孔内以及金属线层M1上进行扩散阻挡层以及种子层的沉积。扩散阻挡层的沉积方法有CVD、PVD、溅射、原子层沉积技术（ALD）等；扩散阻挡层沉积完成后，再在扩散阻挡层上沉积一层种子层，种子层的沉积方法有PVD，ALD等。
步骤十：金属导电物的填充：通过电镀等方法在种子层上填充导电金属，导电填充金属一般为铜，也可以是钨、多晶硅等其他材料。此步骤完成后的产品结构如图7所示，图7中801代表是金属线层M1沉积的扩散阻挡层，802代表TSV硅通孔内沉积的扩散阻挡层，803代表是C T接触孔内沉积的扩散阻挡层，901代表是金属线层M1的导电金属，902代表是TSV硅通孔内的导电金属，903代表CT接触孔内的导电金属。
步骤十一：最后采用CMP技术进行表面平坦化处理，即完成了基于中通孔方法制作的TSV硅通孔、CT接触孔以及金属线层M1的一次成型制作。

Claims (1)

1.基于中通孔制作方法的TSV、M1、CT金属层一次成型方法，其特征在于主要包括以下步骤：
步骤一：TSV的光刻和蚀刻，TSV光刻胶的去除和清洗；
步骤二：进行表面平坦化处理之后沉积接触孔CT氧化层；
步骤三：TSV 绝缘层氧化物沉积；
步骤四：第一次 BARC 填充及刻蚀；
步骤五：接触孔CT光刻和蚀刻；
步骤六：接触孔CT光刻胶的去除和清洗；
步骤七：第二次BARC 填充及刻蚀；
步骤八：金属线层M1的光刻和蚀刻；
步骤九：扩散阻挡层和种子层的沉积；
步骤十：金属导电物的填充；
步骤十一：表面平坦化处理。
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US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

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US20050170625A1 (en) * 2004-01-29 2005-08-04 Chartered Semiconductor Manufacturing Ltd. Novel method to control dual damascene trench etch profile and trench depth uniformity
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Publication number Priority date Publication date Assignee Title
US9892970B2 (en) 2016-06-02 2018-02-13 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
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