CN103928445A - 芯片装置和用于形成芯片装置的方法 - Google Patents

芯片装置和用于形成芯片装置的方法 Download PDF

Info

Publication number
CN103928445A
CN103928445A CN201410019452.4A CN201410019452A CN103928445A CN 103928445 A CN103928445 A CN 103928445A CN 201410019452 A CN201410019452 A CN 201410019452A CN 103928445 A CN103928445 A CN 103928445A
Authority
CN
China
Prior art keywords
chip
carrier
ltcc
sheet
ltcc sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410019452.4A
Other languages
English (en)
Other versions
CN103928445B (zh
Inventor
R.奥特伦巴
M.赛布特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103928445A publication Critical patent/CN103928445A/zh
Application granted granted Critical
Publication of CN103928445B publication Critical patent/CN103928445B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及芯片装置和用于形成芯片装置的方法。提供了一种芯片装置，该芯片装置包括：载体；包括至少一个接触焊盘的至少一个芯片，其设置在载体上；密封材料，其至少部分地围绕所述至少一个芯片和所述载体；以及至少一个低温共烧陶瓷片，其设置在所述载体的侧面上。

Description

芯片装置和用于形成芯片装置的方法
技术领域
各种实施例一般地涉及芯片装置和用于形成芯片装置的方法。
背景技术
图1A示出了基于模制的热沉隔离的图示。例如晶体管外形TO芯片封装的芯片封装可包括背面隔离，例如如108所指示的形成于引线框架102的背面上的密封材料。具有典型厚度的背面隔离可导致比没有背面隔离的TO芯片封装更坏的热耗散性能。图1B示出了具有不同背面隔离厚度的芯片封装的针对芯片面积121（mm2）的热电阻119（K/W）：无背面隔离111；约500μm厚的背面隔离113；约600μm厚的背面隔离115；以及约800μm厚的背面隔离117。例如，如113所示的正常地约500μm的背面隔离的典型密封厚度遭受比例如如111所示的没有背面隔离的芯片封装大得多的热阻，并且因此显示出比没有背面隔离更差的热耗散。
低温共烧陶瓷（LTCC）技术可将HTCC（高温共烧陶瓷）与传统上可能已在常规印刷电路板（PCB）技术中使用的厚膜技术的益处相组合。可将低温共烧陶瓷用于多片/多层电路装置。可以使用单层或多层LTCC片材来生产诸如电容器、电阻器和电感器的部件，例如通过印刷，例如通过丝网印刷和/或光化学工艺。LTCC片材可适合于压印电阻器和/或其他电子部件。例如，利用丝网印刷工艺，可在LTCC表面上印刷导电膏，其产生电路所必需的电阻器和/或电子部件。此类电子部件可不同于所有其额定值（±25%），并且因此可能是过大的印刷品。通过利用激光修整和使用不同的切割样式，可对电阻器和/或电子部件进行修整直至它们达到它们的精确电阻值（±1%）。LTCC片材也可用在微流体领域中，其中，作为玻璃衬底的替代，可构造三维结构。
LTCC片材与氧化铝（厚膜技术）相比可具有相对差的热传导性，并且因此常常与热过孔一起使用。LTCC片材可用在诸如高频无线、卫星、微波系统以及医疗技术和汽车行业（转向）的应用中。
发明内容
各种实施例提供了一种芯片装置，包括：载体；包括至少一个接触焊盘的至少一个芯片，其设置于载体上；密封材料，其至少部分地围绕所述至少一个芯片和所述载体；以及至少一个低温共烧陶瓷片，其设置于载体的侧面上。
附图说明
在附图中，相同的附图标记贯穿不同的视图一般地指代相同的部分。附图不一定是按比例的，而是一般地着重于图示本发明的原理。在以下描述中，参考以下各图来描述发明的各种实施例，在所述图中：
图1A和1B示出了多芯片封装；
图2示出了根据实施例的芯片装置；
图3A-3D示出了根据实施例的芯片装置；
图4示出了根据实施例的用于形成芯片装置的方法。
具体实施方式
以下详细描述参考以图示的方式示出特定细节和其中可实践本发明的实施例的附图。
词语“示例性”在本文中用来意指“充当示例、实例或图示”。不一定要将在本文中被描述为“示例性”的任何实施例或设计理解为相对于其他实施例或设计是优选的或有利的。
关于在侧面或表面“之上”形成的沉积材料所使用的词语“之上”在本文中可用来意指可“直接在”暗示的侧面或表面“上”（例如与之直接接触）形成该沉积材料。关于在侧面或表面“之上”形成的沉积材料所使用的词语“之上”在本文中可用来意指可“间接地在”暗示的侧面或表面“上”形成该沉积材料，其中在暗示的侧面或表面与该沉积材料之间布置有一个或多个附加层。
图2示出了根据实施例的芯片装置210。
芯片装置210可包括：载体202；例如半导体管芯的至少一个芯片204，其包括至少一个接触焊盘206，被设置于载体202上；密封材料208，其至少部分地围绕至少一个芯片204和载体202；以及至少一个低温共烧陶瓷（LTCC）片212，其设置于载体202的侧面上。
图3A示出了根据实施例的芯片装置310。
芯片装置310可包括：载体202。载体202可包括引线框架的至少一部分。载体202可包括引线框架材料，该引线框架材料包括来自以下材料组的至少一种，该材料组包括：铜、镍、铁、铜合金、镍合金、铁合金。可将载体202构造成保持或承载芯片且可包括例如散热器。载体202可包括范围从约0.5 mm至约3 mm（例如约1mm至约2mm）的厚度。
可在载体202上设置包括至少一个接触焊盘206的至少一个芯片204。至少一个芯片204可包括功率半导体芯片、半导体逻辑芯片和半导体存储器芯片中的至少一个。
芯片装置210可包括例如可包括半导体逻辑芯片的第一芯片204A，其中，该半导体逻辑芯片可包括来自包括以下各项的组的至少一个半导体逻辑器件：专用集成电路芯片、驱动器、控制器、传感器。
芯片装置210可包括例如第二芯片204B，其可包括功率半导体芯片，其中，该功率半导体芯片可包括来自包括以下各项的组的至少一个功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅双极晶体管、闸流晶体管、MOS受控闸流晶体管、硅控整流器、肖特基功率二极管、碳化硅二极管、氮化镓器件。
至少一个芯片204可包括多个芯片，例如一个或两个或更多芯片，例如芯片204A、204B。可例如经由粘合剂、例如经由焊料材料将至少一个芯片204粘附于载体202。例如，可将可能要求导电背面的至少一个芯片、例如芯片204B经由其背面、例如经由导电介质314（例如导电粘合剂和/或导电焊料材料）电连接到载体202。
可将密封材料208设置于至少一个芯片204上，其中，密封材料208可至少部分地围绕至少一个芯片204和载体202。密封材料208可包括来自下组材料的至少一种，该组包括：填充的或未填充的环氧树脂、预先浸渍复合纤维、加强纤维、层压材料、模制材料、热固材料、热塑性材料、填料颗粒、纤维加强层压材料、纤维加强聚合物层压材料、具有填料颗粒的纤维加强聚合物层压材料。
可在至少一个芯片204上和在至少一个芯片的一个或多个侧壁316上形成密封材料208。此外，可在至少一个芯片204上和载体202的一个或多个侧壁318上形成密封材料208。可将至少一个导线322电连接到至少一个接触焊盘206，并且密封材料208可至少部分地围绕至少一个导线322。还可例如通过引线接合将至少一个导线322电连接到引线框架324。
密封材料208可具有范围从约10 μm至约300 μm的厚度tM，例如约20 μm至约200 μm，例如约30 μm至约100 μm。
在至少一个低温共烧陶瓷片212在载体202的侧面上、例如在载体底侧326上的沉积之前，载体202的可将至少一个低温共烧陶瓷片212设置到其上的侧面可经受粗化工艺，以改善至少一个低温共烧陶瓷片212到载体的所述侧面、即载体底侧326的粘附。
可在载体202的侧面上设置至少一个低温共烧陶瓷片（LTCC）212。此外，至少一个低温共烧陶瓷片212可物理接触密封材料208。每个陶瓷片可包括范围从约0.01 mm至约10 mm的厚度，例如约0.1 mm至约5 mm，例如约0.1mm至约1 mm。
可在载体底侧326上设置至少一个低温共烧陶瓷片212，载体底侧326与可将芯片204设置在其上的侧面328相对。至少一个低温共烧陶瓷片212可包括一个或多个低温共烧陶瓷片，例如单片或多片。在图3D中示出了多片装置。还可在密封材料208的至少一侧、例如332、例如334上设置至少一个低温共烧陶瓷片212，其中，密封材料208的至少一侧、例如332、例如334可基本上邻近于载体底侧326。密封材料208的至少一侧、例如332、例如334可基本上与载体底侧326齐平且可邻接载体底侧326。密封材料208的至少一侧、例如332、例如334可位于基本上平行于载体底侧326处。密封材料208的至少一侧、例如332、例如334可位于与载体底侧326基本上齐平的平面上。因此，可在单个沉积过程中将至少一个低温共烧陶瓷片212沉积在载体底侧326上并且直接沉积到密封材料208的至少一侧、例如332、例如334上。
在载体202的侧面上沉积至少一个低温共烧陶瓷片212可包括在载体202上的期望位置上布置一个或多个有机陶瓷带和/或片和/或箔。该有机陶瓷带和/或片可包括例如陶瓷颗粒、玻璃和金属和/或其他有机材料。
可将所述一个或多个有机陶瓷带和/或片布置在载体上，并且还可布置多个带和/或片，例如在必要时将它们堆叠和/或层压在一起。层压可使用热和压力工艺来进行，例如可堆叠（例如在模制中）、层压LTCC片212，并在范围从约10 N/mm2至30 N/mm2的压力下将其加热至约70℃至约80℃的范围。层压之后切割至最终尺寸。然后，可将LTCC片的堆叠布置结构化（例如切割）至要求的尺寸。
随后可执行烧制和/或共烧，其中，可对所述一个或多个有机陶瓷带和/或片进行共烧。该共烧工艺可包括将所述一个或多个有机陶瓷带和/或片和载体202加热至高达一温度，使得陶瓷颗粒、金属和玻璃可被烧结在一起。可使用被用于制造LTCC片的烧结工艺，例如，共烧可利用现有厚膜印刷技术。可为陶瓷的组成成分提供塑料和溶剂以允许压力和温度工艺下的层压。通过共烧，可烧掉有机物。取决于烧结陶瓷颗粒和玻璃所需的温度，烧制温度可在从约800℃至约875℃的范围内。可调整共烧剖面。例如，约350℃下的达约一小时的共烧可导致有机物的高达85%被烧掉。则可以例如在正常厚膜烘箱中使用可在850℃至900℃下灼烧LTCC的烧结剖面来执行共烧。LTCC片212可经历由于共烧而引起的收缩。例如经由激光结构化（例如钻孔、冲孔）来形成孔和/或过孔也可以是可能的，并且可通过LTCC片212和在所述孔和/或过孔中形成导电迹线和/或互连。可在过孔中形成用于互连的膏，并且在干燥之后，可印刷导体轨迹。互连例如包括银、金、钯膏，可与陶瓷层的维度的收缩率匹配。必要时可对LTCC片布置212的最外层进行后烧制以确保用于片材的自动化组装的装配的极限准确度。此外，可在干燥之后在LTCC片材布置上执行例如通过印刷的导电材料的沉积。可理解的是，如果准确地重复干燥炉中的温度曲线，则在共烧期间LTCC的收缩在约1%的公差的情况下可能是可再现的。轨迹的电性质可对应于正常厚膜导体。
至少一个低温共烧陶瓷片212可包括被烧结在一起的陶瓷颗粒和玻璃颗粒，其中，可将至少一个低温共烧陶瓷片212烧结到载体202的侧面326上，和/或接合到载体202的侧面326。玻璃可包括铝硼硅酸盐（alumoborosilicate）玻璃。陶瓷颗粒包括氧化铝。金属可包括来自以下材料组的至少一种，该材料组包括：铜、银、钯、金、铂。
根据各种其他实施例，可在共烧工艺之前可选地将LTCC片212、例如多片预先烧结在一起。在堆叠布置中的每层之间可存在可辨识的边界（参见图3D）。根据各种实施例，作为使用低温共烧陶瓷片的替代，可替代地使用高温共烧陶瓷（HTCC）片。
芯片装置310还可包括设置于至少一个芯片204、例如第一芯片204A与载体202之间的至少一个另外的低温共烧陶瓷片336。另外的低温共烧陶瓷片336可类似于低温共烧陶瓷片212，并且可以与如何可例如使用共烧将低温共烧陶瓷片212设置于载体上类似地被设置于载体202、例如载体202的侧面328上。另外的低温共烧陶瓷片336可至少部分地或完全被密封材料208围绕。另外的低温共烧陶瓷片336可充当芯片204、例如第一芯片204A与载体202之间的电绝缘介质。可将另外的低温共烧陶瓷片336的共烧可选地与低温共烧陶瓷片212的共烧放在一起。
根据其他实施例，另外的低温共烧陶瓷片336可以与另外的导电层338相组合地被使用作为如图3B中所示的多芯片模块的再分配层。
如图3B中所示，可将芯片装置310修改成芯片装置320、330，其中，芯片装置320、330可包括处于半桥电路布置中的至少一个芯片204。芯片装置320、330可包括被布置在半桥电路布置中的第一功率芯片204B1和第二功率芯片204B2。
可在至少一个芯片204、例如第一功率芯片204B1与载体202之间形成、即设置另外的低温共烧陶瓷片336。可在另外的低温共烧陶瓷片336上设置另外的导电层338，例如金属层，例如铜层。可将另外的导电层338电连接到形成于第一功率芯片背面处的第一功率芯片204B1的漏极触点206B1D。可在第一功率芯片正面处形成第一功率芯片204B1的源极触点206B1S，并可例如将其连接至地。第一功率芯片204B1可由于形成于第一功率芯片204B1与载体202之间的另外的低温共烧陶瓷片336的电绝缘性质而与载体202电绝缘。可例如经由导线和另外的导电层338将漏极触点206B1D电连接至用于第二功率芯片204B2的源极触点206B2S，源极触点206B2S可形成于芯片204B2的正面上。第二功率芯片204B2可经由其背面触点206B2D被电连接至载体202，载体202可连接至对电路进行供电所需的电压，例如220V。
至少一个低温共烧陶瓷片212可包括与密封材料208不同的材料，并且其可以是铜载体、例如载体202的高达10倍贵。然而，至少一个低温共烧陶瓷片212可包括与密封材料208相比具有更低的热阻（例如与密封材料208中的1至2W/mk相比的10至20 W/mK）的材料。结果，与可显示出不良热耗散性质的形成于芯片封装背面上的常用模制化合物隔离材料（例如类似于密封材料208）相比，可以以至少一个低温共烧陶瓷片212的形式使用较薄的芯片封装背面隔离材料。此外，至少一个低温共烧陶瓷片212可稳定至高达约300℃至约400℃的温度，不同于具有高达约100℃至约200℃的稳定性的传统模制化合物。
可理解的是，芯片装置310可包括芯片封装，例如电隔离芯片封装。芯片装置310可包括例如标准外壳，例如TO-220，例如TO-247，其可包括设置于载体202、例如铜引线框架上的芯片204。可在芯片封装中包括至少一个低温共烧陶瓷片212，其中，可用载体202来涂敷至少一个低温共烧陶瓷片212和/或与其一起烧结。
芯片装置310还可经历分离过程以便完成芯片封装，其中，如果需要的话，可执行通过密封材料208、载体202和至少一个低温共烧陶瓷片212中的至少一个的分割。
图3C示出了根据实施例的芯片装置340。根据各种实施例，芯片装置310、320、330可包括设置于载体202上的至少一个低温共烧陶瓷片212。到目前为止，已将LTCC片212示为是单个连续片材。在芯片装置340中，如所示的LTCC片212可包括设置于载体202和/或密封材料208上的一个或多个不连续的低温共烧陶瓷片212A、212B、212C。可在载体202和/或密封材料208的一部分上设置所述一个或多个低温共烧陶瓷片212A、212B、212C中的每一个。可使所述一个或多个低温共烧陶瓷片212A、212B、212C中的每一个相互分离一定间隙。替换地，可将所述一个或多个低温共烧陶瓷片212A、212B、212C中的每一个布置为基本上相互邻近。
图3D示出了根据实施例的芯片装置350，其中，芯片装置350可包括设置于载体202上的至少一个低温共烧陶瓷片212，其中，至少一个低温共烧陶瓷片212可包括多片堆叠布置。根据各种实施例，可在共烧工艺之前可选地将LTCC片212（例如多片）预先烧结在一起，或者可在共烧工艺期间将其烧结在一起以便将LTCC片接合到载体202。
芯片装置350示出了多LTCC片堆叠布置212，其可包括第一LTCC片212A1和第二LTCC片212B1。可在片212A1、212B1之间形成至少一个界面层，例如界面212A2。例如，由于加热和冷却，可将第一LTCC片212A1冷却，从而可在其表面上形成界面层、例如界面212A2。对可在第一LTCC片212A1上形成的第二LTCC片212B1的随后的加热和冷却可导致另一界面层，例如形成于第二LTCC片212B1的表面上的界面212B2。
根据其他实施例，多LTCC片堆叠布置212可包括设置于第一LTCC片212A1与第二LTCC片212B1之间的至少一个金属化层和/或片（未示出）。随后的烧结、例如共烧可导致所述LTCC片之间、例如第一LTCC片212A1与第二LTCC片212B之间的所述至少一个金属化层和/或片的烧结以及堆叠布置212到载体202的烧结。
图4示出了根据实施例的用于形成芯片装置的方法400。
方法400可包括：
在载体上设置包括至少一个接触焊盘的至少一个芯片（在410中）；
用密封材料至少部分地围绕所述至少一个芯片和所述载体（在420中）；以及
在载体的侧面上设置至少一个低温共烧陶瓷片（在430中）。
各种实施例提供了一种芯片装置，包括：载体；包括至少一个接触焊盘的至少一个芯片，其设置于所述载体上；密封材料，其至少部分地围绕所述至少一个芯片和所述载体；以及至少一个低温共烧陶瓷片，其设置于所述载体的侧面上。
根据实施例，所述载体包括引线框架材料，该引线框架材料包括来自以下材料组的至少一种，该材料组包括：铜、镍、铁、铜合金、镍合金、铁合金。
根据实施例，所述至少一个芯片包括功率半导体芯片、半导体逻辑芯片和半导体存储器芯片中的至少一个。
根据实施例，所述功率半导体芯片包括来自包括以下各项的组的至少一个功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅双极晶体管、闸流晶体管、MOS受控闸流晶体管、硅控整流器、肖特基功率二极管、碳化硅二极管、氮化镓器件。
根据实施例，所述半导体逻辑芯片包括来自包括以下各项的组的至少一个半导体逻辑器件：专用集成电路芯片、驱动器、控制器、传感器。
根据实施例，所述密封材料包括来自下组材料的至少一种，该组包括：填充的或未填充的环氧树脂、预先浸渍复合纤维、加强纤维、层压材料、模制材料、热固材料、热塑性材料、填料颗粒、纤维加强层压材料、纤维加强聚合物层压材料、具有填料颗粒的纤维加强聚合物层压材料。
根据实施例，所述密封材料形成于所述至少一个芯片上和所述至少一个芯片的一个或多个侧壁上。
根据实施例，所述密封材料形成于所述至少一个芯片上和所述载体的一个或多个侧壁上。
根据实施例，所述至少一个低温共烧陶瓷片设置于载体底侧上，该载体底侧与芯片被设置在其上的侧面相对。
根据实施例，所述至少一个低温共烧陶瓷片包括一个或多个低温共烧陶瓷片。
根据实施例，所述至少一个低温共烧陶瓷片被设置于载体的侧面上，并且其中，所述至少一个低温共烧陶瓷片物理地接触所述密封材料。
根据实施例，所述至少一个低温共烧陶瓷片被设置在载体底侧上以及在所述密封材料的至少一侧上，该载体底侧与所述芯片被设置在其上的侧面相对，其中，所述密封材料的所述至少一侧基本上邻近于所述载体底侧。
根据实施例，所述至少一个低温共烧陶瓷片被设置在载体底侧上以及在所述密封材料的至少一侧上，该载体底侧与所述芯片被设置在其上的侧面相对，其中，所述密封材料的所述至少一侧基本上与所述载体底侧齐平并邻接所述载体底侧。
根据实施例，所述至少一个低温共烧陶瓷片包括陶瓷颗粒、玻璃和金属。
根据实施例，所述至少一个低温共烧陶瓷片包括烧结在一起的陶瓷颗粒和玻璃颗粒，其中，所述至少一个低温共烧陶瓷片被烧结到所述载体的所述侧面。
根据实施例，所述玻璃包括铝硼硅酸盐玻璃。
根据实施例，所述陶瓷颗粒包括氧化铝。
根据实施例，所述金属包括来自以下材料组的至少一种，该材料组包括：铜、银、钯、金、铂。
根据实施例，所述芯片装置还包括设置在所述至少一个芯片与所述载体之间的至少一个另外的低温共烧陶瓷片。
根据实施例，所述芯片装置还包括被电连接到至少一个接触焊盘的至少一个导线，其中，所述密封材料至少部分地围绕所述至少一个导线，并且其中，所述至少一个导线被电连接到引线框架。
各种实施例提供了一种用于形成芯片装置的方法，该方法包括：在载体上设置包括至少一个接触焊盘的至少一个芯片；用密封材料至少部分地围绕所述至少一个片和所述载体；以及在载体的侧面上设置至少一个低温共烧陶瓷片。
根据实施例，在载体的侧面上设置至少一个低温共烧陶瓷片包括在载体的侧面上布置所述至少一个低温共烧陶瓷片并将所述至少一个低温共烧陶瓷片加热，其中，所述至少一个低温共烧陶瓷片被烧结到所述载体。
根据实施例，在载体的侧面上设置至少一个低温共烧陶瓷片包括在载体的侧面上布置包括嵌入玻璃中的陶瓷颗粒的所述至少一个低温共烧陶瓷片，并将所述至少一个低温共烧陶瓷片加热，其中，所述陶瓷和玻璃颗粒被烧结在一起。
虽然已经参考特定实施例特别地示出并描述了本发明，但本领域的技术人员应理解的是，在不脱离由所附权利要求定义的本发明的精神和范围的情况下可以对其进行形式和细节方面的各种修改。因此由所附权利要求来指示本发明的范围，并且因此意图涵盖落在权利要求的等价体的意义和范围内的所有改变。

Claims (23)

1.一种芯片装置，包括：
载体；
包括至少一个接触焊盘的至少一个芯片，其设置于所述载体上；
密封材料，其至少部分地围绕所述至少一个芯片和所述载体；以及
至少一个低温共烧陶瓷片，其设置于所述载体的侧面上。
2.根据权利要求1所述的芯片装置 ，
其中，所述载体包括引线框架材料，该引线框架材料包括来自以下材料组的至少一种，该材料组包括：铜、镍、铁、铜合金、镍合金、铁合金。
3.根据权利要求1所述的芯片装置，
其中，所述至少一个芯片包括功率半导体芯片、半导体逻辑芯片和半导体存储器芯片中的至少一个。
4.根据权利要求3所述的芯片装置，
其中，所述功率半导体芯片包括来自包括以下各项的组的至少一个功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅双极晶体管、闸流晶体管、MOS受控闸流晶体管、硅控整流器、肖特基功率二极管、碳化硅二极管、氮化镓器件。
5.根据权利要求3所述的芯片装置，
其中，所述半导体逻辑芯片包括来自包括以下各项的组的至少一个半导体逻辑器件：专用集成电路芯片、驱动器、控制器、传感器。
6.根据权利要求1所述的芯片装置，
其中，所述密封材料包括来自下组材料的至少一种，该组包括：填充的或未填充的环氧树脂、预先浸渍复合纤维、加强纤维、层压材料、模制材料、热固材料、热塑性材料、填料颗粒、纤维加强层压材料、纤维加强聚合物层压材料、具有填料颗粒的纤维加强聚合物层压材料。
7.根据权利要求1所述的芯片装置，
其中，所述密封材料形成于所述至少一个芯片上和所述至少一个芯片的一个或多个侧壁上。
8.根据权利要求1所述的芯片装置，
其中，所述密封材料形成于所述至少一个芯片上和所述载体的一个或多个侧壁上。
9.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片设置于载体底侧上，该载体底侧与芯片被设置在其上的侧面相对。
10.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片包括一个或多个低温共烧陶瓷片。
11.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片被设置于载体的侧面上，并且其中，所述至少一个低温共烧陶瓷片物理地接触所述密封材料。
12.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片被设置在载体底侧上以及在所述密封材料的至少一侧上，该载体底侧与所述芯片被设置在其上的侧面相对，其中，所述密封材料的所述至少一侧基本上邻近于所述载体底侧。
13.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片被设置在载体底侧上以及在所述密封材料的至少一侧上，该载体底侧与所述芯片被设置在其上的侧面相对，其中，所述密封材料的所述至少一侧基本上与所述载体底侧齐平并邻接所述载体底侧。
14.根据权利要求1所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片包括陶瓷颗粒、玻璃和金属。
15.根据权利要求14所述的芯片装置，
其中，所述至少一个低温共烧陶瓷片包括烧结在一起的陶瓷颗粒和玻璃颗粒，其中，所述至少一个低温共烧陶瓷片被烧结到所述载体的所述侧面。
16.根据权利要求14所述的芯片装置，
其中，所述玻璃包括铝硼硅酸盐玻璃。
17.根据权利要求14所述的芯片装置，
其中，所述陶瓷颗粒包括氧化铝。
18.根据权利要求14所述的芯片装置，
其中，所述金属包括来自以下材料组的至少一种，该材料组包括：铜、银、钯、金、铂。
19.根据权利要求1所述的芯片装置，还包括
至少一个另外的低温共烧陶瓷片，其设置在所述至少一个芯片与所述载体之间。
20.根据权利要求1所述的芯片装置，还包括
至少一个导线，其电连接到所述至少一个接触焊盘，其中，所述密封材料至少部分地围绕所述至少一个导线，并且其中，所述至少一个导线被电连接到引线框架。
21.一种用于形成芯片装置的方法，该方法包括：
在载体上设置包括至少一个接触焊盘的至少一个芯片；
用密封材料至少部分地围绕所述至少一个片和所述载体；以及
在载体的侧面上设置至少一个低温共烧陶瓷片。
22.根据权利要求20所述的方法，其中
在载体的侧面上设置至少一个低温共烧陶瓷片包括
在载体的侧面上布置所述至少一个低温共烧陶瓷片并将所述至少一个低温共烧陶瓷片加热，其中，所述至少一个低温共烧陶瓷片被烧结到所述载体。
23.根据权利要求21所述的方法，其中
在载体的侧面上设置至少一个低温共烧陶瓷片包括
在载体的侧面上布置包括嵌入玻璃中的陶瓷颗粒的所述至少一个低温共烧陶瓷片，并将所述至少一个低温共烧陶瓷片加热，其中，所述陶瓷和玻璃颗粒被烧结在一起。
CN201410019452.4A 2013-01-16 2014-01-16 芯片装置和用于形成芯片装置的方法 Active CN103928445B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/742,426 US9230889B2 (en) 2013-01-16 2013-01-16 Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic
US13/742426 2013-01-16

Publications (2)

Publication Number Publication Date
CN103928445A true CN103928445A (zh) 2014-07-16
CN103928445B CN103928445B (zh) 2017-07-28

Family

ID=51015199

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410019452.4A Active CN103928445B (zh) 2013-01-16 2014-01-16 芯片装置和用于形成芯片装置的方法

Country Status (3)

Country Link
US (1) US9230889B2 (zh)
CN (1) CN103928445B (zh)
DE (1) DE102014100309B4 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107500735A (zh) * 2017-09-06 2017-12-22 嘉兴佳利电子有限公司 一种黑色低温烧结微波介质陶瓷材料及其制备方法和应用
CN110211930A (zh) * 2019-05-29 2019-09-06 中国电子科技集团公司第三十八研究所 一种具有异质层结构的基板、制备方法及应用

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9397018B2 (en) 2013-01-16 2016-07-19 Infineon Technologies Ag Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit
US9230889B2 (en) 2013-01-16 2016-01-05 Infineon Technologies Ag Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic
US9368436B2 (en) * 2014-08-04 2016-06-14 Infineon Technologies Ag Source down semiconductor devices and methods of formation thereof
US9640419B2 (en) * 2014-08-04 2017-05-02 Infineon Technologies Ag Carrier system for processing semiconductor substrates, and methods thereof
DE102014111931B4 (de) * 2014-08-20 2021-07-08 Infineon Technologies Ag Niederinduktive Schaltungsanordnung mit Laststromsammelleiterbahn
DE102015116807A1 (de) 2015-10-02 2017-04-06 Infineon Technologies Austria Ag Funktionalisierte Schnittstellenstruktur
DE102016121801B4 (de) 2016-11-14 2022-03-17 Infineon Technologies Ag Baugruppe mit Verbindungen, die verschiedene Schmelztemperaturen aufweisen, Fahrzeug mit der Baugruppe und Verfahren zum Herstellen derselben und Verwendung der Baugruppe für eine Automobilanwendung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674159B1 (en) * 2000-05-16 2004-01-06 Sandia National Laboratories Bi-level microelectronic device package with an integral window
US20080296782A1 (en) * 2007-06-04 2008-12-04 Infineon Technologies Ag Semiconductor device
CN101572259A (zh) * 2008-04-30 2009-11-04 深圳市九洲光电子有限公司 一种全彩smd及其封装方法
CN102368529A (zh) * 2011-06-03 2012-03-07 王双喜 一种大功率led光源封装结构

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153710A (en) 1991-07-26 1992-10-06 Sgs-Thomson Microelectronics, Inc. Integrated circuit package with laminated backup cell
US6432497B2 (en) 1997-07-28 2002-08-13 Parker-Hannifin Corporation Double-side thermally conductive adhesive tape for plastic-packaged electronic components
JP2001351929A (ja) 2000-06-09 2001-12-21 Hitachi Ltd 半導体装置およびその製造方法
JP3627738B2 (ja) 2001-12-27 2005-03-09 株式会社デンソー 半導体装置
JP2003264265A (ja) 2002-03-08 2003-09-19 Mitsubishi Electric Corp 電力用半導体装置
KR100902766B1 (ko) 2002-09-27 2009-06-15 페어차일드코리아반도체 주식회사 절연성 세라믹 히트 싱크를 갖는 디스크리트 패키지
JP2005109100A (ja) 2003-09-30 2005-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4046120B2 (ja) 2005-01-27 2008-02-13 三菱電機株式会社 絶縁シートの製造方法およびパワーモジュールの製造方法
JP2007012857A (ja) 2005-06-30 2007-01-18 Renesas Technology Corp 半導体装置
TWI449137B (zh) * 2006-03-23 2014-08-11 Ceramtec Ag 構件或電路用的攜帶體
US8536445B2 (en) 2006-06-02 2013-09-17 Emcore Solar Power, Inc. Inverted metamorphic multijunction solar cells
DE102006060429B4 (de) * 2006-12-20 2013-08-22 Epcos Ag Elektrisches Bauelement mit Leadframe-Strukturen
DE102007003182B4 (de) * 2007-01-22 2019-11-28 Snaptrack Inc. Elektrisches Bauelement
US8093713B2 (en) 2007-02-09 2012-01-10 Infineon Technologies Ag Module with silicon-based layer
US7836764B2 (en) * 2007-04-02 2010-11-23 Infineon Technologies Ag Electrical device with covering
US7683477B2 (en) 2007-06-26 2010-03-23 Infineon Technologies Ag Semiconductor device including semiconductor chips having contact elements
US8077475B2 (en) 2007-09-27 2011-12-13 Infineon Technologies Ag Electronic device
DE102009014794B3 (de) 2009-03-28 2010-11-11 Danfoss Silicon Power Gmbh Verfahren zum Herstellen eines für Hochvoltanwendungen geeigneten festen Leistungsmoduls und damit hergestelltes Leistungsmodul
US8324653B1 (en) 2009-08-06 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with ceramic/metal substrate
DE102011003481A1 (de) * 2011-02-02 2012-08-02 Robert Bosch Gmbh Elektronisches Bauteil umfassend einen keramischen träger und Verwendung eines keramischen Trägers
JP5919625B2 (ja) 2011-02-22 2016-05-18 富士通株式会社 半導体装置及びその製造方法、電源装置
US9230889B2 (en) 2013-01-16 2016-01-05 Infineon Technologies Ag Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic
US20140197527A1 (en) 2013-01-16 2014-07-17 Infineon Technologies Ag Chip arrangement and a method for manufacturing a chip arrangement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674159B1 (en) * 2000-05-16 2004-01-06 Sandia National Laboratories Bi-level microelectronic device package with an integral window
US20080296782A1 (en) * 2007-06-04 2008-12-04 Infineon Technologies Ag Semiconductor device
CN101572259A (zh) * 2008-04-30 2009-11-04 深圳市九洲光电子有限公司 一种全彩smd及其封装方法
CN102368529A (zh) * 2011-06-03 2012-03-07 王双喜 一种大功率led光源封装结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107500735A (zh) * 2017-09-06 2017-12-22 嘉兴佳利电子有限公司 一种黑色低温烧结微波介质陶瓷材料及其制备方法和应用
CN107500735B (zh) * 2017-09-06 2021-01-15 嘉兴佳利电子有限公司 一种黑色低温烧结微波介质陶瓷材料及其制备方法和应用
CN110211930A (zh) * 2019-05-29 2019-09-06 中国电子科技集团公司第三十八研究所 一种具有异质层结构的基板、制备方法及应用

Also Published As

Publication number Publication date
CN103928445B (zh) 2017-07-28
US9230889B2 (en) 2016-01-05
DE102014100309A1 (de) 2014-07-17
US20140197523A1 (en) 2014-07-17
DE102014100309B4 (de) 2021-06-10

Similar Documents

Publication Publication Date Title
CN103928445A (zh) 芯片装置和用于形成芯片装置的方法
US11172572B2 (en) Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
CN105376936B (zh) 具有集成的功率电子电路系统和逻辑电路系统的模块
CN105575943B (zh) 有直接铜键合衬底和集成无源部件的功率半导体模块和集成功率模块
US9609754B2 (en) Package for mounting electronic element, electronic device, and imaging module
CN107078110A (zh) Igbt模组及其制造方法
CN102017135B (zh) 带有在多个接触平面中的元器件的基板电路模块
CN103906372A (zh) 具有内埋元件的电路板及其制作方法
CN102263194A (zh) 半导体封装与制造半导体封装的方法
US9596747B2 (en) Wiring substrate and electronic device
CN104425470A (zh) 半导体模块及其通过扩展嵌入技术的制造方法
JP2004158545A (ja) 多層基板及びその製造方法
CN103906371A (zh) 具有内埋元件的电路板及其制作方法
US20200402873A1 (en) Electronic device mounting board, electronic package, and electronic module
CN103635028A (zh) 埋入式元件电路板与其制作方法
KR20100014769A (ko) 전자 부품 모듈 및 이의 생산 방법
CN106465546A (zh) 用于生产嵌入了传感器晶片的印刷电路板的方法，以及印刷电路板
JP6312172B2 (ja) 回路装置及び該回路装置の製造方法
CN109964312B (zh) 半导体元件安装用基板端子板的制造方法
CN109121291A (zh) 半导体器件和用于构造半导体器件的方法
CN104766855A (zh) 芯片装置及其制造方法
CN108260274A (zh) 一种led灯用单面铝基板及其制造工艺
CN105390477B (zh) 一种多芯片3d二次封装半导体器件及其封装方法
EP2813132A1 (en) Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
CN112786455A (zh) 一种嵌入式封装模块化制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant