CN103928410A - 封装结构及其制作方法 - Google Patents
封装结构及其制作方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 164
- 238000004806 packaging method and process Methods 0.000 claims description 57
- 239000011241 protective layer Substances 0.000 claims description 49
- 235000012431 wafers Nutrition 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 229920000647 polyepoxide Polymers 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- 239000009719 polyimide resin Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010897 surface acoustic wave method Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 230000035515 penetration Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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Abstract
本发明提供一种封装结构及其制作方法。电子元件的封装体包含一基板、一电子元件晶片、一接合垫、一第一保护层、一导电层、一第二保护层以及一焊料球体。其中导电层具有一第一侧及相对于第一侧的一第二侧,且焊料球体设置于导电层的第一侧。在电子元件封装体中,由于第二保护层会同时接触导电层的第二侧的上表面及侧壁,而第一保护层接触导电层的第二侧的下表面,以完全包覆导电层的第二侧。因此能隔绝水气进入电子元件的封装体,以降低电子元件劣化的机会,进而提升电子元件的耐受性。
Description
技术领域
本发明关于一种电子元件的封装体,特别是有关于一种隔绝水气的电子元件的封装体及其制造方法。
背景技术
在电子元件的制程中,电子元件必须经过封装步骤处里后,以使用于各种不同的领域,例如,计算机、移动电话或数字相机等。因此,电子元件的封装体的可靠性也直接影响了最终电子装置的效能。
图1A是绘示一种已知的电子元件封装体100a剖面图。在图1A中,电子元件晶片110a设置于基板120a上,且电性连接于接合垫130a,其中接合垫130a夹置于电子元件晶片110a及基板120a之间。第一保护层140a夹置于接合垫130a及基板120a之间。而导电层150a形成于电子元件晶片110a之上,且电性连接于接合垫130a,形成T接触,其中导电层150a具有第一侧151a及相对于第一侧151a的第二侧152a,第二侧152a的下表面接触第一保护层140a。接着,第二保护层160a覆盖导电层150a之上,暴露导电层150a的第一侧151a,而导电层150a的第二侧152a暴露于电子元件封装体100a的侧壁。焊料球体170a形成于导电层150a的第一侧151a上。
在已知的电子元件封装体中,第二保护层仅覆盖于导电层之上,导电层的第二侧暴露于电子元件封装体的侧壁。环境中的水气可能沿导电层的第二侧进入电子元件封装体中,导致T接触部分劣化,甚至影响电子元件的效能。因此,亟需一种新的电子元件封装体及其制作方法,以避免环境中的水气进入电子元件封装体中,以提升电子元件的耐受性及其可靠性。
发明内容
为解决上述问题,本发明的一目的在于提供一种隔绝水气的电子元件的封装体。上述电子元件的封装体包含:一基板;一电子元件晶片,设置于基板之上;一接合垫,夹置于基板与电子元件晶片之间,且电性连接于电子元件晶片;一第一保护层,夹置于基板与接合垫之间;一导电层,设置于电子元件晶片的侧壁上,且电性连接于接合垫,其中导电层具有一第一侧及相对于第一侧的一第二侧,第二侧的下表面接触第一保护层;一第二保护层,设置于导电层上,暴露导电层的第一侧,且包覆导电层的第二侧,其中第二保护层同时接触导电层的上表面及侧壁,并与第一保护层完全包覆导电层的第二侧;以及一焊料球体,设置于暴露的导电层的第一侧上。
本发明的另一目的在于提供一种电子元件的封装体的制作方法。上述电子元件的封装体的制作方法包含:提供一半导体晶圆,其上包含多个电子元件晶片;形成一接合垫于各电子元件晶片之下,且电性连接于各电子元件晶片;形成一第一保护层于接合垫之下;形成一导电层于各电子元件晶片的侧壁上,且电性连接于接合垫,此导电层具有一第一侧及一第二侧,其中导电层的第二侧的下表面接触第一保护层,且相邻的所述电子元件晶片的侧壁上的导电层彼此不相连接;形成一第二保护层于导电层上,暴露导电层的第一侧,且包覆导电层的第二侧,其中第二保护层同时接触导电层的上表面及侧壁,并与第一保护层完全包覆导电层的第二侧;形成一焊料球体于导电层的第一侧上;以及切割此些电子元件晶片之间导电层彼此不相连接之处,以分离的此些电子元件晶片,分别制成电子元件封装体。
在上述的电子元件封装体中,由于第二保护层会同时接触导电层的上表面及侧壁,并与该第一保护层完全包覆导电层的第二侧,避免外界水气进入封装体中,降低电子元件劣化的机会,进而提升电子元件的耐受性与可靠性。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附图式的详细说明如下:
图1A是绘示已知的电子元件封装体100a剖面图;
图1B是根据本发明的一实施例所绘示电子元件的封装体100b剖面图;
图2A是绘示已知制作导电层的光罩次图案200a;
图2B是根据本发明的一实施例所绘示制作导电层的光罩次图案200b;
图2C是根据本发明的一实施例所绘示制作导电层的光罩次图案200c;
图3A至图3I是根据本发明的一实施例所绘示制作电子元件封装体剖面图;以及
图4A至图4E是根据本发明的另一实施例所绘示制作电子元件封装体剖面图。
附图中符合的简单说明如下:
100a、100b、300a、300b:电子元件的封装体
110a、110b、310:电子元件晶片
120a、120b、320:基板
130a、130b、330:接合垫
140a、140b、340:第一保护层
150a、150b、350、350a、350b:导电层
151a、151b、351a、351b:第一侧
152a、152b、352a、352b:第二侧
160a、160b、380:第二保护层
170a、170b、390a、390b:焊料球体
180:隔离层
190:胶材层
200a、200b、200c:光罩次图案
210a、210b、210c、220a、220b、220c:次图案
230、240:分隔道
360:凹槽
370a、370b、370c、410a、410b:光阻层
T:T接触。
具体实施方式
接着以实施例并配合图式以详细说明本发明,在图式或描述中,相似或相同的部分使用相同的符号或编号。在图式中,实施例的形状或厚度可能扩大,以简化或方便标示,而图式中元件的部分将以文字描述。可了解的是,未绘示或描述的元件可为本领域普通技术人员所知的各种样式。另外当叙述一层形成于一基材或是另一层上时,此层可直接位于基材或是另一层上,或是其间亦可以有中介层。
本文所使用的术语仅是用于描述特定实施例的目的而不意欲限制本发明。如本文所使用,单数形式“一”及“该”意欲亦包括复数形式,除非本文另有清楚地指示。应进一步了解,当在本说明书中使用时,术语“包含”指定存在所述的特征、整数、步骤、运作、元件及/或组份,但并不排除存在或添加一或多个其它特征、整数、步骤、运作、元件、组份及/或其群组。本文参照为本发明的理想化实施例(及中间结构)的示意性说明的横截面说明来描述本发明的实施例。如此,本领域技术人员将预期偏离所述说明的形状的由于(例如)制造技术及/或容差的改变。因此,不应将本发明的实施例理解为限于本文所说明的特定区域形状,而将包括起因于(例如)制造的形状改变,且所述图中所说明的区域本质上为示意性的,且其形状不意欲说明设备的区域的实际形状且不意欲限制本发明的范畴。
图1B是绘示根据本发明的一实施例所绘示的电子元件的封装体100b剖面图。在图1B中,电子元件晶片110b设置于基板120b上,且电性连接于接合垫130b,其中接合垫130b夹置于电子元件晶片110b及基板120b之间。第一保护层140b夹置于接合垫130b及基板120b之间。而导电层150b形成于电子元件晶片110b之上,且电性连接于接合垫130b,形成T接触,其中导电层150b具有第一侧151b及相对于第一侧151b的第二侧152b,第二侧152b的下表面接触第一保护层140b。接着,第二保护层160b覆盖导电层150b之上,暴露导电层150b的第一侧151b,且包覆导电层150b的第二侧152b。焊料球体170b形成于导电层150b的第一侧151b上。其中,第二保护层160b同时接触导电层150b的上表面及侧壁,并与第一保护层140b完全包覆导电层150b的第二侧152b。
根据本发明的一实施例,上述电子元件晶片110b包含一集成电路元件、一光电元件、一微机电元件、一表面声波元件或其组合。
根据本发明的一实施例,上述第一保护层140b包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
根据本发明的一实施例,上述导电层150b包含铜、铝、镍、金或其组合。
根据本发明的一实施例,上述第二保护层160b包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
在图1B中,电子元件的封装体100b还包含隔离层180,夹置于基板120b与电子元件晶片110b之间。根据本发明的一实施例,上述接合垫130b与上述隔离层180为同平面。根据本发明的另一实施例,上述隔离层180包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
在图1B中,电子元件的封装体100b还包含胶材层190,夹置于导电层150b与电子元件晶片110b之间。根据本发明的一实施例,上述胶材层190包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
图2A是绘示已知制作导电层的光罩次图案200a。在图2A中,光罩次图案200a具有多个透光区(白色部分)及至少一个遮光区(斜线部分),且次图案210a及次图案220a为相邻的次图案。其中次图案210a的上述诸透光区之一连接于次图案220a的上述诸透光区之一。
图2B是根据本发明的一实施例所绘示的制作导电层的光罩次图案200b。在图2B中,光罩次图案200b具有多个透光区(白色部分)及至少一个遮光区(斜线部分),且次图案210b及次图案220b为相邻的次图案。其中次图案210b及次图案220b之间具有分隔道230,分隔道230为遮光区的一部分,以分开次图案210b的透光区及次图案220b的透光区。
图2C是根据本发明的一实施例所绘示的制作导电层的光罩次图案200c。在图2C中,光罩次图案200c具有多个遮光区(斜线部分)及至少一个透光区(白色部分),且次图案210c及次图案220c为相邻的次图案。其中次图案210c及次图案220c之间具有分隔道240,分隔道240为透光区的一部分,以分开次图案210c的遮光区及次图案220c的遮光区。
图3A至图3I是根据本发明的一实施例所绘示的制作电子元件的封装体剖面图。在图3A中,提供电子元件晶片310设置于基板320上,且电性连接于接合垫330,其中接合垫330夹置于电子元件晶片310及基板320之间。第一保护层340夹置于接合垫330及基板320之间。而导电层350形成于电子元件晶片310之上,且电性连接于接合垫330。其中导电层350的下表面接触第一保护层340。在图3A中,具有凹槽360以分别电子元件的封装体300a与相邻的封装体300b。
根据本发明的一实施例,制作电子元件的封装体还包含提供一基板,以及形成一隔离层夹置于基板与电子元件晶片之间。根据本发明的另一实施例,制作电子元件的封装体还包含形成一胶材层夹置于电子元件晶片与导电层之间。
在图3B中,形成光阻层370a于上述导电层350之上。接着利用具有如图2B或图2C所绘示的次图案的光罩进行显影步骤,形成具有光罩次图案的光阻层370b,如图3C所示。根据本发明的一实施例,光阻层370b利用一负光阻剂配合一明光罩所形成,其中上述明光罩具有如图2B所绘示的光罩次图案。根据本发明的一实施例,光阻层370b利用一正光阻剂配合一暗光罩所形成,其中上述暗光罩具有如图2C所绘示的光罩次图案。
在图3D中,移除部分光阻层370b,形成具有一凹部的光阻层370c于凹槽360,以暴露部分的导电层350。值得注意的是,上述光阻层370c的凹部对应于图2B或图2C所绘示的光罩次图案的分隔道230或240。
在图3E中,蚀刻暴露的导电层350,以暴露部分的第一保护层340于凹槽360,形成导电层350a及350b。其中导电层350a具有第一侧351a及第二侧352a,而导电层350b具有第一侧351b及第二侧352b,且导电层350a的第二侧352a不连接于导电层350b的第二侧352b。然而,在已知技术中,不具有蚀刻导电层的步骤,因此电子元件封装体的导电层连接于相邻的封装体的导电层。
在图3F中,移除图3E的光阻层370c后,暴露导电层350a及350b。接着沉积金属于导电层350a及350b上,以增厚导电层350a及350b,如图3G所示。
在图3H中,形成第二保护层380于导电层350a及350b上,暴露导电层350a及350b的第一侧351a及351b,且包覆导电层350a及350b的第二侧352a及352b,其中第二保护层380同时接触导电层350a及350b的上表面及侧壁,并与第一保护层340完全包覆导电层350a的第二侧352a及导电层350b的第二侧352b。接着形成焊料球体390a于导电层350a的第一侧351a上,及形成焊料球体390b于导电层350b的第一侧351b上。经由一切割步骤,沿着凹槽360,分割成分别独立的电子元件封装体300a及300b,如图3I所示。
图4A至图4E是根据本发明的另一实施例所绘示的制作电子元件的封装体剖面图。接续如图3B所绘示的结构,在图4A中,利用具有如图2B或图2C所绘示的次图案的光罩进行显影步骤,形成具有光罩次图案的光阻层410a。根据本发明的一实施例,光阻层410a利用一正光阻剂配合一明光罩所形成,其中上述明光罩具有如图2B所绘示的光罩次图案。根据本发明的一实施例,光阻层410a利用一负光阻剂配合一暗光罩所形成,其中上述暗光罩具有如图2C所绘示的光罩次图案。
在图4B中,移除图4A的光阻层410a后,形成具有一凸块的光阻层410b于凹槽360,以暴露部分的导电层350。值得注意的是,上述光阻层410b的凸块对应于图2B或图2C所绘示的光罩次图案的分隔道230或240。
在图4C中,沉积金属于暴露的导电层350上,以增厚导电层350。接着移除光阻层410b,以形成具有一凹部的导电层350,如图4D所示。
在图4E中,蚀刻导电层350的凹部,以暴露部分的第一保护层340于凹槽360,形成导电层350a及350b。其中导电层350a具有第一侧351a及第二侧352a,而导电层350b具有第一侧351b及第二侧352b,且导电层350a的第二侧352a不连接于导电层350b的第二侧352b。
接着如图3H至图3I所示,依序形成第二保护层、焊料球体以及沿凹槽切割,以分割成个别独立的电子元件封装体。其中图3H至图3I的内容已记载如前,不再加以赘述。
值得注意的是,由于第一保护层接触导电层的第二侧的下表面,而第二保护层会同时接触导电层的第二侧的上表面及侧壁,因此第一保护层与第二保护层会完全覆盖导电层的第二侧,以隔绝水气进入电子元件的封装体。因为降低了电子元件劣化的机会,进而提升电子元件的耐受性。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (18)
1.一种电子元件的封装体,其特征在于,包含:
一基板;
一电子元件晶片,设置于该基板之上;
一接合垫,夹置于该基板与该电子元件晶片之间,且电性连接于该电子元件晶片;
一第一保护层,夹置于该基板与该接合垫之间;
一导电层,设置于该电子元件晶片的侧壁上,且电性连接于该接合垫,其中该导电层具有一第一侧及相对于该第一侧的一第二侧,该第二侧的下表面接触该第一保护层;
一第二保护层,设置于该导电层上,暴露该导电层的该第一侧,且包覆该导电层的该第二侧,
其中该第二保护层同时接触该导电层的上表面及侧壁,并与该第一保护层完全包覆该导电层的该第二侧;以及
一焊料球体,设置于暴露的该导电层的该第一侧上。
2.根据权利要求1所述的电子元件的封装体,其特征在于,该电子元件晶片包含一集成电路元件、一光电元件、一微机电元件、一表面声波元件或其组合。
3.根据权利要求1所述的电子元件的封装体,其中该第一保护层包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
4.根据权利要求1所述的电子元件的封装体,其特征在于,该导电层包含铜、铝、镍、金或其组合。
5.根据权利要求1所述的电子元件的封装体,其特征在于,该第二保护层包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
6.根据权利要求1所述的电子元件的封装体,其特征在于,还包含一隔离层,夹置于该基板与该电子元件晶片之间。
7.根据权利要求6所述的电子元件的封装体,其特征在于,该接合垫与该隔离层为同平面。
8.根据权利要求6所述的电子元件的封装体,其特征在于,该隔离层包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
9.根据权利要求1所述的电子元件的封装体,其特征在于,还包含一胶材层,夹置于该导电层与该电子元件晶片之间。
10.根据权利要求9所述的电子元件的封装体,其特征在于,该胶材层包含环氧树脂、聚酰亚胺树脂、氧化硅、金属氧化物或氮化硅。
11.一种电子元件封装体的制作方法,其特征在于,包含下列步骤:
提供一半导体晶圆,其上包含多个电子元件晶片;
形成一接合垫于各该电子元件晶片之下,且电性连接各该电子元件晶片;
形成一第一保护层于该接合垫之下;
形成一导电层于各该电子元件晶片的侧壁上,且电性连接该接合垫,该导电层具有一第一侧及一第二侧,其中该导电层的该第二侧的下表面接触该第一保护层,且相邻的所述电子元件晶片的侧壁上的该导电层彼此不相连接;
形成一第二保护层于该导电层上,暴露该导电层的该第一侧,且包覆该导电层的该第二侧,其中该第二保护层同时接触该导电层的上表面及侧壁,并与该第一保护层完全包覆该导电层的该第二侧;
形成一焊料球体于该导电层的该第一侧上;以及
切割相邻的所述电子元件晶片之间该导电层彼此不相连接之处以分离所述电子元件晶片。
12.根据权利要求11所述的电子元件封装体的制作方法,其特征在于,还包含:
提供一基板;以及
形成一隔离层,其夹置于该基板与各该电子元件晶片之间。
13.根据权利要求11所述的电子元件封装体的制作方法,其特征在于,还包含形成一胶材层,其夹置于各该电子元件晶片与该导电层之间。
14.根据权利要求11所述的电子元件封装体的制作方法,其特征在于,形成该导电层的步骤包含:
形成一导电层于各该电子元件晶片的侧壁上,并电性连接于该接合垫;
形成一光阻层于该导电层上;
蚀刻部分该导电层,使该导电层不连接于相邻的一电子元件封装体的一导电层;
移除该光阻层;以及
沉积金属于该导电层上,以增厚该导电层。
15.根据权利要求11所述的电子元件封装体的制作方法,其特征在于,形成该导电层的步骤包含:
形成一导电层于该电子元件的侧壁上,并电性连接于该接合垫;
形成一光阻层于该导电层上;
沉积金属于该导电层上,以增厚该导电层;
移除该光阻层;以及
蚀刻部分该导电层,使该导电层不连接于相邻的该封装体的该导电层。
16.根据权利要求14或15所述的电子元件封装体的制作方法,其特征在于,形成该光阻层的步骤包含:
涂布一光阻剂于该导电层上,形成一光阻层;
利用一光罩,形成多个次图案之一于该光阻层上;以及
移除部分该光阻层,以曝露部分该导电层,
其中该次图案分别对应于该电子元件晶片,且各该次图案与相邻的各该次图案之间具有一分隔道,移除部分该光阻层后,与该分隔道相对应的该光阻层形成一凸块或一凹部,使该导电层与相邻的该封装体的该导电层不相连。
17.根据权利要求16所述的电子元件封装体的制作方法,其特征在于,该光阻剂为正光阻剂或负光阻剂。
18.根据权利要求16所述的电子元件封装体的制作方法,其特征在于,该光罩为明光罩或暗光罩。
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US8975739B2 (en) | 2015-03-10 |
US20140197536A1 (en) | 2014-07-17 |
TW201428915A (zh) | 2014-07-16 |
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