CN103915497B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103915497B
CN103915497B CN201310593999.0A CN201310593999A CN103915497B CN 103915497 B CN103915497 B CN 103915497B CN 201310593999 A CN201310593999 A CN 201310593999A CN 103915497 B CN103915497 B CN 103915497B
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epitaxial layer
type epitaxial
groove
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silicon carbide
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CN103915497A (zh
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李钟锡
洪坰国
千大焕
郑永均
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Hyundai Motor Co
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Abstract

本发明涉及一种包括碳化硅(SiC)的半导体器件及其制造方法。本发明利用沟槽栅极来增加碳化硅MOSFET中的沟道的宽度。与传统技术相比，根据本发明的示例实施例，可以通过在沟槽的两侧上形成多个延伸到p型外延层的突起来增加沟道的宽度。

Description

半导体器件及其制造方法
相关申请的交叉参考
本申请要求于2012年12月28日在韩国知识产权局提交的韩国专利申请No.10-2012-0157508的优先权的利益，该申请的全部内容包括在此以供参考。
技术领域
本发明涉及一种包括碳化硅(SiC)的半导体器件及其制造方法。
背景技术
近来随着大尺寸和大容量应用设备的趋势，具有高击穿电压、高电流容量和高速切换特征的功率半导体器件已经成为必需。
相应地，正在进行许多关于利用碳化硅(SiC)的MOSFET（金属氧化物半导体场效应晶体管）的研究与开发，代替了利用硅的传统MOSFET。具体地，有大量的垂直沟槽MOSFET的开发。
在垂直沟槽MOSFET中，在沟槽的两侧上的p型外延层中都形成有沟道。沟道的宽度与该p型外延层的厚度成比例。
能够延长沟道宽度以增加传导电流的量；但是，因为沟道的宽度与p型外延层的厚度成比例，所以不得不把该p型外延层制造得更厚，致使该半导体器件的面积的增加。
在该背景技术部分披露的以上信息仅用于加强对于本发明构思背景的理解，因此也可能包含不构成现有技术的信息。
发明内容
已经做出了本发明构思以努力利用沟槽栅极来增加碳化硅MOSFET中的沟道的宽度。
本发明的一方面涉及半导体器件，该半导体器件包括：n+型碳化硅基板；依次设置在n+碳化硅基板的第一表面上的n-型外延层、p型外延层、和n+区；沟槽，其穿该n+区和p型外延层，设置在n-型外延层上，且包括设置于该沟槽两侧上的多个突起；设置在沟槽内的栅极绝缘膜；设置在栅极绝缘膜上的栅电极；设置在栅电极上的氧化膜；设置在p型外延层、n+区、和氧化膜上的源电极；及置于n+型碳化硅基板的第二表面上的漏电极，其中多个突起延伸到p型外延层。
置于沟槽一侧上的突起可以彼此间隔开。
多个突起可以设置在沟槽的两侧与p型外延层之间的接触区域。
本发明的一方面包含半导体器件的制造方法，该方法包括：在n+型碳化硅基板的第一表面上依次形成n-型外延层、p型外延层、和n+区；通过穿透n+区和p型外延层并通过蚀刻n-型外延层的一部分来形成沟槽；及通过蚀刻沟槽的两侧，形成多个突起，其中多个突起延伸到p型外延层。
根据本发明的示例实施例的半导体器件的制造方法可以进一步包括：在形成多个突起之后，在沟槽内形成栅极绝缘膜；在栅极绝缘膜上形成栅电极；在栅极绝缘膜和栅电极上形成氧化膜；及在p型外延层、n+区、和氧化膜上形成源电极，和在n+型碳化硅基板的第二表面上形成漏电极。
与传统技术相比，根据本发明的示例实施例，可以通过形成多个延伸到沟槽的两侧上的p型外延层的突起来增加沟道的宽度。
随着沟道宽度的增加，可以减小沟道电阻，且可以增加传导电流的量。
此外，为了获得同样的电流量，可以减少半导体器件的面积，从而使生产成本降低。
附图的简要说明
本发明的上述和其他特点将从本发明的如附图中所例示的实施例的更具体描述而变得明显，在附图中，贯穿不同视图中相同的参考字符以指相同或相似部分。附图不必按比例，而是将重点放在说明本发明的实施例的原理上。
图1是根据本发明的示例实施例的半导体器件的截面剖视图。
图2是图1的部分A的放大示图。
图3-图6是依次显示根据本发明的示例实施例的半导体器件的制造方法的示图。
<符号描述>
100：n+型碳化硅基板 200：n-型外延层
300：p型外延层 400：n+区
450：沟槽 455：突起
500：栅极绝缘膜 510：氧化膜
600：栅电极 700：源电极
800：漏电极
具体实施方式
将参照附图来详细描述本发明的示例实施例。本发明可以以许多不同的形式进行改进，并且不应解释为被本文中列出的示例实施例所限制。更确切地说，提供本发明的示例实施例以使得本发明的公开充分和完全，并且能完全地传达给本领域技术人员。
在附图中，为了清晰起见，可能放大层和区的厚度。另外，当描述一个层形成于另一个层上或基板上，这里意味着该层可以形成于另一个层上或基板上，或可以在该层和另一个层或基板之间插入第三层。贯穿本说明书，相同的数字指的是相同的元件。
图1是根据本发明的示例实施例的半导体器件的截面剖视图。图2是图1的部分A的放大示图。
参考图1和图2，在根据本发明的示例实施例的半导体器件中，n-型外延层200、p型外延层300、和n+区400可以依设置在n+型碳化硅基板100的第一表面上。
沟槽450可以设置于n-型外延层200、p型外延层300、和n+区400上。沟槽450可以穿透n+区400和p型外延层300。多个突起455可以设置于沟槽450的两侧上。突起455可以延伸到p型外延层300。就是说，突起455可以设置在沟槽450的侧面与p型外延层300之间的接触区域。并且，位于沟槽450一侧上的突起455可以彼此间隔开。
沟道350可以设置于沟槽450的两侧上的p型外延层300内。沟道350可以与这些突起455接触。这样，沟道350的宽度可以包括突起455的周边，因此，与传统技术相比，沟道350的宽度可以增加突起455的长度T（参见图2）的两倍。
栅极绝缘膜500可以设置于沟槽450内，栅电极600可以设置于栅极绝缘膜500上，且氧化膜510可以设置于栅极绝缘膜500和栅电极600上。栅电极600可以填充沟槽450。
源电极700可以形成于p型外延层300、n+区400、和氧化膜510上。漏电极800可以形成于n+型碳化硅基板100的第二表面上。
这样，与传统技术相比，可以通过形成多个延伸到沟槽450的两侧上的p型外延层300的突起455来增加沟道350的宽度。
随着沟道350的宽度的增加，可以减小沟道350的电阻，且可以增加传导电流的量。
此外，为了获得同样的电流量，可以减少半导体器件的面积，从而使生产成本降低。
现在，根据将参考图3-6及图1详细描述本发明的示例实施例的半导体器件的制造方法。
图3-图6是依次显示根据本发明的示例实施例的半导体器件的制造方法的示图。
如图3中所示，制备n+型碳化硅基板100，然后，可以通过在n+型碳化硅基板100的第一表面上的第一外延生长来形成n-型外延层200，然后，可以通过在n-型外延层200上的第二外延生长来形成p型外延层300，且然后，可以通过在p型外延层300上的第三外延生长来形成n+区400。
虽然在本发明的示例实施例中可以通过第三外延生长来形成n+区400，但是n+区400可以通过向p型外延层300的一部分中注入离子来形成，而不进行外延生长。
如图4所示，可以通过穿透n+区400和p型外延层300及通过蚀刻n-型外延层200的一部分来形成沟槽450。
如图5所示，可以通过蚀刻沟槽450的两侧的一部分来形成多个突起455。突起455可以延伸到p型外延层300。就是说，突起455可以形成在沟槽450的侧面与p型外延层300之间的接触区域。并且，位于沟槽450一侧上的突起455可以彼此间隔开。
如图6所示，栅极绝缘膜500可以形成于沟槽450内，且栅电极600可以形成于栅极绝缘膜500上。氧化膜510可以形成于栅极绝缘膜500和栅电极600上。可以蚀刻n+区400的一部分。
如图1所示，源电极700可以形成于p型外延层300、n+区400、和氧化膜510上。漏电极800可以形成于n+型碳化硅基板100的第二表面上。
虽然已经结合目前被认为是实用的示例性实施例对本发明进行了描述，应理解本发明不限于公开的实施例，相反，本发明旨在涵盖包括在所附权利要求的精神和范围内的各种修改和等效布置。

Claims (5)

1.一种半导体器件，包括：
n+型碳化硅基板；
依次地设置在所述n+型碳化硅基板的第一表面上的n-型外延层、p型外延层、和n+区；
沟槽，其穿透所述n+区和所述p型外延层，设置在所述n-型外延层上，且包括设置于所述沟槽两侧上的多个突起；
设置在所述沟槽内的栅极绝缘膜；
设置在所述栅极绝缘膜上的栅电极；
设置在所述栅电极上的氧化膜；
设置在所述p型外延层、所述n+区、和所述氧化膜上的源电极；和
置于所述n+型碳化硅基板的第二表面上的漏电极，
其中所述多个突起延伸到所述p型外延层，并且
位于所述沟槽的一侧上的突起彼此间隔开。
2.根据权利要求1所述的半导体器件，其中所述多个突起被设置在所述沟槽的侧面与所述p型外延层之间的接触区域。
3.一种半导体器件的制造方法，该方法包括：
在n+型碳化硅基板的第一表面上依次形成n-型外延层、p型外延层、和n+区；
通过穿透所述n+区和所述p型外延层并通过蚀刻所述n-型外延层的一部分，形成沟槽；和
通过蚀刻所述沟槽的两侧，形成多个突起，
其中所述多个突起延伸到所述p型外延层，并且
位于所述沟槽的一侧上的突起彼此间隔开。
4.根据权利要求3所述的方法，其中所述多个突起被设置在所述沟槽的侧面与所述p型外延层之间的接触区域。
5.根据权利要求3所述的方法，进一步包括：
在形成多个突起之后，在所述沟槽内形成栅极绝缘膜；
在所述栅极绝缘膜上形成栅电极；
在所述栅极绝缘膜和所述栅电极上形成氧化膜；和
在所述p型外延层、所述n+区、和所述氧化膜上形成源电极，并在所述n+型碳化硅基板的第二表面上形成漏电极。
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