CN103904053A - 芯片堆叠结构 - Google Patents

芯片堆叠结构 Download PDF

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Publication number
CN103904053A
CN103904053A CN201310089368.5A CN201310089368A CN103904053A CN 103904053 A CN103904053 A CN 103904053A CN 201310089368 A CN201310089368 A CN 201310089368A CN 103904053 A CN103904053 A CN 103904053A
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substrate
layer
those
reroutes
chip stack
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CN103904053B (zh
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刘昌炽
余迅
陈鹏书
吴仕先
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Abstract

一种芯片堆叠结构，包括多个微凸块结构、多个第一衬底、至少一第一间隙层、多个第二衬底以及至少一第二间隙层。所述第一衬底利用所述微凸块结构的一部分彼此堆叠，并且各第一衬底包括至少一第一重布线层。第一间隙层位于所堆叠的第一衬底之间。所述第二衬底利用所述微凸块结构的另一部分与所述第一衬底至少其中之一堆叠，并且各第二衬底包括至少一第二重布线层。第二间隙层位于所堆叠的第一衬底与第二衬底之间。所述第一重布线层、所述第二重布线层以及所述微凸块结构形成多个阻抗元件，并且所述阻抗元件提供一特定的振荡频率。

Description

芯片堆叠结构
技术领域
本发明是有关于一种芯片堆叠结构，且特别是有关于一种三维芯片堆叠结构(three-dimensional chip stacking structure)。
背景技术
近代电子产业随着摩尔定律规范(Moore’s Law)而蓬勃发展。然而，随着电子产品的指令周期提升等需求，技术的瓶颈也逐渐产生。为了让电子产品的性能跟上需求，于是，三维集成电路构装(3D IC integration)技术成为现今解决问题的办法之一。三维集成电路构装技术相较于一般传统封装形式拥有许多优点，例如元件尺寸较小、较少的信号损失与较好的电性性能，这些都是因为使用硅导通孔的缘故。
硅导通孔(Through Silicon Via，TSV)与微凸块(microbump)结构已成为三维集成电路构装技术的重要核心。典型含硅导通孔的中介层(TSVinterposer)的三维集成电路整合系统级封装(3D IC SiP)结构，其中，中介层利用微凸块(microbump)结构，在上下方都可承载芯片，且通过焊锡凸块(solder bump)结构而可与衬底(substrate)或印刷电路板(PCB)连接。因此，三维集成电路构装技术为提升电子产品性能的最有效架构之一，可允许多个芯片间的相互连接，将更多的运算能力、存储器和其他功能整合在同一个小型化装置内。
发明内容
本发明提供一种芯片堆叠结构，包括多个微凸块结构、多个第一衬底、至少一第一间隙层、多个第二衬底以及至少一第二间隙层。所述第一衬底利用所述微凸块结构的第一部分彼此堆叠，并且各第一衬底包括至少一第一重布线层。第一间隙层位于第一衬底之间。第一部分微凸块结构设置于第一间隙层，用以连接所堆叠的第一衬底的第一重布线层。所述第二衬底利用所述微凸块结构的第二部分与所述第一衬底至少其中之一堆叠，并且各第二衬底包括至少一第二重布线层。第二间隙层位于第一衬底与第二衬底之间。第二部分微凸块结构设置于第二间隙层，用以连接所堆叠的第一衬底的第一重布线层和所堆叠的第二衬底的第二重布线层。所述第一重布线层、所述第二重布线层以及所述微凸块结构形成多个阻抗元件，并且所述阻抗元件提供一特定的振荡频率。
基于上述，本发明的芯片堆叠结构包括多个利用微凸块结构、导电通孔以及多层芯片堆叠的方式形成的立体式绕线阻抗元件，此些阻抗元件彼此电性连接，具有良好电气特性。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1绘示本发明一实施例的芯片堆叠结构的概要示意图。
图2绘示图1的芯片堆叠结构的等效电路图。
图3绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图4绘示图3的芯片堆叠结构的等效电路图。
图5绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图6绘示图5的芯片堆叠结构的等效电路图。
图7绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图8绘示图7的芯片堆叠结构的等效电路图。
图9绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图10绘示图9的芯片堆叠结构的等效电路图。
图11绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图12绘示图11的芯片堆叠结构的等效电路图。
图13绘示本发明另一实施例的芯片堆叠结构的概要示意图。
图14绘示图13的芯片堆叠结构的等效电路图。
图15绘示本发明一实施例的电容元件的芯片堆叠结构的概要示意图。
图16绘示本发明另一实施例的电容元件的芯片堆叠结构的概要示意图。
【主要元件符号说明】
100、200、300、400、500、600、700、800、900：芯片堆叠结构；
110、120、210、220、310、320、340、410、420、440、810、910：第一衬底；
112、112a、112b、122、122a、122b、212、212a、212b、222、222a、222b、312、322U、322D、342、412、422U、422D、442、522、512a、512b、612a、612b、712a：第一重布线层；
113、213、413：反环结构；
115a、115b、215a、215b、215c、325a、325b、415a、425b、515a、515b、515c：导电线路；
130、230、330、430、530、630、830、930：微凸块结构；
327、427、517a、517b、617a、617b、617c、647、657、747、757、806、906、TSV1、TSV2、TSV3、TSV4、TSV5、TSV6、TSV7：导电通孔；
510、610、710：第四衬底；
520、620、720：第三衬底；
540：第五衬底；
542、552、642a、642b、652a、652b、742a、742b、752a、752b：第二重布线层；
550：第六衬底；
640、740：第七衬底；
650、750：第八衬底；
670、770：打线结构；
804T、904T：上电极；
804B、904B：下电极；
812、822、912、922：重布线层；
814、914：绝缘层；
816、916：保护层；
820、920：第二衬底；
P1、P2、N：端点；
L、L1、L2、L3：电感元件；
C、C1、C2、C3：电容元件；
D、D1、D2、D3：间隙层；
S0、S0’、S1、S1’、S2、S3、S4、S5：表面；
A1、A2、A3、A4、A5：区域。
具体实施方式
被动式电子元件是射频(radio-frequency，RF)电路中一个重要的组成元件。目前许多的手持式无线设备，诸如智能型手机及平板计算机等设备，均包括大量的被动元件。因为手持式无线设备有轻薄短小的特性，方便携带，所以如何将电路缩小又不致影响系统的效能，便成为了重要的研究方向。目前三维集成电路构装的技术蓬勃发展，其重点即是在小面积基本需求下达到多功能的目的。本发明利用三维集成电路构装技术来实现具有被动式电子元件的电子电路。为更清楚地了解本发明，以下将配合附图，以至少一范例实施例来详细说明。另外，凡可能之处，在附图及实施方式中使用相同标号的元件/构件/符号代表相同或类似部分。
图1绘示本发明一实施例的芯片堆叠结构的概要示意图。图2绘示图1的芯片堆叠结构的等效电路图。请参考图1及图2，本实施例的芯片堆叠结构100包括多个第一衬底110、120及多个微凸块结构130。第一衬底110、120分别包括第一重布线层(redistribution layer，RDL)112、122。第一衬底110的第一重布线层112设置于其下表面S1，第一衬底120的第一重布线层122设置于其上表面S2。微凸块结构130连接第一重布线层112、122，以使第一衬底110稳定地接合于第一衬底120的上表面S2，从而提升芯片堆叠结构100的结构强度。并且，第一衬底110、120彼此之间通过第一重布线层112、122及微凸块结构130而彼此电性连接且传递电子信号。在此例中，第一重布线层112、122及微凸块结构130形成多个阻抗元件，包括电容元件及电感元件，并且所述阻抗元件的组合提供一特定的振荡频率。另外，第一重布线层112、122及微凸块结构130的材料可以是选自于金、铜、镍、银及其组合。
具体而言，在本实施例中，第一衬底110例如是中介层(Interposer)，第一衬底120例如是芯片层，两者之间具有间隙层D。此间隙层D中可填充有空气或惰性气体，当填充惰性气体时，可使第一重布线层112、122及微凸块结构130不易氧化，而保持芯片堆叠结构100的运作顺畅。另外，间隙层D中还可填充有绝缘填料(underfill)，可提升芯片堆叠结构100的结构强度。在电容结构的实施形式中，绝缘填料进一步作电容元件的介电材料。在本实施例中，所述阻抗元件包括位于间隙层D内左半部的电感结构，以及位于间隙层D内右半部的电容结构，此两结构具体实现在电路上为一组串联的电感元件L与电容元件C，如图2所示。此组串联的阻抗元件依据其电感值与电容值的设定，可提供一特定的振荡频率。
位于间隙层D内左半部的电感结构，利用设置于第一衬底110下表面S1的第一重布线层112a，作为电感结构上层的重布线层，并且利用设置于第一衬底120上表面S2的第一重布线层122a，作为电感结构下层的重布线层。此外，微凸块结构130电性连接电感结构上下两层的重布线层，以形成螺旋状的电感结构。此电感结构利用导电线路115a与左端点P1连接，左端点P1作为信号的输出入接垫，用以与其他电路连接，进行信号传递。此电感结构的右端点N与右半部的电容结构的下电极电路连接，形成串联组态。
位于间隙层D内右半部的电容结构，包括微凸块结构与重布线层的组合，分别利用第一衬底110、120的第一重布线层112b、122b作为电容结构的上下电极，其中之一为正电极，其中之另一为负电极。并且，微凸块结构130用以电性绝缘此上下两电极。与第一重布线层122b电性连接的微凸块结构130，延伸至第一衬底110时，以反环(anti-ring)结构113与第一衬底110接触，以与第一重布线层112b电性绝缘。类似地，与第一重布线层112b电性连接的微凸块结构130，延伸至第一衬底120时，也是以反环结构与第一衬底120接触，以与第一重布线层122b电性绝缘。此外，此电感结构的上重布线层利用导电线路115b与右端点P2连接，右端点P2作为信号的输出入接垫，用以与其他电路连接，进行信号传递。
上述芯片堆叠结构100利用第一重布线层112、122与微凸块结构130来实现串联组态的阻抗元件的组合，但本发明并不限于此，利用第一重布线层与微凸块结构也可实现并联组态的阻抗元件的组合。
图3绘示本发明另一实施例的芯片堆叠结构的概要示意图。图4绘示图3的芯片堆叠结构的等效电路图。请参考图3及图4，本实施例的芯片堆叠结构200类似于图1的芯片堆叠结构100，只是两者不同之处主要例如在于，芯片堆叠结构200包括一组并联的电感元件L与电容元件C，如图4所示。
具体而言，位于间隙层D内左半部的电感结构，类似于图1所揭露者，利用微凸块结构230电性连接电感结构上下两层的重布线层212a、222a，形成螺旋状的电感结构。位于间隙层D内右半部的电容结构，类似于图1所揭露者，重布线层212b、222b分别作为电容的上下电极，并且利用微凸块结构230的反环结构213彼此电性绝缘，以形成电容结构。在此例中，电感结构分别利用导电线路215a、215c与左端点P1以及电容的上电极连接，并且，电容的下电极与连接电感结构之处，利用导电线路215b拉线至端点P2。通过上述导电线路215a、215b、215c的布线方式，本实施例的电感元件L与电容元件C形成并联组态。
在上述两实施例中，所述阻抗元件都是位于两个衬底之间的同一间隙层中，因此，电感结构和电容结构属于水平排列的实施形式，但本发明并不加以限制。在其他实施例中，所述阻抗元件也可以是以垂直堆叠的方式来实现并联或串联组态的阻抗元件的组合。
图5绘示本发明另一实施例的芯片堆叠结构的概要示意图。图6绘示图5的芯片堆叠结构的等效电路图。请参考图5及图6，本实施例的芯片堆叠结构300包括垂直堆叠的一组并联的电感元件L与电容元件C，如图6所示。
详细而言，请参考图5及图6，本实施例的芯片堆叠结构300包括多个第一衬底310、320、340及多个微凸块结构330。第一衬底310包括第一重布线层312，设置于其下表面S1。第一衬底320包括第一重布线层322U、322D，分别设置于其上下表面S2、S3。第一衬底340包括第一重布线层342，设置于其上表面S4。微凸块结构330用以连接第一重布线层312、322U，并且用以连接第一重布线层322D、342，以使三个衬底稳定地接合，从而提升芯片堆叠结构300的结构强度。在此例中，第一重布线层312、322U及微凸块结构330在间隙层D1内形成电容结构，第一重布线层322D、342及微凸块结构330在间隙层D2内形成电感结构。在不同间隙层D1、D2内的电容结构与电感结构，利用贯穿第一衬底320的导电通孔327彼此电性连接。此外，本实施例的电感结构的上重布线层利用导电线路325a、325b分别与作为输出入接垫的左右端点P1、P2连接。在另一实施例中，导电线路325a、325b也可分别设置在第一重布线层312、322U，以连接电容结构的上下两电极与另两端点。因此，在本实施例中，所述阻抗元件在电路上包括垂直堆叠的一组并联的电感元件L与电容元件C，如图6所示。此组并联的阻抗元件依据其电感值与电容值的设定，可提供一特定的振荡频率。
上述芯片堆叠结构300利用第一重布线层312、322U、322D、342与微凸块结构430来实现垂直堆叠的并联组态的阻抗元件的组合，但本发明并不限于此，利用第一重布线层与微凸块结构也可实现垂直堆叠的串联组态的阻抗元件的组合。
图7绘示本发明另一实施例的芯片堆叠结构的概要示意图。图8绘示图7的芯片堆叠结构的等效电路图。请参考图7及图8，本实施例的芯片堆叠结构400类似于图5的芯片堆叠结构300，只是两者不同之处主要例如在于，芯片堆叠结构400包括垂直堆叠的一组串联的电感元件L与电容元件C，如图8所示。
具体而言，位于间隙层D2内电感结构，类似于图5所揭露者，利用微凸块结构430电性连接电感结构上下两层的重布线层422D、442，形成螺旋状的电感结构。位于间隙层D1内电容结构，类似于图5所揭露者，重布线层412、422U分别作为电容的上下电极，并且利用微凸块结构430的反环结构413彼此电性绝缘，以形成电容结构。在此例中，电容结构的上电极利用导电线路415a拉线至端点P1，并且，电感结构上层的重布线层422D利用导电线路425b与端点P2电性连接。通过上述导电线路415a、425b的布线方式，本实施例的电感元件L与电容元件C形成串联组态。
在上述两实施例中，所述阻抗元件是位于不同衬底之间的不同间隙层中，因此，电感结构和电容结构属于垂直堆叠的实施形式，但本发明并不加以限制。在其他实施例中，所述阻抗元件也可以综合水平排列与垂直堆叠的方式来实现并联及串联组态的阻抗元件的组合。
举例而言，芯片堆叠结构可包括多个微凸块结构、多个第一衬底以及多个第二衬底。所述第一衬底利用所述微凸块结构彼此堆叠，并且各第一衬底包括至少一第一重布线层。所述第二衬底利用所述微凸块结构与所述第一衬底至少其中之一堆叠，并且各第二衬底包括至少一第二重布线层。所述第一重布线层、所述第二重布线层以及所述微凸块结构形成多个阻抗元件。
具体而言，图9绘示本发明另一实施例的芯片堆叠结构的概要示意图。图10绘示图9的芯片堆叠结构的等效电路图。请参考图9及图10，在本实施例中，芯片堆叠结构500的所述多个第一衬底包括第三衬底520以及第四衬底510。芯片堆叠结构500的所述多个第二衬底包括第五衬底540以及第六衬底550。
进一步而言，第三衬底520具有彼此对向的第一表面S4与第二表面S5。第三衬底520的第一重布线层522配置于第三衬底520的第一表面S4。第四衬底510利用微凸块结构530堆叠在第三衬底520上，并且具有彼此对向的第一表面S2与第二表面S3。第四衬底510的第一重布线层512a、512b分别配置于第四衬底510的第一表面S2与第二表面S3。在此例中，配置于第四衬底510的第二表面S3的第一重布线层512b利用微凸块结构530与配置于第三衬底520的第一表面S4的第一重布线层522形成两个螺旋状的电感结构，分别位于间隙层D1内的左半部及右半部，两个电感结构之间利用第四衬底510的第二表面S3的第一重布线层512b上的导电线路515c，以串联方式连接。并且，位于间隙层D1内左右半部的两个电感结构分别利用导电线路515a、515b与左右端点P1、P2连接，以作为信号的输出入接垫。在另一实施例中，根据实际设计需求，利用改变导电线路515a、515b、515c的布局方式也可使两个电感结构以并联方式连接。此外，在另一实施例中，位于间隙层D1内的两个电感结构也可利用第三衬底520的第一表面S4的第一重布线层522上的导电线路(未绘示)，以串联或并联方式连接。
另一方面，在本实施例中，第五衬底540利用微凸块结构530堆叠在第四衬底510上，并且具有彼此对向的第一表面S0与第二表面S1。第五衬底540的第二重布线层542配置于第五衬底540的第二表面S1。第六衬底550利用微凸块结构530堆叠在第四衬底510上，并且具有彼此对向的第一表面S0’与第二表面S1’。第六衬底550的第二重布线层552配置于第六衬底550的第二表面S1’。在此例中，配置于第五衬底540的第二表面S1的第二重布线层542利用微凸块结构530与配置于第四衬底510的第一表面S2的第一重布线层512a形成电容元件C1。电容元件C1利用贯穿第四衬底510的导电通孔517a与电感元件L1以并联方式连接。利用不同的布线方式，电容元件C1与电感元件L1也可以串联方式连接。此外，配置于第六衬底550的第二表面S1’的第二重布线层552利用微凸块结构530与配置于第四衬底510的第一表面S2的第一重布线层512a形成电容元件C2。电容元件C2利用贯穿第四衬底510的导电通孔517b与电感元件L2以并联方式连接。利用不同的布线方式，电容元件C2与电感元件L2也可以串联方式连接。在本实施例中，电容元件C1、C2之间是利用贯穿第四衬底的导电通孔517a、517b以及导电线路515c以串联方式连接。或者，在另一实施例中，电容元件C1、C2之间也可利用第三衬底520的第一表面S4的第一重布线层522上的导电线路(未绘示)，以串联方式连接。此外，根据实际设计需求，利用不同的布线方式，电容元件C1、C2也可并联方式连接。
从另一观点来看，图9的芯片堆叠结构500也可视为是两个图5的芯片堆叠结构300的组合，其中，位于间隙层D1内两个电感结构是水平排列，并且共享第三衬底520的第一重布线层522以及第四衬底510的第一重布线层512b。接着，位于间隙层D2、D3内两个电容结构再分别以垂直堆叠的方式直接设置在位于间隙层D1内左右半部的两个电感结构上，并且以导电通孔与电感结构电性连接。
在本发明中，芯片堆叠结构的所述多个第二衬底之间也可利用重布线层、微凸块结构、导电通孔以及打线结构等布线方式来形成电容结构或电感结构。
图11绘示本发明另一实施例的芯片堆叠结构的概要示意图。图12绘示图11的芯片堆叠结构的等效电路图。请参考图11及图12，本实施例的芯片堆叠结构600类似于图9的芯片堆叠结构500，只是两者不同之处主要例如在于，芯片堆叠结构600的所述多个第二衬底之间包括电感结构，其等效电路为电感元件L3，耦接在两组并联组态的电感元件与电容元件之间，如图12所示。
具体而言，在本实施例中，芯片堆叠结构600的所述多个第二衬底包括第七衬底640以及第八衬底650。第七衬底640利用微凸块结构630堆叠在第四衬底610上，并且具有彼此对向的第一表面S0与第二表面S1。第七衬底640的第二重布线层642a、642b分别配置于第七衬底640的第一表面S0与第二表面S1。第八衬底650利用微凸块结构630堆叠在第四衬底610上，并且具有彼此对向的第一表面S0’与第二表面S1’。第八衬底650的第二重布线层652a、652b分别配置于第八衬底650的第一表面S0’与第二表面S1’。在本实施例中，第二重布线层642b利用微凸块结构630与第一重布线层612a形成电容元件C1。电容元件C1利用贯穿第四衬底610的导电通孔617a与电感元件L1以并联方式连接，只是本发明也不排除两者串联连接的实施形式。在此例中，电容元件C1是以并联方式与电感元件L1连接。此外，第二重布线层652b利用微凸块结构630与第一重布线层612a形成电容元件C2。电容元件C2利用贯穿第四衬底610的导电通孔617b与电感元件L2以并联方式连接，只是本发明也不排除两者串联连接的实施形式。
在本实施例中，芯片堆叠结构600还包括多个打线结构670。打线结构670连接第七衬底640的第一表面S0的第二重布线层642a与第八衬底650的第一表面S0’的第二重布线层652a。配置于第七衬底640的第一表面S0的第二重布线层642a利用贯穿第七衬底640的导电通孔647与配置于第二表面S1的第二重布线层642b连接。配置于第八衬底650的第一表面S0’的第二重布线层652a利用贯穿第八衬底的导电通孔657与配置于第二表面S1’的第二重布线层652b连接。因此，根据上述布线方式，在本实施例中，打线结构670、第四衬底610的导电线路612b、第二重布线层642a、652a、导电通孔647、657以及连接第七衬底640、第八衬底650与第四衬底610的微凸块结构630在第七衬底640和第八衬底650之间形成电感元件L3。在另一实施例中，第七衬底640与第八衬底650之间还包括高导磁系数材料，以提高电感元件L3的电感值。
此外，在另一实施例中，本发明的芯片堆叠结构的所述多个第二衬底之间也可利用重布线层、微凸块结构、导电通孔以及打线结构等布线方式来形成电容结构。
图13绘示本发明另一实施例的芯片堆叠结构的概要示意图。图14绘示图13的芯片堆叠结构的等效电路图。请参考图13及图14，本实施例的芯片堆叠结构700类似于图11的芯片堆叠结构600，只是两者不同之处主要例如在于，芯片堆叠结构700的所述多个第二衬底之间包括电容结构，其等效电路为电容元件C3，耦接在两组并联组态的电感元件与电容元件之间，如图14所示。对应于所述多个第二衬底之间的电容结构，第七衬底740与第八衬底750之间的布线方式也随之调整。
具体而言，在本实施例中，打线结构770连接第七衬底740的第二重布线层742a与第八衬底750的第二重布线层752a。第七衬底740的第二重布线层742a利用贯穿第七衬底740的导电通孔747与配置于第二重布线层742b连接。第八衬底750的第二重布线层752a利用贯穿第八衬底750的导电通孔757与第二重布线层752b连接。因此，根据上述布线方式，在本实施例中，打线结构770、第二重布线层742a、752a、导电通孔747、757以及连接第七衬底740、第八衬底750与第四衬底710的微凸块结构730在第七衬底740与第八衬底750之间形成电容元件C3。在另一实施例中，第七衬底740与第八衬底750之间还包括高介电系数材料，以提高电容元件C3的电容值。
下文进一步说明本发明的电容元件在芯片堆叠结构中的细部实施方式。
图15绘示本发明一实施例的电容元件的芯片堆叠结构的概要示意图。请参考图15，本实施例的芯片堆叠结构800包括第一衬底810、第二衬底820及微凸块结构830。第一衬底810的下表面与第二衬底820上表面分别设置有重布线层812、822，并且重布线层812、822与第一衬底810、第二衬底820以绝缘层814阻隔。在此例中，重布线层812、822的一部分重布线图样作为电容结构的上电极804T，另一部分重布线图样作为电容结构的下电极804B。微凸块结构830结合重布线层812、822的布线图样可电性绝缘电容结构的上下电极804T、804B。并且，在间隙层D可填充绝缘材料作为电容元件的介电材料。
举例而言，布线区域A1中显示了芯片堆叠结构800利用反环结构来电性绝缘上下电极804T、804B，在此区域中，电容结构的下电极804B环绕上电极804T，并且两者之间填充有保护层(passivation)816的绝缘材料，以形成电性绝缘的组态。类似地，布线区域A2中也显示了芯片堆叠结构800利用反环结构来电性绝缘上下电极804T、804B，只是在此区域中，是由电容结构的上电极804T来环绕下电极804B。
另外，在本实施例中，重布线层812利用多个导电通孔806将电容结构的上下电极804T、804B与芯片堆叠结构800其他的电子元件连接，以进行信号传递。另外，根据不同的应用需求，可任意选择电容结构的上下电极804T、804B作为正电极或负电极。例如，上电极804T可作为正电极，导电通孔TSV1、TSV3、TSV5、TSV7可偏压正电源，下电极804B可作为负电极，导电通孔TSV2、TSV4、TSV6可偏压负电源。
图16绘示本发明另一实施例之电容元件的芯片堆叠结构的概要示意图。请参考图16，本实施例的芯片堆叠结构900类似于图15的芯片堆叠结构800，只是两者不同之处主要例如在于，芯片堆叠结构900分别是以第一衬底910下表面的重布线层912和第二衬底920上表面的重布线层922当作电容结构的上电极904T与下电极904B。
在本实施例中，微凸块结构930配置在第一衬底910与第二衬底920之间，其与两衬底的重布线层912、922的连接方式包括保护开启(passivation open)和保护关闭(passivation close)的组态。如区域A5所示，微凸块结构930的下端在此区域A5以保护开启的组态直接与下电极904B电性连接。反之，如区域A4所示，保护层916阻隔在微凸块结构930的上端与上电极904T之间，以使两者彼此电性绝缘，形成保护关闭的组态。
另外，在本实施例中，重布线层912、922利用多个导电通孔906将电容结构的上下电极904T、904B与芯片堆叠结构900其他的电子元件连接，以进行信号传递。就下电极904B而言，导电通孔TSV2是用以将下电极904B的电讯号输出至其他的电子元件，区域A3的反环结构是用以电性绝缘上下电极904T、904B。在本实施例中，下电极904B例如作为正电极，导电通孔TSV2可偏压正电源，上电极904T例如作为负电极，导电通孔TSV1、TSV3可偏压负电源。另外，在此例中，导电通孔TSV2与区域A3的反环结构的位置分布可在第一衬底910下表面的任意位置。
另外，图15及图16揭露的电容结构也可应用在图1至图14的芯片堆叠结构中，其实施方式可以由图1至图14实施例的叙述中获致足够的教导、建议与实施说明，因此不再赘述。
综上所述，本发明的芯片堆叠结构包括多个利用微凸块结构、导电通孔以及多层芯片堆叠的方式形成的立体式绕线阻抗元件，这些阻抗元件彼此电性连接，具有良好电气特性。另外，本发明的芯片堆叠结构也可进一步利用打线结构来形成立体式绕线阻抗元件，并且在衬底之间填充高介电系数材料或高导磁系数材料来提高这些阻抗元件的电容值或电感值。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作部分的更改与修饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (17)

1.一种芯片堆叠结构，其特征在于，包括：
多个微凸块结构；
多个第一衬底，利用该些微凸块结构的一第一部分彼此堆叠，并且各该第一衬底包括至少一第一重布线层；
至少一第一间隙层，位于该些第一衬底之间，其中该第一部分微凸块结构设置于该至少一第一间隙层，用以连接所堆叠的该些第一衬底的该至少一第一重布线层；以及
多个第二衬底，利用该些微凸块结构的一第二部分与该些第一衬底至少其中之一堆叠，并且各该第二衬底包括至少一第二重布线层；以及
至少一第二间隙层，位于该些第一衬底与该些第二衬底之间，其中该第二部分微凸块结构设置于该至少一第二间隙层，用以连接所堆叠的该些第一衬底的该至少一第一重布线层和所堆叠的该些第二衬底的该至少一第二重布线层，
其中该些第一重布线层、该些第二重布线层以及该些微凸块结构形成多个阻抗元件，并且该些阻抗元件提供一特定的振荡频率。
2.根据权利要求1所述的芯片堆叠结构，其中该些第一衬底包括：
一第三衬底，具有彼此对向的第一表面与第二表面，该第三衬底的该第一重布线层配置于该第三衬底的该第一表面；以及
一第四衬底，利用该第一部分微凸块结构堆叠在该第三衬底上，并且具有彼此对向的第一表面与第二表面，该第四衬底的该些第一重布线层分别配置于该第四衬底的该第一表面与该第二表面，
其中配置于该第四衬底的该第二表面的该第一重布线层利用该第一部分微凸块结构与配置于该第三衬底的该第一表面的该第一重布线层形成该些阻抗元件中的至少一第一阻抗元件。
3.根据权利要求2所述的芯片堆叠结构，其中该些第一阻抗元件之间利用该第四衬底的该第二表面的该第一重布线层上的一导电线路，或者该第三衬底的该第一表面的该第一重布线层上的一导电线路，以串联或并联方式连接。
4.根据权利要求2所述的芯片堆叠结构，其中配置于该第四衬底的该第一表面的该第一重布线层利用贯穿该第四衬底的至少一导电通孔与配置于该第四衬底的该第二表面的该第一重布线层连接。
5.根据权利要求2所述的芯片堆叠结构，其中该些第二衬底包括：
一第五衬底，利用该第二部分微凸块结构堆叠在该第四衬底上，并且具有彼此对向的第一表面与第二表面，该第五衬底的该第二重布线层配置于该第五衬底的该第二表面；以及
一第六衬底，利用该第二部分微凸块结构堆叠在该第四衬底上，并且具有彼此对向的第一表面与第二表面，该第六衬底的该第二重布线层配置于该第六衬底的该第二表面，
其中配置于该第五衬底的该第二表面的该第二重布线层利用该第二部分微凸块结构与配置于该第四衬底的该第一表面的该第一重布线层形成该些阻抗元件中的至少一第二阻抗元件，以及
其中配置于该第六衬底的该第二表面的该第二重布线层利用该第二部分微凸块结构与配置于该第四衬底的该第一表面的该第一重布线层形成该些阻抗元件中的至少一第三阻抗元件。
6.根据权利要求5所述的芯片堆叠结构，其中该至少一第二阻抗元件利用贯穿该第四衬底的至少一导电通孔与该至少一第一阻抗元件以串联或并联方式连接。
7.根据权利要求5所述的芯片堆叠结构，其中该至少一第三阻抗元件利用贯穿该第四衬底的至少一导电通孔与该至少一第一阻抗元件以串联或并联方式连接。
8.根据权利要求5所述的芯片堆叠结构，其中该至少一第二阻抗元件与该至少一第三阻抗元件之间利用贯穿该第四衬底的至少一导电通孔，以及该第四衬底的该第二表面的该第一重布线层上的一导电线路或者该第三衬底的该第一表面的该第一重布线层上的一导电线路，以串联或并联方式连接。
9.根据权利要求2所述的芯片堆叠结构，其中该些第二衬底包括：
一第七衬底，利用该第二部分微凸块结构堆叠在该第四衬底上，并且具有彼此对向的第一表面与第二表面，该第七衬底的该些第二重布线层分别配置于该第七衬底的该第一表面与该第二表面；以及
一第八衬底，利用该第二部分微凸块结构堆叠在该第四衬底上，并且具有彼此对向的第一表面与第二表面，该第八衬底的该些第二重布线层分别配置于该第八衬底的该第一表面与该第二表面，
其中配置于该第七衬底的该第二表面的该第二重布线层利用该第二部分微凸块结构与配置于该第四衬底的该第一表面的该第一重布线层形成该些阻抗元件中的至少一第五阻抗元件，以及
其中配置于该第八衬底的该第二表面的该第二重布线层利用该第二部分微凸块结构与配置于该第四衬底的该第一表面的该第一重布线层形成该些阻抗元件中的至少一第六阻抗元件。
10.根据权利要求9所述的芯片堆叠结构，其中该至少一第五阻抗元件利用贯穿该第四衬底的至少一导电通孔与该至少一第一阻抗元件以串联或并联方式连接。
11.根据权利要求9所述的芯片堆叠结构，其中该至少一第六阻抗元件利用贯穿该第四衬底的至少一导电通孔与该至少一第一阻抗元件以串联或并联方式连接。
12.根据权利要求9所述的芯片堆叠结构，其特征在于，还包括：
多个打线结构，连接该第七衬底的该第一表面的该第二重布线层与该第八衬底的该第一表面的该第二重布线层。
13.根据权利要求12所述的芯片堆叠结构，其中配置于该第七衬底的该第一表面的该第二重布线层利用贯穿该第七衬底的至少一导电通孔与配置于该第七衬底的该第二表面的该第二重布线层连接，以及配置于该第八衬底的该第一表面的该第二重布线层利用贯穿该第八衬底的至少一导电通孔与配置于该第八衬底的该第二表面的该第二重布线层连接。
14.根据权利要求13所述的芯片堆叠结构，其中该些打线结构、该第七衬底与该第八衬底的该些第二重布线层、贯穿该第七衬底与该第八衬底的该些导电通孔以及连接第七衬底、该第八衬底与该第四衬底的该第二部分微凸块结构形成该些阻抗元件中的至少一第七阻抗元件。
15.根据权利要求14所述的芯片堆叠结构，其中该第七衬底与该第八衬底之间还包括高介电系数材料，以提高该至少一第七阻抗元件的电容值。
16.根据权利要求13所述的芯片堆叠结构，其中该些打线结构、该第四衬底的该第一表面的该第一重布线层上的一导电线路、该第七衬底与该第八衬底的该些第二重布线层、贯穿该第七衬底与该第八衬底的该些导电通孔以及连接该第七衬底、该第八衬底与该第四衬底的部分该第二部分微凸块结构形成该些阻抗元件中的至少一第八阻抗元件。
17.根据权利要求16所述的芯片堆叠结构，其中该第七衬底与该第八衬底之间还包括高导磁系数材料，以提高该至少一第八阻抗元件的电感值。
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