TWI479640B - 晶片堆疊結構 - Google Patents

晶片堆疊結構 Download PDF

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Publication number
TWI479640B
TWI479640B TW101149886A TW101149886A TWI479640B TW I479640 B TWI479640 B TW I479640B TW 101149886 A TW101149886 A TW 101149886A TW 101149886 A TW101149886 A TW 101149886A TW I479640 B TWI479640 B TW I479640B
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Taiwan
Prior art keywords
substrate
redistribution layer
disposed
microbump
wafer stack
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TW101149886A
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English (en)
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TW201426961A (zh
Inventor
Chang Chih Liu
Hsun Yu
Peng Shu Chen
Shih Hsien Wu
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Ind Tech Res Inst
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Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW101149886A priority Critical patent/TWI479640B/zh
Priority to CN201310089368.5A priority patent/CN103904053B/zh
Priority to US13/912,207 priority patent/US9013892B2/en
Publication of TW201426961A publication Critical patent/TW201426961A/zh
Application granted granted Critical
Publication of TWI479640B publication Critical patent/TWI479640B/zh

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Description

晶片堆疊結構
本揭露是有關於一種晶片堆疊結構，且特別是有關於一種三維晶片堆疊結構(three-dimensional chip stacking structure)。
近代電子產業隨著摩爾定律規範(Moore’s Law)而蓬勃發展。然而，隨著電子產品的運算速度提升等需求，技術的瓶頸也逐漸產生。為了讓電子產品的性能跟上需求，於是，三維積體電路構裝(3D IC integration)技術成為現今解決問題的辦法之一。三維積體電路構裝技術相較於一般傳統封裝形式擁有許多優點，例如元件尺寸較小、較少的訊號損失與較好的電性性能，這些都是因為使用矽導通孔的緣故。
矽導通孔(Through Silicon Via,TSV)與微凸塊(microbump)結構已成為三維積體電路構裝技術的重要核心。典型含矽導通孔的中介層(TSV interposer)的三維積體電路整合系統級封裝(3D IC SiP)結構，其中，中介層利用微凸塊(microbump)結構，在上下方皆可承載晶片，且透過焊錫凸塊(solder bump)結構而可與基板(substrate)或印刷電路板(PCB)連結。因此，三維積體電路構裝技術為提升電子產品性能的最有效架構之一，可允許多個晶片間的相互連結，將更多的運算能力、記憶體和其他功能整合在同一 極小裝置內。
本揭露提供一種晶片堆疊結構，包括多個微凸塊結構、多個第一基板、至少一第一間隙層、多個第二基板以及至少一第二間隙層。所述第一基板利用所述微凸塊結構之第一部份彼此堆疊，並且各第一基板包括至少一第一重佈線層。第一間隙層位於第一基板之間。第一部份微凸塊結構設置於第一間隙層，用以連接所堆疊的第一基板的第一重佈線層。所述第二基板利用所述微凸塊結構之第二部份與所述第一基板至少其中之一堆疊，並且各第二基板包括至少一第二重佈線層。第二間隙層位於第一基板與第二基板之間。第二部份微凸塊結構設置於第二間隙層，用以連接所堆疊的第一基板的第一重佈線層和所堆疊的第二基板的第二重佈線層。所述第一重佈線層、所述第二重佈線層以及所述微凸塊結構形成多個阻抗元件，並且所述阻抗元件提供一特定的振盪頻率。
基於上述，本揭露的晶片堆疊結構包括多個利用微凸塊結構、導電通孔以及多層晶片堆疊的方式形成的立體式繞線阻抗元件，此些阻抗元件彼此電性連接，具有良好電氣特性。
為讓本揭露之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
被動式電子元件是射頻(radio-frequency，RF)電路中一個重要的組成元件。目前許多的手持式無線設備，諸如智慧型手機及平板電腦等設備，均包括大量的被動元件。因為手持式無線設備有輕薄短小的特性，方便攜帶，所以如何將電路縮小又不致影響系統的效能，便成為了重要的研究方向。目前三維積體電路構裝的技術蓬勃發展，其重點即是在小面積基本需求下達到多功能的目的。本揭露利用三維積體電路構裝技術來實現具有被動式電子元件的電子電路。為更清楚地瞭解本揭露，以下將配合圖式，以至少一範例實施例來詳細說明。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/符號代表相同或類似部分。
圖1繪示本揭露一實施例之晶片堆疊結構的概要示意圖。圖2繪示圖1之晶片堆疊結構的等效電路圖。請參考圖1及圖2，本實施例之晶片堆疊結構100包括多個第一基板110、120及多個微凸塊結構130。第一基板110、120分別包括第一重佈線層(redistribution layer，RDL)112、122。第一基板110的第一重佈線層112設置於其下表面S1，第一基板120的第一重佈線層122設置於其上表面S2。微凸塊結構130連接第一重佈線層112、122，以使第一基板110穩定地接合於第一基板120的上表面S2，從而提升晶片堆疊結構100的結構強度。並且，第一基板110、120彼此之間透過第一重佈線層112、122及微凸塊結構130 而彼此電性連接且傳遞電子訊號。在此例中，第一重佈線層112、122及微凸塊結構130形成多個阻抗元件，包括電容元件及電感元件，並且所述阻抗元件的組合提供一特定的振盪頻率。另外，第一重佈線層112、122及微凸塊結構130的材料可以是選自於金、銅、鎳、銀及其組合。
具體而言，在本實施例中，第一基板110例如是中介層(Interposer)，第一基板120例如是晶片層，兩者之間具有間隙層D。此間隙層D中可填充有空氣或惰性氣體，當填充惰性氣體時，可使第一重佈線層112、122及微凸塊結構130不易氧化，而保持晶片堆疊結構100的運作順暢。另外，間隙層D中還可填充有絕緣填料(underfill)，可提升晶片堆疊結構100的結構強度。在電容結構的實施態樣中，絕緣填料係進一步作電容元件的介電材料。在本實施例中，所述阻抗元件包括位於間隙層D內左半部的電感結構，以及位於間隙層D內右半部的電容結構，此兩結構具體實現在電路上為一組串聯的電感元件L與電容元件C，如圖2所示。此組串聯的阻抗元件依據其電感值與電容值的設定，可提供一特定的振盪頻率。
位於間隙層D內左半部的電感結構，利用設置於第一基板110下表面S1的第一重佈線層112a，作為電感結構上層的重佈線層，並且利用設置於第一基板120上表面S2的第一重佈線層122a，作為電感結構下層的重佈線層。此外，微凸塊結構130電性連接電感結構上下兩層的重佈線層，以形成螺旋狀的電感結構。此電感結構利用導電線路 115a與左端點P1連接，左端點P1作為訊號的輸出入接墊，用以與其他電路連接，進行訊號傳遞。此電感結構的右端點N與右半部的電容結構的下電極電路連接，形成串聯組態。
位於間隙層D內右半部的電容結構，包括微凸塊結構與重佈線層的組合，分別利用第一基板110、120的第一重佈線層112b、122b作為電容結構的上下電極，其中之一為正電極，其中之另一為負電極。並且，間隙層D填充的絕緣填料用以電性絕緣此上下兩電極。與第一重佈線層122b電性連接的微凸塊結構130，延伸至第一基板110時，係以反環(anti-ring)結構113與第一基板110接觸，以與第一重佈線層112b電性絕緣。類似地，與第一重佈線層112b電性連接的微凸塊結構130，延伸至第一基板120時，也是以反環結構與第一基板120接觸，以與第一重佈線層122b電性絕緣。此外，此電感結構的上重佈線層利用導電線路115b與右端點P2連接，右端點P2作為訊號的輸出入接墊，用以與其他電路連接，進行訊號傳遞。
上述晶片堆疊結構100利用第一重佈線層112、122與微凸塊結構130來實現串聯組態的阻抗元件之組合，但本揭露並不限於此，利用第一重佈線層與微凸塊結構也可實現並聯組態的阻抗元件之組合。
圖3繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖4繪示圖3之晶片堆疊結構的等效電路圖。請參考圖3及圖4，本實施例之晶片堆疊結構200類似於圖1 的晶片堆疊結構100，惟兩者不同之處主要例如在於，晶片堆疊結構200包括一組並聯的電感元件L與電容元件C，如圖4所示。
具體而言，位於間隙層D內左半部的電感結構，類似於圖1所揭露者，利用微凸塊結構230電性連接電感結構上下兩層的重佈線層212a、222a，形成螺旋狀的電感結構。位於間隙層D內右半部的電容結構，類似於圖1所揭露者，重佈線層212b、222b分別作為電容的上下電極，並且利用微凸塊結構230的反環結構213彼此電性絕緣，以形成電容結構。在此例中，電感結構分別利用導電線路215a、215c與左端點P1以及電容的上電極連接，並且，電容的下電極與連接電感結構之處，利用導電線路215b拉線至端點P2。藉由上述導電線路215a、215b、215c的佈線方式，本實施例的電感元件L與電容元件C形成並聯組態。
在上述兩實施例中，所述阻抗元件都是位在兩個基板之間的同一間隙層中，因此，電感結構和電容結構屬於水平排列的實施態樣，但本揭露並不加以限制。在其他實施例中，所述阻抗元件也可以是以垂直堆疊的方式來實現並聯或串聯組態的阻抗元件之組合。
圖5繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖6繪示圖5之晶片堆疊結構的等效電路圖。請參考圖5及圖6，本實施例之晶片堆疊結構300包括垂直堆疊的一組並聯的電感元件L與電容元件C，如圖6所示。
詳細而言，請參考圖5及圖6，本實施例之晶片堆疊結構300包括多個第一基板310、320、340及多個微凸塊結構330。第一基板310包括第一重佈線層312，設置於其下表面S1。第一基板320包括第一重佈線層322U、322D，分別設置於其上下表面S2、S3。第一基板340包括第一重佈線層342，設置於其上表面S4。微凸塊結構330用以連接第一重佈線層312、322U，並且用以連接第一重佈線層322D、342，以使三個基板穩定地接合，從而提升晶片堆疊結構300的結構強度。在此例中，第一重佈線層312、322U及微凸塊結構330在間隙層D1內形成電容結構，第一重佈線層322D、342及微凸塊結構330在間隙層D2內形成電感結構。在不同間隙層D1、D2內的電容結構與電感結構，利用貫穿第一基板320的導電通孔327彼此電性連接。此外，本實施例的電感結構的上重佈線層利用導電線路325a、325b分別與作為輸出入接墊的左右端點P1、P2連接。在另一實施例中，導電線路325a、325b也可分別設置在第一重佈線層312、322U，以連接電容結構的上下兩電極與另兩端點。因此，在本實施例中，所述阻抗元件在電路上包括垂直堆疊的一組並聯的電感元件L與電容元件C，如圖6所示。此組並聯的阻抗元件依據其電感值與電容值的設定，可提供一特定的振盪頻率。
上述晶片堆疊結構300利用第一重佈線層312、322U、322D、342與微凸塊結構330來實現垂直堆疊的並聯組態的阻抗元件之組合，但本揭露並不限於此，利用第 一重佈線層與微凸塊結構也可實現垂直堆疊的串聯組態的阻抗元件之組合。
圖7繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖8繪示圖7之晶片堆疊結構的等效電路圖。請參考圖7及圖8，本實施例之晶片堆疊結構400類似於圖5的晶片堆疊結構300，惟兩者不同之處主要例如在於，晶片堆疊結構400包括垂直堆疊的一組串聯的電感元件L與電容元件C，如圖8所示。
具體而言，位於間隙層D2內電感結構，類似於圖5所揭露者，利用微凸塊結構430電性連接電感結構上下兩層的重佈線層422D、442，形成螺旋狀的電感結構。位於間隙層D1內電容結構，類似於圖5所揭露者，重佈線層412、422U分別作為電容的上下電極，並且利用微凸塊結構430的反環結構413彼此電性絕緣，以形成電容結構。在此例中，電容結構的上電極利用導電線路415a拉線至端點P1，並且，電感結構上層的重佈線層422D利用導電線路425b與端點P2電性連接。藉由上述導電線路415a、425b的佈線方式，本實施例的電感元件L與電容元件C形成串聯組態。
在上述兩實施例中，所述阻抗元件是位在不同基板之間的不同間隙層中，因此，電感結構和電容結構屬於垂直堆疊的實施態樣，但本揭露並不加以限制。在其他實施例中，所述阻抗元件也可以綜合水平排列與垂直堆疊的方式來實現並聯及串聯組態的阻抗元件之組合。
舉例而言，晶片堆疊結構可包括多個微凸塊結構、多個第一基板以及多個第二基板。所述第一基板利用所述微凸塊結構彼此堆疊，並且各第一基板包括至少一第一重佈線層。所述第二基板利用所述微凸塊結構與所述第一基板至少其中之一堆疊，並且各第二基板包括至少一第二重佈線層。所述第一重佈線層、所述第二重佈線層以及所述微凸塊結構形成多個阻抗元件。
具體而言，圖9繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖10繪示圖9之晶片堆疊結構的等效電路圖。請參考圖9及圖10，在本實施例中，晶片堆疊結構500的所述多個第一基板包括第三基板520以及第四基板510。晶片堆疊結構500的所述多個第二基板包括第五基板540以及第六基板550。
進一步而言，第三基板520具有彼此對向的第一表面S4與第二表面S5。第三基板520的第一重佈線層522配置於第三基板520的第一表面S4。第四基板510利用微凸塊結構530堆疊在第三基板520上，並且具有彼此對向的第一表面S2與第二表面S3。第四基板510的第一重佈線層512a、512b分別配置於第四基板510的第一表面S2與第二表面S3。在此例中，配置於第四基板510的第二表面S3的第一重佈線層512b利用微凸塊結構530與配置於第三基板520的第一表面S4的第一重佈線層522形成兩個螺旋狀的電感結構，分別位於間隙層D1內的左半部及右半部，兩個電感結構之間係利用第四基板510的第二表面 S3的第一重佈線層512b上的導電線路515c，以串聯方式連接。並且，位於間隙層D1內左右半部的兩個電感結構分別利用導電線路515a、515b與左右端點P1、P2連接，以作為訊號的輸出入接墊。在另一實施例中，根據實際設計需求，利用改變導電線路515a、515b、515c的佈局方式也可使兩個電感結構以並聯方式連接。此外，在另一實施例中，位於間隙層D1內的兩個電感結構也可利用第三基板520的第一表面S4的第一重佈線層522上的導電線路(未繪示)，以串聯或並聯方式連接。
另一方面，在本實施例中，第五基板540利用微凸塊結構530堆疊在第四基板510上，並且具有彼此對向的第一表面S0與第二表面S1。第五基板540的第二重佈線層542配置於第五基板540的第二表面S1。第六基板550利用微凸塊結構530堆疊在第四基板510上，並且具有彼此對向的第一表面S0’與第二表面S1’。第六基板550的第二重佈線層552配置於第六基板550的第二表面S1’。在此例中，配置於第五基板540的第二表面S1的第二重佈線層542利用微凸塊結構530與配置於第四基板510的第一表面S2的第一重佈線層512a形成電容元件C1。電容元件C1利用貫穿第四基板510的導電通孔517a與電感元件L1以並聯方式連接。利用不同的佈線方式，電容元件C1與電感元件L1也可以串聯方式連接。此外，配置於第六基板550的第二表面S1’的第二重佈線層552利用微凸塊結構530與配置於第四基板510的第一表面S2的第一重佈 線層512a形成電容元件C2。電容元件C2利用貫穿第四基板510的導電通孔517b與電感元件L2以並聯方式連接。利用不同的佈線方式，電容元件C2與電感元件L2也可以串聯方式連接。在本實施例中，電容元件C1、C2之間是利用貫穿第四基板的導電通孔517a、517b以及導電線路515c以串聯方式連接。或者，在另一實施例中，電容元件C1、C2之間也可利用第三基板520的第一表面S4的第一重佈線層522上的導電線路(未繪示)，以串聯方式連接。此外，根據實際設計需求，利用不同的佈線方式，電容元件C1、C2也可並聯方式連接。
從另一觀點來看，圖9的晶片堆疊結構500也可視為是兩個圖5的晶片堆疊結構300之組合，其中，位在間隙層D1內兩個電感結構是水平排列，並且共用第三基板520的第一重佈線層522以及第四基板510的第一重佈線層512b。接著，位在間隙層D2、D3內兩個電容結構再分別以垂直堆疊的方式直接設置在位於間隙層D1內左右半部的兩個電感結構上，並且以導電通孔與電感結構電性連接。
在本揭露中，晶片堆疊結構的所述多個第二基板之間也可利用重佈線層、微凸塊結構、導電通孔以及打線結構等佈線方式來形成電容結構或電感結構。
圖11繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖12繪示圖11之晶片堆疊結構的等效電路圖。請參考圖11及圖12，本實施例之晶片堆疊結構600類似於圖9的晶片堆疊結構500，惟兩者不同之處主要例如在 於，晶片堆疊結構600的所述多個第二基板之間包括電感結構，其等效電路為電感元件L3，耦接在兩組並聯組態的電感元件與電容元件之間，如圖12所示。
具體而言，在本實施例中，晶片堆疊結構600的所述多個第二基板包括第七基板640以及第八基板650。第七基板640利用微凸塊結構630堆疊在第四基板610上，並且具有彼此對向的第一表面S0與第二表面S1。第七基板640的第二重佈線層642a、642b分別配置於第七基板640的第一表面S0與第二表面S1。第八基板650利用微凸塊結構630堆疊在第四基板610上，並且具有彼此對向的第一表面S0’與第二表面S1’。第八基板650的第二重佈線層652a、652b分別配置於第八基板650的第一表面S0’與第二表面S1’。在本實施例中，第二重佈線層642b利用微凸塊結構630與第一重佈線層612a形成電容元件C1。電容元件C1利用貫穿第四基板610的導電通孔617a與電感元件L1以並聯方式連接，惟本揭露亦不排除兩者串聯連接的實施態樣串。在此例中，電容元件C1是以並聯方式與電感元件L1連接。此外，第二重佈線層652b利用微凸塊結構630與第一重佈線層612a形成電容元件C2。電容元件C2利用貫穿第四基板610的導電通孔617b與電感元件L2以並聯方式連接，惟本揭露亦不排除兩者串聯連接的實施態樣。
在本實施例中，晶片堆疊結構600更包括多個打線結構670。打線結構670連接第七基板640的第一表面S0的 第二重佈線層642a與第八基板650的第一表面S0’的第二重佈線層652a。配置於第七基板640的第一表面S0的第二重佈線層642a利用貫穿第七基板640的導電通孔647與配置於第二表面S1的第二重佈線層642b連接。配置於第八基板650的第一表面S0’的第二重佈線層652a利用貫穿第八基板的導電通孔657與配置於第二表面S1’的第二重佈線層652b連接。因此，根據上述佈線方式，在本實施例中，打線結構670、第四基板610的導電線路612b、第二重佈線層642a、652a、導電通孔647、657以及連接第七基板640、第八基板650與第四基板610的微凸塊結構630在第七基板640和第八基板650之間形成電感元件L3。在另一實施例中，第七基板640與第八基板650之間更包括高導磁係數材料，以提高電感元件L3的電感值。
此外，在另一實施例中，本揭露的晶片堆疊結構的所述多個第二基板之間也可利用重佈線層、微凸塊結構、導電通孔以及打線結構等佈線方式來形成電容結構。
圖13繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。圖14繪示圖13之晶片堆疊結構的等效電路圖。請參考圖13及圖14，本實施例之晶片堆疊結構700類似於圖11的晶片堆疊結構600，惟兩者不同之處主要例如在於，晶片堆疊結構700的所述多個第二基板之間包括電容結構，其等效電路為電容元件C3，耦接在兩組並聯組態的電感元件與電容元件之間，如圖14所示。對應於所述多個第二基板之間的電容結構，第七基板740與第八基板750 之間的佈線方式亦隨之調整。
具體而言，在本實施例中，打線結構770連接第七基板740的第二重佈線層742a與第八基板750的第二重佈線層752a。第七基板740的第二重佈線層742a利用貫穿第七基板740的導電通孔747與配置於第二重佈線層742b連接。第八基板750的第二重佈線層752a利用貫穿第八基板750的導電通孔757與第二重佈線層752b連接。因此，根據上述佈線方式，在本實施例中，打線結構770、第二重佈線層742a、752a、導電通孔747、757以及連接第七基板740、第八基板750與第四基板710的微凸塊結構730在第七基板740與第八基板750之間形成電容元件C3。在另一實施例中，第七基板740與第八基板750之間更包括高介電係數材料，以提高電容元件C3的電容值。
底下進一步說明本揭露的電容元件在晶片堆疊結構中的細部實施方式。
圖15繪示本揭露一實施例之電容元件的晶片堆疊結構的概要示意圖。請參考圖15，本實施例之晶片堆疊結構800包括第一基板810、第二基板820及微凸塊結構830。第一基板810的下表面與第二基板820上表面分別設置有重佈線層812、822，並且重佈線層812、822與第一基板810、第二基板820以絕緣層814阻隔。在此例中，重佈線層812、822的一部份重佈線圖樣作為電容結構的上電極804T，另一部份重佈線圖樣作為電容結構的下電極804B。微凸塊結構830結合重佈線層812、822的佈線圖樣可電性 絕緣電容結構的上下電極804T、804B。並且，在間隙層D可填充絕緣材料作為電容元件的介電材料。
舉例而言，佈線區域A1中顯示了晶片堆疊結構800利用反環結構來電性絕緣上下電極804T、804B，在此區域中，電容結構的下電極804B環繞上電極804T，並且兩者之間填充有保護層(passivation)816的絕緣材料，以形成電性絕緣的組態。類似地，佈線區域A2中也顯示了晶片堆疊結構800利用反環結構來電性絕緣上下電極804T、804B，惟在此區域中，是由電容結構的上電極804T來環繞下電極804B。
另外，在本實施例中，重佈線層812利用多個導電通孔806將電容結構的上下電極804T、804B與晶片堆疊結構800其他的電子元件連接，以進行訊號傳遞。另外，根據不同的應用需求，可任意選擇電容結構的上下電極804T、804B作為正電極或負電極。例如，上電極804T可作為正電極，導電通孔TSV1、TSV3、TSV5、TSV7可偏壓正電源，下電極804B可作為負電極，導電通孔TSV2、TSV4、TSV6可偏壓負電源。
圖16繪示本揭露另一實施例之電容元件的晶片堆疊結構的概要示意圖。請參考圖16，本實施例之晶片堆疊結構900類似於圖15的晶片堆疊結構800，惟兩者不同之處主要例如在於，晶片堆疊結構900分別是以第一基板910下表面的重佈線層912和第二基板920上表面的重佈線層922當作電容結構的上電極904T與下電極904B。
在本實施例中，微凸塊結構930配置在第一基板910與第二基板920之間，其與兩基板的重佈線層912、922的連接方式包括保護開啟(passivation open)和保護關閉(passivation close)的組態。如區域A5所示，微凸塊結構930之下端在此區域A5以保護開啟的組態直接與下電極904B電性連接。反之，如區域A4所示，保護層916阻隔在微凸塊結構930之上端與上電極904T之間，以使兩者彼此電性絕緣，形成保護關閉的組態。
另外，在本實施例中，重佈線層912、922利用多個導電通孔906將電容結構的上下電極904T、904B與晶片堆疊結構900其他的電子元件連接，以進行訊號傳遞。就下電極904B而言，導電通孔TSV2是用以將下電極904B的電訊號輸出至其他的電子元件，區域A3的反環結構是用以電性絕緣上下電極904T、904B。在本實施例中，下電極904B例如作為正電極，導電通孔TSV2可偏壓正電源，上電極904T例如作為負電極，導電通孔TSV1、TSV3可偏壓負電源。另外，在此例中，導電通孔TSV2的與區域A3的反環結構的位置分佈可在第一基板910下表面的任意位置。
另外，圖15及圖16揭露之電容結構亦可應用在圖1至圖14的晶片堆疊結構中，其實施方式可以由圖1至圖14實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。
綜上所述，本揭露的晶片堆疊結構包括多個利用微凸 塊結構、導電通孔以及多層晶片堆疊的方式形成的立體式繞線阻抗元件，此些阻抗元件彼此電性連接，具有良好電氣特性。另外，本揭露的晶片堆疊結構也可進一步利用打線結構來形成立體式繞線阻抗元件，並且在基板之間填充高介電係數材料或高導磁係數材料來提高此些阻抗元件的電容值或電感值。
雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作些許之更動與潤飾，故本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100、200、300、400、500、600、700、800、900‧‧‧晶片堆疊結構
110、120、210、220、310、320、340、410、420、440、810、910‧‧‧第一基板
112、112a、112b、122、122a、122b、212、212a、212b、222、222a、222b、312、322U、322D、342、412、422U、422D、442、522、512a、512b、612a、612b、712a‧‧‧第一重佈線層
113、213、413‧‧‧反環結構
115a、115b、215a、215b、215c、325a、325b、415a、425b、515a、515b、515c‧‧‧導電線路
130、230、330、430、530、630、830、930‧‧‧微凸塊結構
327、427、517a、517b、617a、617b、617c、647、657、747、757、806、906、TSV1、TSV2、TSV3、TSV4、TSV5、TSV6、TSV7‧‧‧導電通孔
510、610、710‧‧‧第四基板
520、620、720‧‧‧第三基板
540‧‧‧第五基板
542、552、642a、642b、652a、652b、742a、742b、752a、752b‧‧‧第二重佈線層
550‧‧‧第六基板
640、740‧‧‧第七基板
650、750‧‧‧第八基板
670、770‧‧‧打線結構
804T、904T‧‧‧上電極
804B、904B‧‧‧下電極
812、822、912、922‧‧‧重佈線層
814、914‧‧‧絕緣層
816、916‧‧‧保護層
820、920‧‧‧第二基板
P1、P2、N‧‧‧端點
L、L1、L2、L3‧‧‧電感元件
C、C1、C2、C3‧‧‧電容元件
D、D1、D2、D3‧‧‧間隙層
S0、S0’、S1、S1’、S2、S3、S4、S5‧‧‧表面
A1、A2、A3、A4、A5‧‧‧區域
圖1繪示本揭露一實施例之晶片堆疊結構的概要示意圖。
圖2繪示圖1之晶片堆疊結構的等效電路圖。
圖3繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖4繪示圖3之晶片堆疊結構的等效電路圖。
圖5繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖6繪示圖5之晶片堆疊結構的等效電路圖。
圖7繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖8繪示圖7之晶片堆疊結構的等效電路圖。
圖9繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖10繪示圖9之晶片堆疊結構的等效電路圖。
圖11繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖12繪示圖11之晶片堆疊結構的等效電路圖。
圖13繪示本揭露另一實施例之晶片堆疊結構的概要示意圖。
圖14繪示圖13之晶片堆疊結構的等效電路圖。
圖15繪示本揭露一實施例之電容元件的晶片堆疊結構的概要示意圖。
圖16繪示本揭露另一實施例之電容元件的晶片堆疊結構的概要示意圖。
500‧‧‧晶片堆疊結構
510‧‧‧第四基板
515a、515b、515c‧‧‧導電線路
520‧‧‧第三基板
517a、517b‧‧‧導電通孔
522、512a、512b‧‧‧第一重佈線層
530‧‧‧微凸塊結構
540‧‧‧第五基板
542、552‧‧‧第二重佈線層
550‧‧‧第六基板
P1、P2‧‧‧端點
D1、D2、D3‧‧‧間隙層
S0、S0’、S1、S1’、S2、S3、S4、S5‧‧‧表面

Claims (17)

  1. 一種晶片堆疊結構，包括：多個微凸塊結構；多個第一基板，具有至少一第一重佈線層，包括：一第三基板，該至少一第一重佈線層配置於該第三基板的一第一表面；一第四基板，利用該些微凸塊結構之第一部份堆疊在該第三基板上，該至少一第一重佈線層分別配置於該第四基板的該第一表面與該第二表面；至少一第一間隙層，位於該些第一基板之間，其中該第一部份微凸塊結構設置於該至少一第一間隙層，用以連接所堆疊的該些第一基板的該至少一第一重佈線層；以及多個第二基板，利用該些微凸塊結構之一第二部份堆疊在該第四基板上，並且各該第二基板包括至少一第二重佈線層；以及至少一第二間隙層，位於該些第一基板與該些第二基板之間，其中該第二部份微凸塊結構設置於該至少一第二間隙層，用以連接所堆疊的該些第一基板的該至少一第一重佈線層和所堆疊的該些第二基板的該至少一第二重佈線層，其中該些第一重佈線層、該些第二重佈線層以及該些微凸塊結構形成多個阻抗元件，並且該些阻抗元件提供一特定的振盪頻率。
  2. 如申請專利範圍第1項所述之晶片堆疊結構，其中 配置於該第四基板的該第二表面的該第一重佈線層利用該第一部份微凸塊結構與配置於該第三基板的該第一表面的該第一重佈線層形成該些阻抗元件中的至少一第一阻抗元件。
  3. 如申請專利範圍第2項所述之晶片堆疊結構，其中該些第一阻抗元件之間利用該第四基板的該第二表面的該第一重佈線層上的一導電線路，或者該第三基板的該第一表面的該第一重佈線層上的一導電線路，以串聯或並聯方式連接。
  4. 如申請專利範圍第2項所述之晶片堆疊結構，其中配置於該第四基板的該第一表面的該第一重佈線層利用貫穿該第四基板的至少一導電通孔與配置於該第四基板的該第二表面的該第一重佈線層連接。
  5. 如申請專利範圍第2項所述之晶片堆疊結構，其中該些第二基板包括：一第五基板，利用該第二部份微凸塊結構堆疊在該第四基板上，並且具有彼此對向的第一表面與第二表面，該第五基板的該第二重佈線層配置於該第五基板的該第二表面；以及一第六基板，利用該第二部份微凸塊結構堆疊在該第四基板上，並且具有彼此對向的第一表面與第二表面，該第六基板的該第二重佈線層配置於該第六基板的該第二表面，其中配置於該第五基板的該第二表面的該第二重佈 線層利用該第二部份微凸塊結構與配置於該第四基板的該第一表面的該第一重佈線層形成該些阻抗元件中的至少一第二阻抗元件，以及其中配置於該第六基板的該第二表面的該第二重佈線層利用該第二部份微凸塊結構與配置於該第四基板的該第一表面的該第一重佈線層形成該些阻抗元件中的至少一第三阻抗元件。
  6. 如申請專利範圍第5項所述之晶片堆疊結構，其中該至少一第二阻抗元件利用貫穿該第四基板的至少一導電通孔與該至少一第一阻抗元件以串聯或並聯方式連接。
  7. 如申請專利範圍第5項所述之晶片堆疊結構，其中該至少一第三阻抗元件利用貫穿該第四基板的至少一導電通孔與該至少一第一阻抗元件以串聯或並聯方式連接。
  8. 如申請專利範圍第5項所述之晶片堆疊結構，其中該至少一第二阻抗元件與該至少一第三阻抗元件之間利用貫穿該第四基板的至少一導電通孔，以及該第四基板的該第二表面的該第一重佈線層上的一導電線路或者利用該第一部份微凸塊結構連接該第三基板的該第一表面的該第一重佈線層上的一導電線路，以串聯或並聯方式連接。
  9. 如申請專利範圍第2項所述之晶片堆疊結構，其中該些第二基板包括：一第七基板，利用該第二部份微凸塊結構堆疊在該第四基板上，並且具有彼此對向的第一表面與第二表面，該第七基板的該些第二重佈線層分別配置於該第七基板的該 第一表面與該第二表面；以及一第八基板，利用該第二部份微凸塊結構堆疊在該第四基板上，並且具有彼此對向的第一表面與第二表面，該第八基板的該些第二重佈線層分別配置於該第八基板的該第一表面與該第二表面，其中配置於該第七基板的該第二表面的該第二重佈線層利用該第二部份微凸塊結構與配置於該第四基板的該第一表面的該第一重佈線層形成該些阻抗元件中的至少一第五阻抗元件，以及其中配置於該第八基板的該第二表面的該第二重佈線層利用該第二部份微凸塊結構與配置於該第四基板的該第一表面的該第一重佈線層形成該些阻抗元件中的至少一第六阻抗元件。
  10. 如申請專利範圍第9項所述之晶片堆疊結構，其中該至少一第五阻抗元件利用貫穿該第四基板的至少一導電通孔與該至少一第一阻抗元件以串聯或並聯方式連接。
  11. 如申請專利範圍第9項所述之晶片堆疊結構，其中該至少一第六阻抗元件利用貫穿該第四基板的至少一導電通孔與該至少一第一阻抗元件以串聯或並聯方式連接。
  12. 如申請專利範圍第9項所述之晶片堆疊結構，更包括：多個打線結構，連接該第七基板的該第一表面的該第二重佈線層與該第八基板的該第一表面的該第二重佈線層。
  13. 如申請專利範圍第12項所述之晶片堆疊結構，其中配置於該第七基板的該第一表面的該第二重佈線層利用貫穿該第七基板的至少一導電通孔與配置於該第七基板的該第二表面的該第二重佈線層連接，以及配置於該第八基板的該第一表面的該第二重佈線層利用貫穿該第八基板的至少一導電通孔與配置於該第八基板的該第二表面的該第二重佈線層連接。
  14. 如申請專利範圍第13項所述之晶片堆疊結構，其中該些打線結構、該第七基板與該第八基板的該些第二重佈線層、貫穿該第七基板與該第八基板的該些導電通孔以及連接第七基板、該第八基板與該第四基板的該第二部份微凸塊結構形成該些阻抗元件中的至少一第七阻抗元件。
  15. 如申請專利範圍第14項所述之晶片堆疊結構，其中該第七基板與該第八基板之間更包括高介電係數材料，以提高該至少一第七阻抗元件的電容值。
  16. 如申請專利範圍第13項所述之晶片堆疊結構，其中該些打線結構、該第四基板的該第一表面的該第一重佈線層上的一導電線路、該第七基板與該第八基板的該些第二重佈線層、貫穿該第七基板與該第八基板的該些導電通孔以及連接該第七基板、該第八基板與該第四基板的部份該第二部份微凸塊結構形成該些阻抗元件中的至少一第八阻抗元件。
  17. 如申請專利範圍第16項所述之晶片堆疊結構，其中該第七基板與該第八基板之間更包括高導磁係數材料， 以提高該至少一第八阻抗元件的電感值。
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