201037543 . 六、發明說明： 【發明所屬之技術領域】 本發明係有關積體電路的驗證（verification)，特別 是關於一種可整合於二維電子設計自動化（EDA)工具的 立體積體電路（3D-IC)驗證方法。 【先前技術】 由於現代的電子系統愈趨於複雜，因此經常會使用系 統單晶片（SOC)技術將電子系統的所有電子組件集成一 單晶片。但是，可能因所使用的各種製程技術不易相容， 因此往往無法使用系統單晶片（SOC)技術來建構一電子 系統。 鑑於此’三維或立體積體電路技術就成為另一種建構 電子系統的可行技術，其可將二或多個晶片以水平和垂直 方式集成一積體電路，即使這些晶片間的製程並不相容。 特別是在石夕穿孔（through-silicon via, TSV)技術愈趨 於成熟後’立體積體電路技術變得更為普遍，其可使用矽 穿孔（TSV)技術藉由穿孔（via)以垂直方式而電性連接 晶片。第一 A圖至第一 b圖顯示瑞薩（Renesas)公司所 3 201037543 - 提出的一種矽穿孔（TSV)技術。於第一 A圖中，藉由將 上層晶片的凸塊（bump) 5插入相鄰下層晶片的矽穿孔6 中而堆疊晶片1-4。接下來，以力量擠壓堆疊之晶片1-4, 因而形成第一 B圖所示的結構。第二A圖至第二B圖顯示 另一種矽穿孔（TSV)技術。於圖式中，晶片11-13藉由 石夕穿孔14及微凸塊（micro bump) 15而連接在一起。 值得注意的是，第二B圖中相鄰晶片11-13的矽穿孔14 0 不需如第二A圖、第一 A/B圖所示之互為對準。第三圖之 示意圖例示一連接的立體積體電路。在此例子中，第一（上） 層包含晶片A及B ;第二（中）層包含晶片C、D及E ; 而第三（下）層包含晶片F。這些晶片藉由矽穿孔31及凸 塊3 2而連接在一起’且互不相鄰的晶片（例如晶片B與 晶片F)也可藉由中空孔洞33而直接連接。 © 現代的複雜積體電路需要藉由電子設計自動化（EDA) 工具（例如積體電路佈局編輯器（layout editor)及設計 規則檢查（DRC)、佈局-簡圖檢查（LVS)等各種驗證工 具）來進行設計以及在真正製造前可驗證積體電路的功 能。由於立體積體電路仍是一種新的技術，因此目前尚未 發展有真正的立體電子設計自動化（EDA)工具。傳統（二 維）電子設計自動化（EDA)工具僅能用以驗證同一層的 晶片，但無法驗證不同層晶片間的連接。傳統二維電子設 4 201037543 • 計自動化（EDA)工具之所以無法用以驗證立體積體電路， 主要原因在於無法分辨出所有晶片的電子組成。因此，傳 統二維電子設計自動化（EDA)工具是無法偵測出如第四 圖所例示的♦穿孔31與凸塊32之錯位情形。 鑑於傳統二維電子設計自動化（EDA)工具無法有效 地驗證立體積體電路，或者真正的立體積體電路電子設計 q 自動化（EDA)工具尚未發展出來，因此亟需提出一種立 體積體電路驗證方法’其可整合至傳統二維電子設計自動 化（EDA)工具，也可單獨使用以驗證立體積體電路。 【發明内容】 本發明的目的之一在於提出一種立體積體電路的驗證 方法，其可整合至傳統二維電子設計自動化（EDA)工具’ ❹ 也可單獨使用以驗證立體積體電路。整合之電子設計自動 化（EDA)工具可用以驗證立體積體電路’而不需尋求昂貴 的真正立體積體電路電子設計自動化（EDA)工具。 根據本發明實施例，對於立體積體電路的每一層級， 定義對準標示（alignment mark)、矽穿孔（TSV)及微 凸塊（micro bump)於虛擬層（dummy layer)上。接 5 201037543 * 著，分別驗證每一層級的晶片、對準標示、矽穿孔及微凸 塊。藉由信息流出（stream out)方式以梅取所有層級的 虛擬層，並根據對準標示將所擷取之虛擬層予以整二。接 下來，垂直地驗證整合之虛擬層，並檢查不同層級i矽穿 孔、微凸塊間的連接關係。 【實施方式】 第五圖顯示本發明實施例之（三維）立體積體電路 (3D 1C)驗證方法的流程。在本實施例中立體積體電 路包含二或多個晶片，其分屬於不同層級。這些晶片藉由 夕穿孔（tsv)及凸塊（或微凸塊（micr〇bUmp))而垂 直地連接在一起（有些晶片還可能水平地連接）^石夕穿孔技 術可以使用（但不限定於）第一 A/B圖、第二A/B圖所 示者。 於步驟51中’提供至少一虛擬層（dummy layer) 給立體積體電路的每一層級，並於該虛擬層上定義及繪製 對準標示（alignment mark)。此外，於該至少一虛擬層 上也繪製有石夕穿孔及凸塊。在本實施例中，同一層級的對 準標示及矽穿孔係繪製於同一虛擬層，而同一層級的凸塊 則緣製於另一虛擬層。第六A圖例示一立體積體電路，其 6 201037543 。 ' 第一（上）層包含晶片A及B，而第二（下）層包含晶片 C °這些晶片藉由矽穿孔61及凸塊62而連接在一起。對 準標示63定義於各自層級。第六b圖顯示第六A圖之立 體積體電路的階層式單元視圖， 第六C圖顯示第六A圖之 立體積體電路的扁平單元視圖，第六D圖顯示經對準標示 所對準的堆疊層級。 〇 在提供了對準標示/矽穿孔/凸塊之虚擬層（步驟51) 後’接著於步驟52中，每一層級分別進行積體電路驗證， 例如設計規則檢查（DRC)及佈局-簡圖檢查（LVS)。每 一層級的驗證可以使用傳統（二維）電子設計自動化（EDA) 工具’其細節不在此贅述。 接著，於步驟53，除了虛擬層之外，對於所有層級的 〇 電子組成進行”信息流出（stream out) ”。在本說明書中， 所謂”信息流出（stream out) ”係指將電子設計自動化 (EDA )工具之檔案從（非標準）資料庫格式轉換為標準 資料庫格式（例如Cadence Design Systems擁有的 GDSII或SEMI擁有的OASIS)。經轉換後之（GDSII 或OASIS)檔案為一種一元樓案’其代表佈局信息，例如 幾何形狀及本文標籤（textlabel)，且提供單元及晶片層 級的物理及光罩佈局資料’用以作為晶圓代工廠於製造積 7 201037543 體電路時之甩。於步驟53 方式，因而得以擷取出每 中’藉由信息流出（stream out) 一層的虛概層。 對於每-層所操取得到之虛擬層，於步驟％中將其 整合或予以合併。其中’所有層級虛擬層之整合主要係根 據=準標7F來進行的。第七A圖顯示當虛擬層正確對準時 疊合對準標示，而第七B圖則顯示當虛擬層未正 喊對準時所得合對準標示。 接著’於步驟55中對整合之虛擬層進行驗證，例如 設計規則檢查（Drc)。第 * )乐八A圃顯不每一層級的擷取虛 第\B圖則顯示所有層級的疊合虛擬層。藉由步 驟55的立_體電路之⑪穿孔Μ塊驗證，♦穿孔91和 凸塊92之_錯位即可則貞測得到，如第九圖中⑽和 ❹ 94所示的錯位情形。 於完成了個別層級的水平檢查 孔/凸塊的垂直檢查（步驟55) 7 及整合石夕穿 證還不能稱已經完整，因為Υ ’ 體電路的驗 已經诵坍m 使所有層級的矽穿孔/凸塊 ==述的檢查(例如設計規則檢查(_ = 凸境之間的連接關係仍有可能 了解決此問題，本實施例更於步驟56進 8 201037543 一步進行立體積體電路的矽穿孔/凸塊連接檢查。於步驟 56中，可以針對矽穿孔、凸塊進行連接檢查，也可以僅單 獨針對矽穿孔進行連接檢查。第十A圖顯示步驟56(立體 積體電路的矽穿孔/凸塊連接檢查）的詳細流程圖。第十B 圖例示一進行連接檢查的結構。於步驟560中，擷取立體 積體電路的埠本文（port text)。於該埠本文中，矽穿孔、 凸塊或其他元件被指定一相對應的琿名稱（P〇rt name )。 〇 上述埠名稱（P〇rt name)之指定及埠本文（p〇rt text) 的產生功能通常可由傳統（二維）電子設計自動化（EDA) 工具來提供，因此其細節不在此贅述。於第十B圖的例子 中，第一層具有Al、A2、A3三個埠名稱，第二層具有 B1至B6共六個埠名稱，第三層具有C1至c6共六個埠 名稱。 ❹ 於步驟561中’產生一連接列表檔案（connecti〇n list file)，用以宣告各層級元件（例如矽穿孔、凸塊）之間的 連接關係。在本實施例中，連接列表檔案的格式如第十C 圖所示。於圖式中，第一層虛擬層（DL1)的埠名稱A2 標示為A2@DL1。依照相同的格式原則，第二層虛擬層 (DL2)的埠名稱B5標示為B5@DL2，而第三層虛擬層 (DL3)的埠名稱C4標示為C4@DL3。於第十C圖中， (第一層的）A2應連接至（第二層的）B5，其應再連接 9 201037543 - 至（第三層的）C4。根據本發明實施例的連接列表構案格 式’埠名稱A2、B5和C4的連接可標示為A2@DL1 to B5@DL2 to C4@DL3。第十D圖顯示連接列表標案格式 的另一例子。在這個例子中’第一層虛擬層（Dli )的璋 名稱A3 (亦即’ A3@DL1)藉由中空孔洞99而直接連接 至第三層虛擬層（DL3)的琿名稱C6(亦即，C6@DL3)。 根據本發明實施例的連接列表檔案格式，埠名稱八3和C6 0 的連接可標示為A3@DL1 to C6@DL3。根據上述的連接 列表槽案格式，第十B圖的連接可以宣告如下： A1@DL1 to B2@DL2 B1@DL2 to C1@DL3 B3@DL2 to C2@DL3 B4@DL2 to C3@DL3 A2@DL1 to B5@DL2 to C4@DL3 0 B6@DL2 to C5@DL3 A3@DL1 to C6@DL3 接下來’於步驟562中，將步驟560所擁取的立體積 體電路的埠本文和步驟561所產生的連接列表檔案予以比 較，以進行連接之追蹤，因而得以檢查連接的正確性。這 個步驟之執行可以使用程式（programming)方式，例如 使用工具命令語言（Tool Command Language，TCL)。 201037543 。 - 根據步驟562的比較結果，如果發現有錯誤的矽穿孔/凸 塊連接，則可以藉由步驟563報導錯誤的連接。 根據上述的實施例，立體積體電路的驗證方法可整合 至傳統二維電子設計自動化（EDA)工具，也可單獨使用 以驗證立體積體電路是否符合功能及製造方面的要求。本 實施例所提供的立體積體電路驗證方法，其成本遠較真正 0 立體積體電路電子設計自動化（EDA)工具之成本來得低， 況且該真正的立體積體電路電子設計自動化（EDA)工具 目前尚未發展出來。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專 Q 利範圍内。 【圖式簡單說明】 第一 A圖至第一 B圖顯示一種矽穿孔（TSV)技術。 第二A圖至第二B圖顯示另一種矽穿孔（TSV)技術。 第三圖之示意圖例示一連接的立體積體電路。 第四圖例示一傳統立體積體電路，其矽穿孔與凸塊有錯位 11 201037543 之情形。 第五圖顯示本發明實施例之（三維）立體積體電路（3D-IC) 驗證方法的流程。 第六A圖例示一立體積體電路。 第六B圖顯示第六A圖之立體積體電路的階層式單元視 圖。 第六C圖顯示第六A圖之立體積體電路的扁平單元視圖。 0 第六D圖顯示經對準標示所對準的堆疊層級。 第七A圖顯示當虚擬層正確對準時所得到的疊合對準標 示。 第七B圖顯示當虛擬層未正確對準時所得到的疊合對準標 示。 第八A圖顯示每一層級的擷取虛擬層。 第八B圖顯示所有層級的疊合虛擬層。 Q 第九圖例示石夕穿孔和凸塊之錯位情形。 第十A圖顯示立體積體電路的矽穿孔/凸塊連接檢查的詳 細流程圖。 第十B圖例示一進行連接檢查的結構。 第十C圖顯示連接列表檔案格式的一個例子。 第十D圖顯示連接列表檔案格式的另一例子。 【主要元件符號說明】 12 201037543 I- 4 晶片 5 凸塊 6 矽穿孔 II- 13 晶片 14 矽穿孔 15 微凸塊 31 矽穿孔201037543 . VI. Description of the Invention: [Technical Field] The present invention relates to verification of integrated circuits, and more particularly to a vertical volume circuit (3D) that can be integrated into a two-dimensional electronic design automation (EDA) tool -IC) verification method. [Prior Art] As modern electronic systems become more complex, system single-chip (SOC) technology is often used to integrate all electronic components of an electronic system into a single wafer. However, it may not be compatible with the various process technologies used, so it is often impossible to construct an electronic system using system single-chip (SOC) technology. In view of this 'three-dimensional or vertical volume circuit technology is another feasible technology for constructing electronic systems, which can integrate two or more wafers into one integrated circuit in a horizontal and vertical manner, even if the process between these wafers is not compatible. . Especially in the case that the through-silicon via (TSV) technology is becoming more and more mature, the vertical volume circuit technology becomes more common, and it can be used in a vertical manner by using through-via (TSV) technology by vias. And electrically connected to the wafer. The first A to the first b shows a twisted perforation (TSV) technique proposed by Renesas Corporation 3 201037543. In the first A diagram, the wafers 1-4 are stacked by inserting the bumps 5 of the upper wafer into the turns 8 of the adjacent lower wafer. Next, the stacked wafers 1-4 are pressed with force, thereby forming the structure shown in Fig. B. Figures 2A through 2B show another technique for boring perforation (TSV). In the drawings, the wafers 11-13 are joined together by a stone-like via 14 and a micro bump 15. It should be noted that the pupil vias 14 0 of the adjacent wafers 11-13 in the second B diagram need not be aligned with each other as shown in the second A diagram and the first A/B diagram. The schematic of the third figure illustrates a connected vertical volume circuit. In this example, the first (upper) layer comprises wafers A and B; the second (middle) layer comprises wafers C, D and E; and the third (lower) layer comprises wafer F. The wafers are joined together by the turns 31 and the bumps 32. The wafers (e.g., the wafer B and the wafer F) which are not adjacent to each other can also be directly connected by the hollow holes 33. © Modern complex integrated circuits require electronic design automation (EDA) tools (such as integrated circuit layout editors and design rule checking (DRC), layout-drawing check (LVS) and other verification tools) Design and verify the functionality of the integrated circuit before it is actually manufactured. Since the vertical volume circuit is still a new technology, there is currently no real three-dimensional electronic design automation (EDA) tool. Traditional (two-dimensional) electronic design automation (EDA) tools can only be used to verify wafers in the same layer, but cannot verify connections between different layers of wafers. Traditional two-dimensional electronic design 4 201037543 • The reason why the automatic (EDA) tool can not be used to verify the vertical volume circuit is that the electronic composition of all the wafers cannot be distinguished. Therefore, the conventional two-dimensional electronic design automation (EDA) tool cannot detect the misalignment of the punch 31 and the bump 32 as illustrated in the fourth figure. In view of the fact that traditional two-dimensional electronic design automation (EDA) tools cannot effectively verify the vertical volume circuit, or the true volumetric circuit electronic design (QA) tool has not been developed, it is urgent to propose a vertical volume circuit verification method. 'It can be integrated into traditional two-dimensional electronic design automation (EDA) tools, or it can be used alone to verify the vertical volume circuit. SUMMARY OF THE INVENTION One object of the present invention is to provide a verification method for a vertical volume circuit that can be integrated into a conventional two-dimensional electronic design automation (EDA) tool ❹ ❹ can also be used alone to verify a vertical volume circuit. Integrated electronic design automation (EDA) tools can be used to verify vertical volume circuits without the need for expensive, true volumetric circuit electronic design automation (EDA) tools. In accordance with an embodiment of the invention, alignment marks, TSVs, and micro bumps are defined on the dummy layer for each level of the volumetric circuit. Connect 5 201037543 * to verify each level of wafers, alignment marks, boring perforations and micro-bumps. The virtual layer of all levels is taken by means of stream out, and the captured virtual layer is rounded up according to the alignment mark. Next, the integrated virtual layer is verified vertically, and the connections between the different levels of the through holes and the microbumps are checked. [Embodiment] The fifth figure shows the flow of the (3D) vertical volume circuit (3D 1C) verification method of the embodiment of the present invention. In the present embodiment, the neutral volume circuit contains two or more wafers, which belong to different levels. These wafers are vertically connected together by swarf (tsv) and bumps (or micro-bumps (or micr〇bUmp)) (some wafers may also be connected horizontally) ^Shi Xi piercing technology can be used (but not limited to ) The first A/B diagram and the second A/B diagram. In step 51, at least one dummy layer is provided to each level of the vertical volume circuit, and an alignment mark is defined and drawn on the virtual layer. In addition, a stone-shaped perforation and a bump are also drawn on the at least one virtual layer. In this embodiment, the alignment marks and the puncturing marks of the same level are drawn in the same virtual layer, and the bumps of the same level are formed in another virtual layer. Figure 6A illustrates a vertical volume circuit, 6 201037543. The first (upper) layer contains wafers A and B, and the second (lower) layer contains wafers C. These wafers are joined together by meandering vias 61 and bumps 62. The alignment mark 63 is defined at the respective levels. Figure 6b shows a hierarchical unit view of the volumetric circuit of Figure 6A, and Figure 6C shows a flat view of the vertical volume circuit of Figure 6A, and the sixth D shows the aligned indication Quasi-level stacking.提供After providing the virtual layer of alignment mark/矽perforation/bump (step 51)', then in step 52, each level is separately verified by integrated circuits, such as design rule check (DRC) and layout-simplification Check (LVS). Verification of each level can use traditional (two-dimensional) electronic design automation (EDA) tools' details are not described here. Next, in step 53, in addition to the virtual layer, "stream out" is performed for the 〇 electronic composition of all levels. In this specification, the term "stream out" refers to the conversion of an electronic design automation (EDA) tool file from a (non-standard) database format to a standard database format (eg, GDSII or SEMI owned by Cadence Design Systems). Owned OASIS). The converted (GDSII or OASIS) file is a one-dimensional case 'which represents layout information, such as geometry and text labels, and provides physical and reticle layout data for the cell and wafer level' as a wafer The foundry was in the process of manufacturing the 7 201037543 body circuit. In the manner of step 53, it is thus possible to extract the virtual layer of each layer by streaming out one layer. For the virtual layer obtained by each layer, it is integrated or merged in step %. The integration of all the hierarchical virtual layers is mainly based on the = standard 7F. Figure 7A shows the overlay alignment marks when the virtual layers are properly aligned, while the seventh B map shows the resulting alignment marks when the virtual layers are not being aligned. The integrated virtual layer is then verified in step 55, such as a design rule check (Drc). The first *) Le 8 A圃 does not show the imaginary virtual level of each level. The \B diagram shows the superimposed virtual layers of all levels. By the step 11 of the vertical _ body circuit of step 55, the _ misalignment of the puncturing 91 and the bump 92 can be guessed, as shown in the ninth figure (10) and ❹ 94. After completing the vertical inspection of the horizontal inspection holes/bumps at the individual levels (step 55) 7 and the integration of the Shi Xi Chuan card can not be said to be complete, because the inspection of the Υ 'body circuit has been 诵坍m to make all levels of 矽 perforation / The check of the bump == (for example, the design rule check (_ = the connection relationship between the convexes is still possible to solve this problem, this embodiment is more than step 56 into 8 201037543 one step to make the hole punching of the vertical volume circuit / Bump connection inspection. In step 56, the connection inspection may be performed for the perforation, the bump, or the connection inspection may be performed only for the perforation. The tenth A shows the step 56 (the perforation/bump of the vertical volume circuit) Detailed flowchart of the connection check. The tenth B diagram illustrates a structure for performing a connection check. In step 560, a port text of a vertical volume circuit is taken. In this document, a perforation, a bump or The other components are assigned a corresponding 珲 name (P〇rt name ). 指定 The above 埠 埠 name (P〇rt name) designation and 埠 (p〇rt text) generation function can usually be designed by traditional (two-dimensional) electronic The elaboration (EDA) tool is provided, so the details are not described here. In the example of the tenth B, the first layer has three 埠 names of Al, A2, and A3, and the second layer has six BB1 to B6. Name, the third layer has a total of six names from C1 to c6. ' In step 561, 'create a connection list file (connecti〇n list file) to declare between each level of components (such as 矽 perforation, bumps) In the present embodiment, the format of the connection list file is as shown in the tenth C. In the figure, the 埠 name A2 of the first layer virtual layer (DL1) is denoted as A2@DL1. According to the same format In principle, the 埠 name B5 of the second layer virtual layer (DL2) is denoted as B5@DL2, and the 埠 name C4 of the third layer virtual layer (DL3) is denoted as C4@DL3. In the tenth C picture, (the first layer A2 should be connected to B5 (of the second layer), which should be reconnected 9 201037543 - to C3 (of the third layer). The connection list structure format ''names A2, B5 and C4 according to an embodiment of the invention The connection can be labeled as A2@DL1 to B5@DL2 to C4@DL3. The tenth D diagram shows another example of the connection list format. In the example, the first layer virtual layer (Dli) has the name A3 (ie, 'A3@DL1) connected directly to the third layer virtual layer (DL3) by the hollow hole 99 (ie, C6@). DL3) According to the connection list file format of the embodiment of the present invention, the connection of the names 八3 and C6 0 may be denoted as A3@DL1 to C6@DL3. According to the connection list slot format described above, the connection of the tenth B diagram may be The announcement is as follows: A1@DL1 to B2@DL2 B1@DL2 to C1@DL3 B3@DL2 to C2@DL3 B4@DL2 to C3@DL3 A2@DL1 to B5@DL2 to C4@DL3 0 B6@DL2 to C5@DL3 A3@DL1 to C6@DL3 Next, in step 562, the connection list file generated by the volumetric circuit of step 560 and the connection list file generated by step 561 are compared to perform connection tracking, thereby being inspected. The correctness of the connection. This step can be performed using a programming method, such as using the Tool Command Language (TCL). 201037543. - According to the comparison result of step 562, if an erroneous puncturing/bump connection is found, the erroneous connection can be reported by step 563. According to the above embodiment, the verification method of the vertical volume circuit can be integrated into a conventional two-dimensional electronic design automation (EDA) tool, or can be used alone to verify whether the vertical volume circuit meets the functional and manufacturing requirements. The cost of the vertical volume circuit verification method provided by this embodiment is much lower than the cost of the true zero volume circuit electronic design automation (EDA) tool, and the true vertical volume circuit electronic design automation (EDA) tool It has not yet been developed. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Apply for a special Q range. [Simple diagram of the diagram] The first A to the first B diagrams show a technique of sputum perforation (TSV). Figures 2A through 2B show another technique for boring perforation (TSV). The schematic of the third diagram illustrates a connected vertical volume circuit. The fourth figure illustrates a conventional vertical volume circuit in which the turns and the bumps are misaligned 11 201037543. The fifth figure shows the flow of the (three-dimensional) vertical volume circuit (3D-IC) verification method of the embodiment of the present invention. Figure 6A illustrates a vertical volume circuit. Figure 6B shows a hierarchical unit view of the volumetric circuit of Figure 6A. Figure 6C shows a flat cell view of the volumetric circuit of Figure 6A. 0 The sixth D graph shows the stacking levels aligned by the alignment marks. Figure 7A shows the overlay alignment marks obtained when the virtual layers are properly aligned. Figure 7B shows the resulting overlay alignment when the virtual layers are not properly aligned. Figure 8A shows the captured virtual layer for each level. Figure 8B shows the superimposed virtual layers of all levels. Q The ninth figure illustrates the misalignment of the stone-shaped piercing and the bump. Figure 10A shows a detailed flow chart of the 矽 perforation/bump connection check of the vertical volume circuit. The tenth B diagram illustrates a structure for performing connection check. The tenth C chart shows an example of the connection list file format. The tenth D diagram shows another example of the connection list file format. [Main component symbol description] 12 201037543 I- 4 Wafer 5 Bump 6 矽 Perforation II- 13 Wafer 14 矽 Perforation 15 Microbump 31 矽 Perforation
32 凸塊 33 中空孔洞 51-56 實施例之流程步驟 560-563 連接檢查之流程步驟 61 矽穿孔 62 凸塊 63 對準標示 91 矽穿孔 92 凸塊 93 錯位 94 錯位 99 中空孔洞 1332 Bumps 33 Hollow Holes 51-56 Process Steps for the Example 560-563 Procedures for Connection Inspection 61 矽Perforation 62 Bumps 63 Alignment Marks 91 矽Perforations 92 Bumps 93 Misalignment 94 Dislocations 99 Hollow Holes 13