CN103890931B - 半导体装置及半导体模块 - Google Patents
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Abstract
模拟集成电路(12)及数字集成电路(14)形成在基板(22)的主面上。模拟接地端子(T2)设置在模拟集成电路(12)上,数字接地端子(T6)及(T7)设置在数字集成电路(14)上。模拟接地层(28)以与模拟集成电路(12)相对的方式层叠在基板(22)上,数字接地层(30)及(34)以与数字集成电路(14)相对的方式层叠在基板(22)上。模拟接地端子(T2)与模拟接地层(28)相连接,数字接地端子(T6)及(T7)分别与数字接地层(30)及(34)相连接。
Description
技术领域
本发明涉及半导体装置,尤其涉及安装有模拟集成电路及数字集成电路的半导体装置。
本发明还涉及半导体模块,尤其涉及表面安装或内置有具有模拟集成电路及数字集成电路的半导体装置的半导体模块。
背景技术
专利文献1中揭示了这种装置的一个示例。根据其背景技术,电路元件形成区域分配在硅基板的上表面的中央部,在其外侧设有信号用的多个连接焊盘以及接地用的单一的连接焊盘。从信号用的连接焊盘的上表面起到绝缘膜的上表面设有信号用的再布线,在位于再布线的前端的焊盘部的上表面设有突起电极。此外,接地层以避开信号用的再布线及其附近的方式设置在电路元件形成区域上的绝缘膜的上表面,并经由接地用的再布线与接地用的连接焊盘相连接。在接地层的上表面的规定部位设有其它突起电极。
现有技术文献
专利文献
专利文献1:日本专利特开2001-156209号公报
发明内容
发明所要解决的技术问题
然而,在电路元件形成区域中形成模拟集成电路及数字集成电路这样的多个集成电路的情况下,存在某一集成电路所产生的噪声经由接地层对其它集成电路产生影响的可能性。尤其是,存在数字集成电路所产生的高频噪声使模拟集成电路的动作变得不稳定的可能性。
因此,本发明的主要目的在于提供一种能抑制数字集成电路产生的噪声对模拟集成电路产生的影响的、半导体装置或半导体模块。
解决技术问题所采用的技术方案
本发明所涉及的半导体装置(10:相当于实施例中的参照标号,以下相同)包括:半导体基板(22),该半导体基板(22)具有分配了第1区域及第2区域的主面;模拟集成电路(12),该模拟集成电路(12)与第1区域相对应地设置在主面上;数字集成电路(14),该数字集成电路(14)与第2区域相对应地设置在主面上;以及接地层(28~30、34),该接地层(28~30、34)与第1区域及第2区域相对,在所述半导体装置(10)中,在模拟集成电路及数字集成电路上分别设有模拟接地端子(T2)及数字接地端子(T6、T7),接地层分割为与第1区域相对的模拟接地层(28)和与第2区域相对的数字接地层(30、34),模拟接地端子及数字接地端子分别与模拟接地层及数字接地层相连接,数字接地端子被分割成多个接地端子,数字接地层被分割成分别与多个接地端子相连的多个小接地层,模拟集成电路包含承担模拟和数字之间的转换处理中的模拟一侧的处理的模拟一侧转换电路(18a)的至少一部分,数字集成电路包含承担模拟和数字之间的转换处理中的数字一侧的处理的数字一侧转换电路(18d)的至少一部分,而且,模拟接地端子与模拟一侧转换电路相连,多个接地端子的其中一个与数字一侧转换电路相连接。
优选为数字集成电路还包含多个数字电路(201~203)、以及分别与多个数字电路相连接的多个电源端子(T3~T5)。
在某一方面,数字一侧转换电路(18d)与多个电源端子中的任一个相连接。
在另一方面,还包括与第2区域相对的浮置层(32),多个接地端子中的至少一个也与浮置层相连接。
在其它方面,还包括:绝缘层(42),该绝缘层(42)形成在多个电源端子及接地层的上面;第1通孔(H1),该第1通孔(H1)与多个电源端子各自的位置相对应地形成在绝缘层上;第2通孔(H2),该第2通孔(H2)与数字接地层的位置相对应地形成在绝缘层上;电源电极构件(PE1),该电源电极构件(PE1)经由第1通孔分别与多个电源端子相连接;以及接地电极构件(GE1),该接地电极构件(GE1)经由第2通孔与数字接地层相连接。优选为电源电极构件以绝缘层为基准,配置在比接地电极构件更远的位置上。
优选为在模拟接地层及数字接地层上分别形成有1个或2个以上的开口。
本发明所涉及的半导体模块(10)表面安装或内置有半导体封装(LB3),该半导体封装(LB3)包括:半导体基板(22),该半导体基板(22)具有分配了第1区域及第2区域的主面;模拟集成电路(12),该模拟集成电路(12)与第1区域相对应地设置在主面上;数字集成电路(14),该数字集成电路(14)与第2区域相对应地设置在主面上;以及接地层(28~30、34),该接地层(28~30、34)与第1区域及第2区域相对,在所述半导体封装中,在模拟集成电路及数字集成电路上分别设有模拟接地端子(T2)及数字接地端子(T6、T7),接地层分割为与第1区域相对的模拟接地层(28)和与第2区域相对的数字接地层(30、34),而且,模拟接地端子及数字接地端子分别与模拟接地层及数字接地层相连接,数字接地端子被分割成多个接地端子,并且数字接地层被分割成分别与多个接地端子相连的多个小接地层。
优选为还包括:电源电极构件(PE1),该电源电极构件(PE1)与数字集成电路相连接;以及接地电极构件(GE1),该接地电极构件(GE1)配置在数字集成电路与电源电极构件之间,并与数字接地层相连接。
发明效果
根据本发明,接地层分割为与模拟集成电路用的第1区域相对的模拟接地层、以及覆盖数字集成电路用的第2区域的数字接地层。由此,能抑制从数字集成电路产生的噪声经由接地层对模拟集成电路产生影响的现象。
本发明的上述目的、其它的目的、特征及优点通过参照附图进行的以下的实施例的详细的说明能更加清楚。
附图说明
图1是表示本实施例的半导体装置的一个示例的框图。
图2是表示适用于图1所示的半导体装置的转换器的结构的一个示例的框图。
图3是表示适用于图1所示的半导体装置的数字信号处理电路的结构的一个示例的框图。
图4(A)是表示形成在基板上的功能面的一个示例的图解图,图4(B)是图4(A)所示的层叠体的A-A剖视图。
图5(A)是表示层叠在图4所示的层叠体上的绝缘层及再布线层的一个示例的图解图,图5(B)是图5(A)所示的层叠体的A-A剖视图。
图6(A)是表示层叠在图5所示的层叠体上的另一绝缘层及柱形电极的一个示例的图解图,图6(B)是图6(A)所示的层叠体的A-A剖视图。
图7是对图6所示的层叠体进行密封而制成的半导体装置的剖视图。
图8是对图6所示的层叠体进行密封而制成的另一半导体装置的剖视图。
具体实施方式
参照图1,本实施例的半导体装置10包含模拟集成电路12及数字集成电路14。模拟集成电路12中设有模拟信号处理电路16和转换器18的一部分,在数字集成电路14中设有转换器18的另一部分和数字信号处理电路20。
经过模拟信号处理电路12进行了处理的模拟信号通过转换器18转换为数字信号,转换后的数字信号提供给数字信号处理电路20。此外,经过数字信号处理电路20进行了处理的数字信号通过转换器18转换为模拟信号,转换后的模拟信号提供给模拟信号处理电路16。
在模拟集成电路12中设有模拟电源端子T1及模拟接地端子T2。模拟电源端子T1及模拟接地端子T2均与模拟信号处理电路16及转换器18双方相连接。模拟电源电压A_Vcc经由模拟电源端子T1提供给模拟信号处理电路16及转换器18。此外,模拟接地端子T2接地。
在数字集成电路20中设有数字电源端子T3~T5和数字接地端子T6~T7。数字电源端子T3与转换器18及数字信号处理电路20双方相连接,数字电源端子T4及T5仅与数字信号处理电路20相连接。数字接地端子T6仅与转换器18相连接,数字接地端子T7仅与数字信号处理电路20相连接。
数字电源电压D_Vcc经由数字电源端子T3~T5提供给转换器18及数字信号处理电路20。此外,数字接地端子T6及T7接地。
另外,将数字电源电压D_Vcc的输入端分散到数字电源端子T3~T5,且将与基准电位面进行连接的连接端分散到数字接地端子T6~T7,这是为了提高下文所述的再布线层的设计自由度。
模拟信号处理电路16基于模拟电源电压A_Vcc执行模拟信号处理,数 字信号处理电路20基于数字电源电压D_Vcc执行数字信号处理。此外,转换器18基于模拟电源电压A_Vcc执行模拟一侧的转换处理,并基于数字电源电压D_Vcc执行数字一侧的转换处理。
参照图2,转换器18通过A/D转换电路181及D/A转换电路182而得以形成。从模拟信号处理电路16输出的模拟信号通过A/D转换器181转换为数字信号,从数字信号处理电路20输出的数字信号通过D/A转换器182转换为模拟信号。经A/D转换器181转换后的数字信号提供给数字信号处理电路20,经D/A转换器182转换后的模拟信号提供给模拟信号处理电路16。
此处,A/D转换电路181及D/A转换电路182中,承担模拟一侧的转换处理的电路的至少一部分属于模拟一侧转换电路18a,承担数字一侧的转换处理的电路的至少一部分属于数字一侧转换电路18d。模拟电源端子T1及模拟接地端子T2与模拟一侧转换电路18a相连接,数字电源端子T3及数字接地端子T6与数字一侧转换电路18d相连接。
参照图3,数字信号处理电路20包含控制电路201、I/F电路202及存储电路203。数字电源端子T3与控制电路201相连接,数字电源端子T4与I/F电路202相连接,而且,数字电源端子T5与存储电路203相连接。此外,数字接地端子T7与控制电路201、I/F电路202及存储电路203公共连接。
图1所示的半导体装置10通过对经由图4(A)及图4(B)~图6(A)~图6(B)的制造工艺制成的半导体封装(=层叠体LB3)按照图7所示的要点进行密封而得以完成。此处,作为半导体封装的制造工艺,采用WL-CSP(Wafer LevelChip Size Package:晶圆级芯片尺寸封装)工艺,到形成再布线层为止以晶圆级进行,但为了便于说明,设想为从刚开始就已经是芯片化的状态。
首先,参照图4(A)及图4(B),模拟集成电路12形成在半导体基板22的上表面的某一区域(=在图4中用斜线表示的矩形区域),数字集成电路14形成 在半导体基板22的上表面的另一区域(=在图4中用网格表示的L字形区域)。此外,在半导体基板22的上表面的周边部形成有多个焊盘电极24、24、…。这些焊盘电极24、24、…的一部分与模拟集成电路12相连接,这些焊盘电极24、24、…的另一部分与数字集成电路14相连接。由此,能获得上表面相当于功能面的层叠体LB1。
另外,与模拟集成电路12相连接的焊盘电极24、24、…的一部分相当于模拟电源端子T1及模拟接地端子T2。此外,与数字集成电路14相连接的焊盘电极24、24、…的一部分相当于数字电源端子T3~T5及数字接地端子T6~T7。
参照图5(A)及图5(B),层叠体LB1的上表面中除焊盘电极24、24、…以外的区域被绝缘层26覆盖。此外,在绝缘层26上层叠有再布线层。再布线层由单一的模拟接地层28、三个数字接地层30~34、多个焊盘电极层36、36、…、多个柱状电极层38、38、…、及多个走线布线40、40、…所形成。而且,在模拟接地层28中形成有分别呈圆形的两个开口,在数字接地层30中也形成有分别呈圆形的三个开口。另外,这些开口是为了调节模拟接地层28及数字接地层30中的残铜率(接地层的坯料均优选为铜等导电性较高的材料)而设置的。
此处,模拟接地层28形成在与模拟集成电路12相对的位置上,数字接地层30~34形成在与数字集成电路14相对的位置上。此外,焊盘电极层36形成在焊盘电极24上,柱状电极层38形成在配置下文所述的柱状电极44的位置上。而且,走线布线40是为了将焊盘电极层24与模拟接地层28、数字接地层30、数字接地层34、柱状电极层38、或其它焊盘电极层24进行连接而形成的。数字接地层32未与任何焊盘电极层24相连接而成为浮置层。由此,能获得在上表面形成有绝缘层26及再布线层的层叠体LB2。
另外,相当于模拟电源端子T1的焊盘电极24经由焊盘电极层36及走线 布线40与柱状电极层38相连接,相当于模拟接地端子T2的焊盘电极24经由焊盘电极层36及走线布线40与模拟接地层28相连接。
此外,相当于各数字电源端子T3~T5的焊盘电极24经由焊盘电极层36及走线布线40与柱状电极层38相连接,相当于数字接地端子T6的焊盘电极24经由焊盘电极层36及走线布线40与数字接地层30相连接,相当于数字接地端子T7的焊盘电极24经由焊盘电极层36及走线布线40与数字接地层34相连接。
另外,也可以将相当于数字接地端子T6的焊盘电极24以及相当于数字接地端子T7的焊盘电极24中的至少一个进一步与数字接地层32进行连接。
将数字电源端子T3~T5隔开距离地进行分配,且将与数字集成电路14相对的接地层分割为三个数字接地层30~34,从而使提供数字电源电压D_Vcc的布线避开数字一侧转换电路18d的附近,确保走线自由度。通过这样的走线的自由度和处于浮置状态的数字接地层32的屏蔽功能,能减少在数字一侧转换电路18d产生的噪声与数字电源电压D_Vcc叠加的现象。
即,若数字集成电路14产生的噪声与数字接地层30~34同时和数字电源电压D_Vcc叠加,则该噪声以相同的相位与数字信号线和数字接地电极叠加而成为共模噪声,无法利用形成在信号线与接地之间的电容器等来除去噪声,因此,会与数字一侧转换电路18d叠加。此外,由于数字接地层30~34是利用薄膜工艺制成的电极厚度较薄(例如厚度为1μm~5μm)的接地电极,因此,无法将接地的电位保持为恒定,在该接地层中无法消除噪声,噪声会传输到模拟一侧转换电路18a。该噪声有时会由共模噪声转换为常模噪声,因此,共模噪声和常模噪声会与由模拟集成电路16进行信号处理的微弱的信号叠加而产生寄生噪声,从而在无线通信中成为重要问题的数据包错误率增大,通信速度和通信质量变差。另一方面,如本实施例那样,通过将提供数字电源电压D_Vcc的布线以避开数字一侧转换电路18d的附 近的方式进行走线,能降低与数字电源电压D_Vcc叠加的噪声,由此使模拟一侧转换电路18a的动作稳定,减小数据包错误率,提高通信质量。另外,此处,作为传输到模拟一侧转换电路18a的噪声,对在数字集成电路14产生的噪声成为共模噪声传输到模拟一侧转换电路18a的示例进行了说明,但作为噪声的传输模式,存在共模噪声变为常模噪声进行传输等各种各样的模式。
参照图6(A)及图6(B),层叠体LB2的上表面被具有多个通孔46、46、…的绝缘层42所覆盖。柱状电极层38、38、…从多个通孔46、46、…的一部分露出,模拟接地层28、数字接地层30~34各自的一部分从多个通孔46、46、…的另一部分露出。多个柱状电极44、44、…分别埋入这些通孔46、46、…中。
因此,某一柱状电极44经由柱状电极层38与模拟电源端子T1相连接,其它柱状电极44经由模拟接地层28与模拟接地端子T2相连接。此外,某一柱状电极44经由柱状电极层38与数字电源端子T3、T4或T5相连接,另一柱状电极经由数字接地层30与数字接地端子T6相连接,其它柱状电极经由数字接地层34与数字接地端子T7相连接。由此,能获得在上表面形成有绝缘层46及多个柱状电极44、44、…的层叠体LB3。
此处,将与模拟电源端子T1相连接的柱状电极44特别定义为“柱状电极E1”,将与模拟接地端子T2相连接的柱状电极44特别定义为“柱状电极E2”。
此外,将与数字电源端子T3相连接的柱状电极44特别定义为“柱状电极E3”,将与数字电源端子T4相连接的柱状电极44特别定义为“柱状电极E4”,将与数字电源端子T5相连接的柱状电极44特别定义为“柱状电极E5”。而且,将与数字接地端子T6相连接的柱状电极44特别定义为“柱状电极E6”,将与数字接地端子T7相连接的柱状电极44特别定义为“柱状电极E7”。
而且,将分别埋入有柱状电极E3~E5的各个通孔46、46及46特别定义为“通孔H1”,将分别埋入有柱状电极E6及E7的各个通孔46及46特别定义为“通孔H2”。
参照图7,利用树脂60对层叠体LB3即半导体封装和布线导体50~56一起进行密封。其中,在树脂60中形成有多个通孔48、48、…。另外,出于能在半导体封装内容易地进行布线,树脂60的材质优选为液晶聚合物或聚酰亚胺等能进行片材层叠的柔性树脂。此外,半导体封装也可以安装在树脂60的表面。
数字电源电压D_Vcc经由通孔48、布线导体54及50提供给柱状电极E3,并经由通孔48、布线导体54及52提供给柱状电极E5。数字电源电路D_Vcc还经由通孔48、布线导体56及未图示的布线导体提供给柱状电极E4(参照图6)。
此外,与柱状电极E6~E7及数字接地电极32(参照图5)相连接的柱状电极44经由通孔48及布线导体56彼此进行连接。因此,能将布线导体54定义为“数字电源电极PE1”,能将布线导体56定义为“数字接地电极GE1”。
此处,从层叠体LB3的上表面到数字电源电极PE1为止的距离比从层叠体LB3的上表面到数字接地电极GE1为止的距离要长,数字接地电极GE1夹设在数字电源电极PE1与数字集成电路24之间。形成转换器18的数字一侧转换电路18d产生的噪声也被数字接地电极GE1屏蔽,能降低或消除与数字电源电压D_Vcc叠加的噪声。由此,能防止在数字集成电路14产生的噪声成为与数字接地层30~34和数字电源同相叠加的共模噪声,能仅靠数字接地层30~34来屏蔽噪声。
从以上的说明可见,半导体基板22具有分配了矩形区域及L字形区域的
主面。模拟集成电路12与矩形区域相对应地设置在半导体基板22的主面上,数字集成电路14与L字形区域相对应地设置在半导体基板22的主面上。模拟接地端子T2设置在模拟集成电路12上,数字接地端子T6及T7设置在数字集成电路14上。模拟接地层28以与模拟集成电路12相对的方式层叠在半导体基板22上,数字接地层30及34以与数字集成电路14相对的方式层叠在半导体基板22上。模拟接地端子T2与模拟接地层28相连接,数字接地端子T6及T7分别与数字接地层30及34相连接。
通过将模拟接地层28及数字接地层30、34如上所述地进行配置,能抑制从数字集成电路14产生的噪声对模拟集成电路12产生影响的现象。此外,通过确保再布线层中的走线布线40的走线的自由度,并配置浮置状态的数字接地层32,而且在半导体封装的外部,在比数字接地电极GE1更远的位置形成数字电源电极PE1,能抑制在数字一侧转换电路18d产生的噪声与数字电源电压D_Vcc叠加的现象,进而使模拟一侧转换电路18a的动作稳定。
另外,本实施例的半导体装置10具有图7所示的截面结构。然而,也可以按照图8所示的要点对半导体封装即层叠体LB3进行密封来制作另一半导体装置10。即使是图8的半导体装置10,也能利用树脂60将层叠体LB3和多个布线导体52、52、…一起进行密封,并在树脂60中形成多个通孔48、48、…。其中,布线导体52、52、…的一部分在树脂60的上表面及下表面露出,在树脂60的上表面安装有半导体元件62、64及66。由此,能获得能执行更为复杂的处理的半导体装置10。
此外,本发明的半导体装置并不限于由半导体模块构成的结构,例如,也可以是将电路元件安装在印刷基板上的结构。
标号说明
10…半导体装置
12…模拟集成电路
14…数字集成电路
16…模拟信号处理电路
18…转换器
20…数字信号处理电路
28…模拟接地层
30、32、34…数字接地层
Claims (10)
1.一种半导体装置,该半导体装置包括:
半导体基板,该半导体基板具有分配了第1区域及第2区域的主面;
模拟集成电路,该模拟集成电路与所述第1区域相对应地设置在所述主面上;
数字集成电路,该数字集成电路与所述第2区域相对应地设置在所述主面上;以及
接地层,该接地层与所述第1区域及所述第2区域相对,
其特征在于,
模拟接地端子及数字接地端子分别设置在所述模拟集成电路及所述数字集成电路上,
所述接地层分割为与所述第1区域相对的模拟接地层和与所述第2区域相对的数字接地层,
所述模拟接地端子及所述数字接地端子分别与所述模拟接地层及所述数字接地层相连接,
所述数字接地端子被分割成多个接地端子,
所述数字接地层被分割成分别与所述多个接地端子相连的多个小接地层,
所述模拟集成电路包含承担模拟和数字之间的转换处理中的模拟一侧的处理的模拟一侧转换电路的至少一部分,
所述数字集成电路包含承担所述模拟和数字之间的转换处理中的数字一侧的处理的数字一侧转换电路的至少一部分,而且,
所述模拟接地端子与所述模拟一侧转换电路相连,并且,
所述多个接地端子的其中一个与所述数字一侧转换电路相连接。
2.如权利要求1所述的半导体装置,其特征在于,所述数字集成电路还包含多个数字电路、以及分别与所述多个数字电路相连接的多个电源端子。
3.如权利要求2所述的半导体装置,其特征在于,所述数字一侧转换电路与所述多个电源端子中的任意一个相连接。
4.如权利要求2或3所述的半导体装置,其特征在于,还包括与所述第2区域相对的浮置层,
所述多个接地端子中的至少一个也与所述浮置层相连接。
5.如权利要求2所述的半导体装置,其特征在于,还包括:绝缘层,该绝缘层形成在所述多个电源端子及所述接地层的上面;
第1通孔,该第1通孔与所述多个电源端子各自的位置相对应地形成在所述绝缘层中;
第2通孔,该第2通孔与所述数字接地层的位置相对应地形成在所述绝缘层中;
电源电极构件,该电源电极构件经由所述第1通孔分别与所述多个电源端子相连接,以及
接地电极构件,该接地电极构件经由所述第2通孔与所述数字接地层相连接。
6.如权利要求5所述的半导体装置,其特征在于,所述电源电极构件以所述绝缘层为基准,配置在比所述接地电极构件更远的位置上。
7.如权利要求1所述的半导体装置,其特征在于,在所述模拟接地层及所述数字接地层上分别形成有1个或2个以上的开口。
8.一种半导体模块,该半导体模块表面安装或内置有半导体封装,该半导体封装包括:半导体基板,该半导体基板具有分配了第1区域及第2区域的主面;模拟集成电路,该模拟集成电路与所述第1区域相对应地设置在所述主面上;数字集成电路,该数字集成电路与所述第2区域相对应地设置在所述主面上;以及接地层,该接地层与所述第1区域及所述第2区域相对,其特征在于,
在所述半导体封装中,
模拟接地端子及数字接地端子分别设置在所述模拟集成电路及所述数字集成电路上,
所述接地层分割为与所述第1区域相对的模拟接地层和与所述第2区域相对的数字接地层,而且,
所述模拟接地端子及所述数字接地端子分别与所述模拟接地层及所述数字接地层相连接,
所述数字接地端子被分割成多个接地端子,并且,
所述数字接地层被分割成分别与所述多个接地端子相连的多个小接地层。
9.如权利要求8所述的半导体模块,其特征在于,还包括:电源电极构件,该电源电极构件与所述数字集成电路相连接;以及接地电极构件,该接地电极构件配置在所述数字集成电路与所述电源电极构件之间,并与所述数字接地层相连接。
10.一种半导体装置,该半导体装置包括:
半导体基板,该半导体基板具有分配了第1区域及第2区域的主面;
模拟集成电路,该模拟集成电路与所述第1区域相对应地设置在所述主面上;
数字集成电路,该数字集成电路与所述第2区域相对应地设置在所述主面上;以及
接地层,该接地层与所述第1区域及所述第2区域相对,
其特征在于,
模拟接地端子及数字接地端子分别设置在所述模拟集成电路及所述数字集成电路上,
所述接地层分割为与所述第1区域相对的模拟接地层和与所述第2区域相对的数字接地层,
所述模拟接地端子及所述数字接地端子分别与所述模拟接地层及所述数字接地层相连接,
所述数字接地端子被分割成多个接地端子,并且,
所述数字接地层被分割成分别与所述多个接地端子相连接的多个小接地层。
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