CN103872670A

CN103872670A - Electrostatic discharge protection circuit, bias circuit and electronic device

Info

Publication number: CN103872670A
Application number: CN201210578414.3A
Authority: CN
Inventors: 陈哲宏; 杨宗翰
Original assignee: Integrated System Solution Corp
Current assignee: British Cayman Islands Business Miley Electronic Ltd By Share Ltd; Microchip Technology Inc
Priority date: 2012-12-07
Filing date: 2012-12-27
Publication date: 2014-06-18
Anticipated expiration: 2032-12-27
Also published as: TW201424181A; TWI455435B; CN103872670B

Abstract

The invention discloses an electrostatic discharge protection circuit, a bias circuit and an electronic device. The trigger unit has an input end and an output end for triggering the clamping unit. The control unit receives the transformation enabling signal to start the trigger unit, and determines the opening or closing of the current discharge channel in the clamping unit by the transformation enabling signal, wherein when the transformation enabling signal is a low voltage level, the trigger unit can open the current discharge channel of the clamping unit so as to protect the bias circuit from damage caused by instantaneous high voltage generated by static electricity.

Description

ESD protection circuit, bias circuit and electronic installation

Technical field

The present invention has about a kind of ESD protection circuit, and particularly about one in the time that bias circuit cuts out, automatically open the discharge channel of ESD protection circuit so that bias circuit current potential is discharged to rapidly to earthing potential.

Background technology

Generally in integrated circuit (IC) design; the power management of IC interior often can use linear low dropout voltage regulator (Linear Low-dropout Regulator; LDO); for the stability of compensation low dropout pressurizer, can hang up at output the capacity cell of larger capacitance simultaneously.But in integrated circuit circuit, capacity cell quite accounts for area, so major part all can select this building-out capacitor to be placed on the outside of integrated circuit, namely on printed circuit board (PCB).

Therefore, the output voltage terminal of IC interior low dropout voltage regulator, the pin position that must be connected to encapsulation via lead-in wire (bond wire) by pad (Pad) just can with printed circuit board (PCB) on electric capacity establish a connection.Wherein, pad (Pad) must design has static discharge (Electrostatic discharge, ESD) protection, suffers electrostatic breakdown with the low dropout voltage regulator that prevents IC interior.Generally speaking, the design of electrostatic discharge protective must be under normal operation in high-impedance state pattern, but suffering static when bombardment that but the electrostatic discharging path of low resistance can be provided, to avoid electrostatic charge produce the large voltage (as kilovolt grade) of moment and cause damage integrated circuit.

Please refer to Figure 1A, the circuit diagram that Figure 1A is existing bias circuit.As shown in Figure 1A.Existing bias circuit 10 comprises low dropout voltage regulator 12 and ESD protection circuit 14, and wherein ESD protection circuit 14 is coupled to low dropout voltage regulator 12.Low dropout voltage regulator 12 comprises amplifier OP ', P transistor npn npn MP ' and feedback resistance R1 ', R2 '.The building-out capacitor CL ' of chip exterior is through being connected with feedback resistance R1 ' with the drain electrode of P transistor npn npn MP '.Wherein, the negative input end of amplifier OP ' receives a reference voltage VREF ', and the positive input terminal of amplifier OP ' receives feedback voltage V F '.The source electrode of P transistor npn npn MP ' receives input voltage VIN '.

Because ESD protection circuit 14 only can be to suffering static when bombardment to produce action; therefore in the time that low dropout voltage regulator 12 is closed from normal operating conditions; the path that the upper stored electric charge of load capacitance CL only can be connected via feedback resistance R1 ', R2 ' is discharged to ground, and can not flow to ESD protection circuit 14.Generally in order to make low dropout voltage regulator 12 circuit power savings, the resistance value of feedback resistance R1, R2 can design in kilohm (k Ω) grade, makes low dropout voltage regulator 12 can reach lower quiescent dissipation electric current (Quiescent Current).So the time more than electric charge is from the load capacitance CL ' of μ F level via the R1 ' of k Ω level and R2 ' conductive discharge during to ground, may need tens of seconds can be discharged completely.

Therefore, if while wanting low dropout voltage regulator 12 to close from normal operating conditions, output voltage VO UT can repid discharge to ground, conventionally can additionally add a discharge path.

Please refer to Figure 1B, the schematic diagram that Figure 1B is another existing bias circuit.As shown in Figure 1B, different from Figure 1A, the discharge path additionally adding in Figure 1B is made up of resistance R 3 ' (ohm level) and N-type transistor MN '.The grid of N-type transistor MN ' receives a switching signal LDO_enb contrary with the enable signal LDO_en of low dropout voltage regulator.Therefore,, when low dropout voltage regulator 12 normal work, N-type transistor MN ' closes.In the time that low dropout voltage regulator 12 is closed from normal operating conditions, N-type transistor MN ' conducting forms discharge path, and making load capacitance CL ' go up stored electric charge can be via resistance R 3 ' repid discharge to ground.

In Figure 1B; the resistance value of resistance R 3 ' is less; the discharging current of moment is larger; the speed of electric discharge is also faster, but because this pin position is connected directly to outside, is therefore easy to suffer static to bombard; under the design consideration of ESD protection circuit; must increase the resistance of R3 to increase the repellence of static bombardment, but so design not only increases layout area, and reduced again the speed of the charge discharge on load capacitance CL '.

Summary of the invention

The object of the present invention is to provide a kind of ESD protection circuit, described ESD protection circuit comprises strangulation unit, trigger element and control unit.Strangulation unit couples between positive power line and negative power line.Trigger element has input and output, and trigger element couples negative power line and reference voltage, and output is coupled to strangulation unit and in order to trigger strangulation unit.Control unit is coupled to this input of positive power line, negative power line and this trigger element, control unit receives transformation enable signal to trigger trigger element, and determine by this strangulation unit current discharge passage unlatching or close, wherein, in the time that this transformation enable signal is a low voltage level, this trigger element can be opened this current discharge passage of strangulation unit.

The embodiment of the present invention provides a kind of bias circuit, and bias circuit comprises voltage conversion circuit and ESD protection circuit.Voltage conversion circuit is in order to be converted to output voltage by received input voltage, and wherein output voltage is stored in load capacitance.ESD protection circuit is electrically connected to output voltage, and ESD protection circuit receives and decides the unlatching of its inner current discharge passage or close according to transformation enable signal.In the time that transformation enable signal is low voltage level, bias circuit is in closed condition, and ESD protection circuit firing current discharge channel, and discharging current is from load capacitance inflow current discharge channel, so that the electric charge in load capacitance is discharged.

In one of them embodiment of the present invention, control unit comprises controlling resistance and control capacitance.One end of controlling resistance is electrically connected positive power line, and the other end of controlling resistance receives transformation enable signal.One end of control capacitance is electrically connected the other end of controlling resistance, and the other end of control capacitance is electrically connected earthed voltage.

In one of them embodiment of the present invention, trigger element comprises that P type triggers transistor AND gate N-type and triggers transistor.P type triggers the other end of transistorized grid electric connection the 3rd resistance, and P type triggers transistorized source electrode and is electrically connected reference voltage, in order in the time that current discharge passage is opened, the electric charge in load capacitance can be released.N-type triggers the electrical electricity of transistorized grid and connects the other end of the 3rd resistance, and N-type triggers transistorized drain electrode and be electrically connected the drain electrode of the 2nd P transistor npn npn, and N-type triggers transistorized source electrode and is electrically connected negative power line.

In one of them embodiment of the present invention, strangulation unit comprises N-type strangulation transistor.The transistorized grid of N-type strangulation is electrically connected N-type and triggers transistorized drain electrode, and the transistorized drain electrode of N-type strangulation is electrically connected output capacitance, and the transistorized source electrode of N-type strangulation is electrically connected negative power line.The transistor AND gate N-type that triggers P type triggers transistor and forms inverter, in the time that transformation enable signal is high-voltage level, P type triggering transistor is closed and the unlatching of N-type triggering transistor, and the transistorized grid of N-type strangulation receives the voltage of negative power line, with close current discharge channel, in the time that transformation enable signal is low voltage level, the unlatching of P type triggering transistor and N-type triggering transistor are closed, and the transistorized grid of N-type strangulation receives reference voltage, with firing current discharge channel.

In one of them embodiment of the present invention, ESD protection circuit more comprises catching diode.The anode of catching diode is electrically connected positive power line, and the negative electrode of catching diode is electrically connected P type and triggers transistorized source electrode, and catching diode triggers the voltage level of transistorized source electrode in order to determine P type.In one of them embodiment of the present invention; when transformation enable signal is high-voltage level; bias circuit is in normal operating conditions; and voltage conversion circuit is enabled; and ESD protection circuit close current discharge channel, voltage conversion circuit output charging current to load capacitance to produce output voltage.

In one of them embodiment of the present invention, voltage conversion circuit is low dropout voltage regulator, in order to input voltage is given to step-down and regulated output voltage.

In one of them embodiment of the present invention, low dropout voltage regulator comprises the first amplifier, a P transistor npn npn, the first resistance and the second resistance.The negative input end of the first amplifier receives reference voltage, and the output of the first amplifier is exported the first voltage.The grid of the one P transistor npn npn receives the first voltage, and the source electrode of a P transistor npn npn is electrically connected input voltage, the drain electrode output output voltage of a P transistor npn npn.One end of the first resistance is electrically connected the drain electrode of a P transistor npn npn, and the other end of the first resistance is exported feedback voltage and feedback voltage is sent to the positive input terminal of the first amplifier.One end of the second resistance is electrically connected the other end of the first resistance, and the other end of the second resistance is electrically connected earthed voltage.In the time that feedback voltage is greater than reference voltage, the electric current of the first voltage rising and first and second resistance of flowing through declines, and then reduces output voltage, in the time that feedback voltage is less than reference voltage, the Current rise of the first voltage drop and first and second resistance of flowing through, and then increase output voltage.

In one of them embodiment of the present invention, ESD protection circuit comprises strangulation unit, a trigger element and a control unit.Described control unit comprises the 3rd resistance and the first electric capacity.Described trigger element comprises the 2nd P transistor npn npn and the first N-type transistor.Described strangulation unit comprises the second N-type transistor.One end of the 3rd resistance is electrically connected the drain electrode of a P transistor npn npn, and the other end of the 3rd resistance receives transformation enable signal.One end of the first electric capacity is electrically connected the other end of the 3rd resistance, and the other end of the first electric capacity is electrically connected earthed voltage.The grid of the 2nd P transistor npn npn is electrically connected the other end of the 3rd resistance, and the source electrode of the 2nd P transistor npn npn is electrically connected stable second voltage, in order in the time that current discharge passage is opened, the electric charge in load capacitance can be released.The electrical electricity of the transistorized grid of the first N-type connects the other end of the 3rd resistance, and the transistorized drain electrode of the first N-type is electrically connected the drain electrode of the 2nd P transistor npn npn, and the transistorized source electrode of the first N-type is electrically connected earthed voltage.The transistorized grid of the second N-type is electrically connected the transistorized drain electrode of the first N-type, and the transistorized drain electrode of the second N-type is electrically connected output voltage, and the transistorized source electrode of the second N-type is electrically connected earthed voltage.Wherein the 2nd P transistor npn npn and the first N-type transistor form inverter, in the time that transformation enable signal is high-voltage level, the 2nd P transistor npn npn is closed and the unlatching of the first N-type transistor, and the transistorized grid of the second N-type receives earthed voltage, with close current discharge channel, in the time that transformation enable signal is low voltage level, the 2nd P transistor npn npn unlatching and the first N-type transistor are closed, and the transistorized grid of the second N-type receives second voltage, with firing current discharge channel.

In one of them embodiment of the present invention, ESD protection circuit more comprises the first diode.The anode of the first diode is electrically connected output voltage, the negative electrode of the first diode is electrically connected the source electrode of the 2nd P transistor npn npn, when bias circuit is subject to static when bombardment and makes output voltage abnormal ascending, the voltage of the source electrode of the 2nd P transistor npn npn is the conducting voltage that output voltage deducts the first diode, in order to maintain the unlatching of current discharge passage in discharge process.

In one of them embodiment of the present invention, ESD protection circuit comprises the 3rd P transistor npn npn, the second electric capacity, the 4th P transistor npn npn, the 3rd N-type transistor AND gate the 4th N-type transistor.The grid of the 3rd P transistor npn npn receives transformation enable signal, and the source electrode of the 3rd P transistor npn npn is electrically connected output voltage.One end of the second electric capacity is electrically connected the drain electrode of the 3rd P transistor npn npn, and the other end of the second electric capacity is electrically connected earthed voltage.The grid of the 4th P transistor npn npn is electrically connected the drain electrode of the 3rd P transistor npn npn, and the source electrode of the 4th P transistor npn npn is electrically connected stable tertiary voltage, in order in the time that current discharge passage is opened, the electric charge in load capacitance can be released.The electrical electricity of the transistorized grid of the 3rd N-type connects the drain electrode of the 3rd P transistor npn npn, and the transistorized drain electrode of the 3rd N-type is electrically connected the drain electrode of the 4th P transistor npn npn, and the transistorized source electrode of the 3rd N-type is electrically connected earthed voltage.The transistorized grid of the 4th N-type is electrically connected the transistorized drain electrode of the 3rd N-type, and the transistorized drain electrode of the 4th N-type is electrically connected output voltage, and the transistorized source electrode of the 4th N-type is electrically connected earthed voltage.Wherein the 4th P transistor npn npn and the 3rd N-type transistor form inverter, in the time that transformation enable signal is high-voltage level, the the 3rd and the 4th P transistor npn npn is closed and the unlatching of the 3rd N-type transistor, and the transistorized grid of the 4th N-type receives earthed voltage, with close current discharge channel, in the time that transformation enable signal is low voltage level, the 3rd and the 4th P transistor npn npn unlatching and the 3rd N-type transistor are closed, and the transistorized grid of the 4th N-type receives tertiary voltage, with firing current discharge channel.

In one of them embodiment of the present invention, ESD protection circuit more comprises the second diode.The anode of the second diode is electrically connected output voltage, the negative electrode of the second diode is electrically connected the source electrode of the 4th P transistor npn npn, when bias circuit is subject to static when bombardment and makes output voltage abnormal ascending, the voltage of the source electrode of the 4th P transistor npn npn is the conducting voltage that output voltage deducts the second diode, in order to maintain the unlatching of current discharge passage in discharge process.

The embodiment of the present invention separately provides a kind of electronic installation, and described electronic installation comprises bias circuit and load, and wherein load is electrically connected bias circuit, to receive output voltage.Bias circuit comprises voltage conversion circuit and ESD protection circuit.Voltage conversion circuit is in order to be converted to output voltage by received input voltage, and wherein output voltage is stored in load capacitance.ESD protection circuit is electrically connected to output voltage, and ESD protection circuit receives and decides the unlatching of its inner current discharge passage or close according to transformation enable signal.In the time that transformation enable signal is low voltage level, bias circuit is in closed condition, and ESD protection circuit firing current discharge channel, and discharging current is from load capacitance inflow current discharge channel, so that the electric charge in load capacitance is discharged.

In sum; bias circuit that the embodiment of the present invention proposes and electronic installation; in the time that transformation enable signal is low voltage level; bias circuit cuts out from normal operating conditions; ESD protection circuit can be by enforced opening current discharge passage, makes the discharging current can be from load capacitance inflow current discharge channel.Accordingly, this disclosure does not only need to increase the discharge time that extra layout area just can efficient reduction load capacitance, more can make the cost of integrated circuit decline and improve the antistatic effect of bias circuit.

For enabling further to understand feature of the present invention and technology contents, refer to following about detailed description of the present invention and accompanying drawing, but these multiple explanations and appended graphic the present invention that is only used for illustrating but not do any restriction to claim scope of the present invention.

Brief description of the drawings

Explain specific embodiments of the invention with reference to alterations above, by this can be more clear to the present invention, in these are graphic:

Figure 1A is the circuit diagram of existing bias circuit.

Figure 1B is the schematic diagram of another existing bias circuit.

Fig. 2 A is the block schematic diagram according to the ESD protection circuit of the embodiment of the present invention.

Fig. 2 B is the block schematic diagram according to the ESD protection circuit of the embodiment of the present invention.

Fig. 3 A is according to the schematic diagram of the bias circuit of the embodiment of the present invention.

Fig. 3 B is according to the schematic diagram of the bias circuit that do not power on of the embodiment of the present invention.

Fig. 3 C is according to the schematic diagram of the bias circuit in normal operating conditions of the embodiment of the present invention.

Fig. 3 D is according to the schematic diagram that switches to the transient state bias circuit of closed condition in the embodiment of the present invention from operating state.

Fig. 4 is the physical circuit schematic diagram of bias circuit according to another embodiment of the present invention.

Fig. 5 A is the voltage time oscillogram of the discharge waveform of existing bias circuit.

Fig. 5 B is the voltage time oscillogram of the discharge waveform of the bias circuit of corresponding diagram 2D.

Fig. 6 is the concrete schematic diagram of bias circuit of not powering on according to another embodiment of the present invention.

Fig. 7 is the physical circuit figure of bias circuit according to yet another embodiment of the invention.

Fig. 8 is the concrete schematic diagram of the bias circuit that do not power on according to yet another embodiment of the invention.

Fig. 9 is the schematic diagram of the electronic installation of the embodiment of the present invention.

Wherein, description of reference numerals is as follows:

10,20: existing bias circuit

12: low dropout voltage regulator

14: ESD protection circuit

200: ESD protection circuit

210: control unit

220: trigger element

230: strangulation unit

300,400,600,700,800: bias circuit

310: voltage conversion circuit

320: ESD protection circuit

410: low dropout voltage regulator

900: electronic installation

910: bias circuit

920: load

C: output capacitance

C1: the first electric capacity

C2: the second electric capacity

CL ', CL: load capacitance

CS: control signal

D1: the first diode

D2: the second diode

ENS: transformation enable signal

GND: earthed voltage

I1: electric current

IC: charging current

ID: discharging current

IES: electrostatic induced current

LDO_en: enable signal

LDO_enb: switching signal

MN ': N-type transistor

MN1: the first N-type transistor

MN2: the second N-type transistor

MN3: the 3rd N-type transistor

MN4: the 4th N-type transistor

MNT:N type triggers transistor

MNC:N type strangulation transistor

MP ': P transistor npn npn

MP1: a P transistor npn npn

MP2: the 2nd P transistor npn npn

MP3: the 3rd P transistor npn npn

MP4: the 4th P transistor npn npn

MPT:P type triggers transistor

N1, n2: node

OP ': amplifier

OP: the first amplifier

R: controlling resistance

R1: the first resistance

R1 ': feedback resistance

R2 ', R2: the second resistance

R3: the 3rd resistance

R3 ': resistance

T1: negative input end

T2: positive input terminal

TC: control capacitance

V1: the first voltage

V2: second voltage

V3: tertiary voltage

VDD: positive power line

VSS: negative power line

VF ', VF: feedback voltage

VIN ', VIN: input voltage

VR, VREF ', VREF: reference voltage

VOUT ', VOUT: output voltage

Embodiment

Below describing more fully various exemplary embodiments referring to alterations, in alterations, show some exemplary embodiments.But concept of the present invention may be with many multi-form embodiments, and should not be construed as and be limited to the exemplary embodiments set forth herein.Definite, provide these multiple exemplary embodiments to make the present invention will be for detailed and complete, and will fully pass on the category of concept of the present invention to those skilled in the art.All graphic in, can be for clear and lavish praise on oneself size and the relative size in Ceng Ji district.Similar numeral is indicated like all the time.

Although should be understood that herein and may describe various elements by term first, second, third, etc., these multiple elements are not limited by these multiple terms should.These multiple terms are to distinguish an element and another element.Therefore the first element of, below discussing can be described as the second element and does not depart from the teaching of concept of the present invention.As used herein, term " and/or " comprise any one and one or many person's all combinations in project of listing that are associated.

(embodiment of ESD protection circuit)

Please refer to Fig. 2 A, Fig. 2 A is the block schematic diagram according to the ESD protection circuit of the embodiment of the present invention.In the present embodiment, ESD protection circuit 200 comprises control unit 210, trigger element 220 and strangulation unit 230.Strangulation unit 230 is coupled between positive power line VDD and negative power line VSS.Trigger element 220 has an input and an output, and trigger element 220 couples negative power line VSS and reference voltage VR, and the output of trigger element 220 is coupled to strangulation unit 230, in order to trigger strangulation unit 230.Control unit 210 is coupled to this input of positive power line VDD, negative power line VSS and trigger element 220.Control unit 210 receives transformation enable signal ENS and triggers described trigger element 220 according to control signal CS, and determines by this unlatching of the current discharge passage in strangulation unit 230 or close.

In an embodiment; be coupled to other circuit blocks (Fig. 2 A does not illustrate) at the positive power line VDD of ESD protection circuit 200; and other circuit blocks produce in output capacitance C in the situation of an output voltage; in the time that transformation enable signal ENS is low voltage level (that is other circuit blocks is closed in its operating state), control unit 210 can be according to received transformation enable signal ENS transfer control signal CS to trigger element 220.Then the current discharge passage that, trigger element 220 can be opened strangulation unit 230 according to received control signal CS is to discharge the output voltage on output capacitance C.On the other hand, in the time that transformation enable signal ENS is high-voltage level (that is in the normal work of other circuit blocks), control unit 210 can be according to received transformation enable signal ENS transfer control signal CS to trigger element 220.Then, the current discharge passage that trigger element 220 can be closed strangulation unit 230 according to received control signal CS, to maintain the output voltage on output capacitance C.It is worth mentioning that, in one embodiment, transformation enable signal ENS equals control signal CS.

(another embodiment of ESD protection circuit)

Please refer to Fig. 2 B, Fig. 2 B is the block schematic diagram according to the ESD protection circuit of the embodiment of the present invention.Different from above-mentioned Fig. 2 A embodiment, control unit 210 comprises controlling resistance R and control capacitance TC.Trigger element 220 comprises that P type triggers transistor MPT and N-type triggers transistor MNT.Strangulation unit 230 comprises N-type strangulation transistor MNC.

One end of controlling resistance R is electrically connected positive power line VDD, and the other end of controlling resistance R receives transformation enable signal ENS.One end of control capacitance TC is electrically connected the other end of controlling resistance R, and the other end of control capacitance TC is electrically connected negative power line VSS.P type triggers the other end of the grid electric connection controlling resistance R of transistor MPT, and the source electrode that P type triggers transistor MPT is electrically connected reference voltage VR, in order in the time that current discharge passage is opened, the electric charge on an output capacitance C can be released.The electrical electricity of grid of N-type triggering transistor MNT connects the other end of this controlling resistance R, and the drain electrode of N-type triggering transistor MNT is electrically connected the drain electrode of this P type triggering transistor MPT, and the source electrode that N-type triggers transistor MNT is electrically connected negative power line VSS.The grid of N-type strangulation transistor MNC is electrically connected the drain electrode of N-type triggering transistor MNT, and the drain electrode of N-type strangulation transistor MNC is electrically connected an output capacitance C, and the source electrode of N-type strangulation transistor MNC is electrically connected this negative power line VSS.

In the present embodiment, must first illustrate, the grid that triggers transistor MPT and N-type triggering transistor MNT due to P type is coupled to transformation enable signal ENS, so control signal CS equals transformation enable signal ENS.Be coupled to other circuit blocks (Fig. 2 B does not illustrate) in the positive power line VDD of ESD protection circuit 200; and other circuit blocks produce in output capacitance C in the situation of an output voltage; in the time that transformation enable signal ENS is low voltage level (that is other circuit blocks is closed in its operating state), the current discharge passage that the P type triggering transistor MPT of formation inverter and N-type triggering transistor MNT can open N-type strangulation transistor MNT according to received transformation enable signal ENS is to discharge the output voltage on output capacitance C.In other words, P type triggers that transistor MPT can open and N-type triggers transistor MNT and can close, and then makes the grid of N-type strangulation transistor MNT be coupled to reference voltage VREF and firing current discharge channel.

On the other hand, in the time that transformation enable signal ENS is high-voltage level (that is in the normal work of other circuit blocks), the current discharge passage that the P type triggering transistor MPT of formation inverter and N-type triggering transistor MNT can close N-type strangulation transistor MNT according to received transformation enable signal ENS is to be maintained the output voltage on output capacitance C.In other words, P type triggers that transistor MPT can close and N-type triggers transistor MNT and can open, and then makes the grid of N-type strangulation transistor MNT be coupled to negative power line and firing current discharge channel.In one embodiment, negative power line VSS is coupled to earthed voltage, is not limited with the present embodiment.

In order to illustrate in greater detail the operation workflow of bias circuit 200 of the present invention, below by for one of at least doing further description in multiple embodiment.

In ensuing multiple embodiment, description is different to the part of above-mentioned Fig. 2 A～2B embodiment, and all the other clippeds are identical with the part of above-mentioned Fig. 2 A～2B embodiment.In addition,, for the purpose of facility is described, similar reference number or label are indicated similar element.

(embodiment of bias circuit)

Please refer to Fig. 3 A, Fig. 3 A is according to the schematic diagram of the bias circuit of the embodiment of the present invention.Bias circuit 300 comprises voltage conversion circuit 310 and ESD protection circuit 320.ESD protection circuit 320 is electrically connected voltage conversion circuit 310.As shown in Figure 3A, voltage conversion circuit 310 is in order to be converted to output voltage VO UT by received input voltage VIN, and wherein output voltage VO UT is stored on load capacitance CL.ESD protection circuit 320 receives and decides according to transformation enable signal ENS unlatching or the closed condition of its inner current discharge passage.Bias circuit 300 can be band gap reference circuit or other voltage boosting/lowering circuits.

In an embodiment of this disclosure; in the time that transformation enable signal ENS is low voltage level (low voltage level); bias circuit 300 is in closed condition; 320 of ESD protection circuits can firing current discharge channel; and discharging current can be from the current discharge passage of load capacitance CL inflow ESD protection circuit 320 inside, so that the electric charge on load capacitance CL is discharged fast.In a preferred embodiment, the electric charge of load capacitance CL can be discharged completely.On the other hand; in the time that transformation enable signal ENS is high-voltage level (high voltage level); bias circuit 300 is in normal operating conditions; and voltage conversion circuit 310 can be enabled; and ESD protection circuit 320 can close current discharge channels, so make voltage conversion circuit 310 export charging current to load capacitance CL to produce stable output voltage VO UT.

In order more to clearly demonstrate this disclosure, to carry out the concrete action of teaching bias circuit 300 further from three kinds of states below, wherein three kinds of states instruction bias circuit 200 is installed on operating state and the closed condition on circuit board from having manufactured to being installed on (not powering on) and bias circuit 200 process of circuit board.

Please refer to Fig. 3 B, Fig. 3 B is according to the schematic diagram of the bias circuit that do not power on of the embodiment of the present invention.When bias circuit 300 is from having manufactured to being installed on the process of circuit board (that is not powering on), " not powering on " be defined as do not have any input voltage VIN, reference voltage VREF and transformation enable signal ENS.Owing to human body contact feet position (pin) or other factors may occur touching to make in the situation of pin position the output voltage VO UT abnormal ascending of output; while reaching the trigger condition of ESD protection circuit 320; ESD protection circuit 320 can unlatching one static discharge passage make electrostatic induced current IES directly guide inflow place (ground) via static discharge passage, the function that reduces integrated circuit to avoid damageeing the inner member of voltage conversion circuit 310.

On the other hand, please refer to Fig. 3 C, Fig. 3 C is according to the schematic diagram of the bias circuit in normal operating conditions of the embodiment of the present invention.When bias circuit 300 is installed on after circuit board, voltage conversion circuit 310 is with ESD protection circuit 320 meeting receptions and according to the transformation enable signal ENS of a high-voltage level and in normal operating conditions.Then, voltage conversion circuit 310 can be converted to input voltage VIN output voltage VO UT and export next stage circuit blocks (Fig. 2 B does not illustrate) to.That is to say, it is upper to store electric charge to load capacitance CL that voltage conversion circuit 310 can be exported a charging current IC, to export stable in fact output voltage VO UT to provide next stage circuit blocks to use.It should be noted that; at the same time; ESD protection circuit 320 can be according to transformation enable signal ENS by current discharge pathway closure, to guarantee that charging current IC can not flow to via current discharge passage ground, and then reaches bias circuit 300 and be scheduled to the output voltage VO UT exporting.

Finally, please refer to Fig. 3 D, Fig. 3 D switches to the schematic diagram of the transient state bias circuit of closed condition according to the embodiment of the present invention from operating state.When bias circuit 300 is installed on after circuit board, voltage conversion circuit 310 can receive and switch to closed condition according to the transformation enable signal ENS of a low voltage level from normal operating conditions with ESD protection circuit 320.Now; voltage conversion circuit 310 can be disabled and stop exporting charging current to load capacitance CL; and ESD protection circuit 320 can be according to transformation enable signal ENS and in the inner portion produce a current discharge passage, and then can guide current discharge passage that discharging current ID flow to ESD protection circuit 320 inside from load capacitance CL to discharge fast the electric charge load capacitance CL.Therefore,, in the time that bias circuit 300 switches to closed condition from normal operating conditions, output voltage OUT can drop to rapidly and approach no-voltage, and can not have influence on the action of next stage circuit.In another embodiment, output voltage OUT can drop to no-voltage rapidly, is not limited with the present embodiment.

In order to illustrate in greater detail the operation workflow of bias circuit 300 of the present invention, below by for one of at least doing further description in multiple embodiment.

In ensuing multiple embodiment, description is different to the part of above-mentioned Fig. 3 A～3D embodiment, and all the other clippeds are identical with the part of above-mentioned Fig. 3 A～3D embodiment.In addition,, for the purpose of facility is described, similar reference number or label are indicated similar element.

(another embodiment of bias circuit)

Please refer to Fig. 4, Fig. 4 is the physical circuit schematic diagram of bias circuit according to another embodiment of the present invention.As shown in Figure 4, in the present embodiment, voltage conversion circuit is low dropout voltage regulator 410 (Low Dropout Regulator, LDO), in order to input voltage VIN is given to the output voltage VO UT of step-down and stable output.In other embodiments, voltage conversion circuit can be other reduction voltage circuit or booster circuit, is not limited with the present embodiment.For convenience of description, below explanation will be made an example with low dropout voltage regulator 410 and come the overall start of teaching bias circuit.Low dropout voltage regulator 410 comprises the first amplifier OP, a P transistor npn npn MP1, the first resistance R 1 and the second resistance R 2.ESD protection circuit 200 comprises strangulation unit 230, trigger element 220 and control unit 210.Control unit 210 comprises the 3rd resistance R 3 and the first capacitor C 1.Trigger element 220 comprises the 2nd P transistor npn npn MP2 and the first N-type transistor MN1.Strangulation unit 230 comprises the second N-type transistor MN2.

The negative input end I1 of the first amplifier OP receives reference voltage VREF, and the output of the second amplifier OP is exported the first voltage V1.The grid of the one P transistor npn npn MP1 receives the first voltage V1, and the source electrode of a P transistor npn npn MP1 is electrically connected input voltage VIN, and an output voltage VO UT is exported in the drain electrode of a P transistor npn npn MP1.One end of the first resistance R 1 is electrically connected the drain electrode of a P transistor npn npn MP1, and the other end of the first resistance R 1 is exported a feedback voltage V F and feedback voltage V F is sent to the positive input terminal T2 of the first amplifier OP.One end of the second resistance R 2 is electrically connected the other end of the first resistance R 1, and the other end of the second resistance R 2 is electrically connected earthed voltage GND.One end of the 3rd resistance R 3 is electrically connected the drain electrode of a P transistor npn npn MP1, and the other end of the 3rd resistance R 3 receives transformation enable signal ENS.One end of the first capacitor C 1 is electrically connected the other end of the 3rd resistance R 3, and the other end of the first capacitor C 1 is electrically connected earthed voltage GND.The grid of the 2nd P transistor npn npn MP2 is electrically connected the other end of the 3rd resistance R 3, and the source electrode of the 2nd P transistor npn npn MP2 is electrically connected stable second voltage V2.The grid of the first N-type transistor MN1 is electrically connected the other end of the 3rd resistance R 3, and the drain electrode of the first N-type transistor MN1 is electrically connected the drain electrode of the 2nd P transistor npn npn MP2, and the source electrode of the first N-type transistor MN1 is electrically connected earthed voltage GND.The grid of the second N-type transistor MN2 is electrically connected the drain electrode of the first N-type transistor MN1, and the drain electrode of the second N-type transistor MN2 is electrically connected output voltage VO UT, and the source electrode of the second N-type transistor MN2 is electrically connected earthed voltage GND.

Below will illustrate, be the concrete start about bias circuit 400 in Fig. 4 embodiment.

Continue referring to Fig. 4, when bias circuit 400 is installed on after circuit board, low dropout voltage regulator 410 is with ESD protection circuit 200 meeting receptions and according to the transformation enable signal ENS of a high-voltage level and in normal operating conditions.The source electrode of the one P transistor npn npn MP1 couples input voltage VIN to receive input voltage VIN, and the size of output voltage VO UT can be decided by the value of reference voltage VREF, the first resistance R 1 and the second resistance R 2.Furthermore, because the configuration of the first amplifier OP is imaginary short relation, so feedback voltage V F can equal in fact reference voltage VREF, therefore designer can design according to circuit design demand or practical application request the size of predetermined output voltage VO UT according to equation (1).

VOUT=[(R1+R2)/R2] x VREF equation (1)

In the time that feedback voltage V F is greater than reference voltage VREF, the first voltage V1 that the first amplifier OP exports can rise, and the grid source electrode cross-pressure of a P transistor npn npn MP1 can be declined, and then the electric current I 1 of cause flowing through the first resistance R 1 and the second resistance R 2 declines.Therefore, according to the relation of current resistor voltage drop (IR drop), output voltage VO UT can decline, and then causes feedback voltage V F to decline until feedback voltage V F is less than reference voltage VREF.In the time that feedback voltage V F is less than reference voltage VREF, the first voltage V1 that the first amplifier OP exports can decline, and makes the grid source electrode cross-pressure of a P transistor npn npn MP1 to increase, and then the electric current I 1 of cause flowing through the first resistance R 1 and the second resistance R 2 rises.Therefore, according to the relation of current resistor voltage drop (IR drop), output voltage VO UT can rise, and then causes feedback voltage V F to rise until feedback voltage V F is less than reference voltage VREF.According to above-mentioned negative feedback (negative feedback) mechanism, low dropout voltage regulator 410 can provide stable output voltage VO UT, and designer can further decide the size of output voltage VO UT according to the value of reference voltage VREF, the first resistance R 1 and the second resistance R 2.

Now; because the node n1 in ESD protection circuit 200 receives the transformation enable signal ENS of high-voltage level, so the inverter (inverter) forming due to the 2nd P transistor npn npn M2 and the first N-type transistor MN1 also receives the transformation enable signal ENS of high-voltage level simultaneously.Therefore, the 2nd P transistor npn npn MP2 can be in closed condition, and the first N-type transistor MN1 can be in opening, and then the signal that makes inverter export a low voltage level is sent to the second N-type transistor MN2.That is to say, the grid of the second N-type transistor MN2 can receive or be electrically connected to earthed voltage GND, and makes the second N-type transistor MN2 in closed condition.What deserves to be explained is; in the present embodiment, the second N-type transistor MN2 is as the current discharge passage in ESD protection circuit 200, therefore; if the second N-type transistor MN2 is in closed condition, the current discharge passage in ESD protection circuit 220 is also in closed condition.Therefore, when low dropout voltage regulator 410 export a charging current IC to load capacitance CL when output voltage VO UT to be provided to next stage circuit blocks (Fig. 3 does not illustrate), charging current IC can't flow through current discharge passage and produce the phenomenon of leakage current (leakage current).

On the other hand, in the time that low dropout voltage regulator 410 can receive the transformation enable signal ENS of a low voltage level with ESD protection circuit 200, low dropout voltage regulator 410 can be disabled and switch to closed condition from normal operating conditions.Node n1 in ESD protection circuit 200 is receiving after the transformation enable signal ENS of low voltage level, can make the 2nd P transistor npn npn MP2 in inverter in opening, and the first N-type transistor MN1 is in closed condition.Then, inverter can be exported the grid of second voltage V2 to the second N-type transistor MN2 to open the second N-type transistor MN2, and then opens the current discharge passage in ESD protection circuit 200.Then; discharging current ID can flow to from load capacitance CL ground through current discharge passage; that is to say; electric charge on load capacitance CL can be from the current discharge passage repid discharge of ESD protection circuit 200 inside; so that output voltage VO UT fast-descending, and avoid having influence on the action of other circuit.In one embodiment, more can increase the integral passage width of the second N-type transistor MN2 to reduce electric conduction group, and then improve discharging efficiency.

It is worth mentioning that, in the present embodiment, because the grid of the second N-type transistor MN2 is electrically connected to stable second voltage V2, so in the transient process of circuit discharging, output voltage VO UT can constantly decline, but the grid voltage of the second N-type transistor MN2 still can keep stable second voltage V2.That is to say, the grid source electrode cross-pressure of the second N-type transistor MN2 keeps second voltage V2 that can be stable.Therefore, be coupled to output voltage VO UT compared to the source electrode of the 2nd P transistor npn npn MP2 of the prior art, this disclosure contributes to the electric charge on load capacitance CL to discharge fast complete, and can effectively promote the speed of electric discharge.Subsidiary one carries, and second voltage V2 can be system voltage or other stable voltage.

In order to better understand this disclosure, referring to Fig. 5 A and Fig. 5 B.Fig. 5 A is the voltage time oscillogram of the discharge waveform of existing bias circuit.Fig. 5 B is the voltage time oscillogram of the discharge waveform of the bias circuit of corresponding diagram 3D.From Fig. 5 A and Fig. 5 B, existing bias circuit is discharged to 10% by the voltage of load capacitance by 90% approximately needs 500 microseconds, approximately only needs 2 microseconds but the voltage of load capacitance CL is discharged to 10% by 90% at the bias circuit 400 of this disclosure.Therefore compared to prior art, this disclosure can reduce discharge time significantly, and layout area that need be not extra.

In addition, please refer to Fig. 5, Fig. 5 is the concrete schematic diagram of bias circuit of not powering on according to another embodiment of the present invention.ESD protection circuit 200 more comprises the first diode D1.The anode of the first diode D1 is electrically connected output voltage VO UT, and the negative electrode of the first diode D1 is electrically connected the source electrode of the 2nd P transistor npn npn MP2.In the present embodiment, the first diode D1 in order to determine the voltage level (when being subjected to static when bombardment) of source electrode of the 2nd P transistor npn npn MP2 before bias circuit 500 does not power on.

When bias circuit 600 is from having manufactured to being installed on the process of circuit board (that is not powering on), " do not power on " to be defined as and do not have any input voltage VIN, reference voltage VREF and transformation enable signal ENS, owing to human body may occur touching situation that pin position (pin) or other factors touch pin position (pin) and make the output voltage VO UT abnormal ascending of output, in the time reaching the trigger condition of ESD protection circuit 200, ESD protection circuit 200 can unlatching one static discharge passage make electrostatic induced current IES directly guide inflow place (ground) via static discharge passage, the function that reduces integrated circuit to avoid damageeing the inner member of low dropout voltage regulator 410.Therefore, when the pin position of integrated circuit (IC) chip or output are subjected to static bombardment and while making output voltage VO UT abnormal ascending, in order expliciting the position to go out the voltage level of the source electrode of the 2nd P transistor npn npn MP2, the present embodiment utilizes the voltage-current characteristic of the first diode D1, the voltage level of the source electrode of the 2nd P transistor npn npn MP2 is orientated as to output voltage VO UT and is deducted the forward conducting voltage of the first diode D1, in discharge process to suffer static bombardment at bias circuit 600 after firing current discharge channel, can determine and maintain the unlatching of current discharge passage, contribute to electrostatic induced current IES to be directed to ground.

Specifically, due in human-body model, the rise time of its discharge waveform is about 10 nanoseconds, and the voltage waveform rise time of integrated circuit is about millisecond grade, so the capacity resistance cime constant of the 3rd resistance R 3 and the first capacitor C 1 (RC constant) is typically designed to the time between millisecond～nanosecond.Therefore, in the time that bias circuit 500 suffers static bombardment, output voltage VO UT meeting abnormal ascending, now, the source voltage of the 2nd P transistor npn npn MP2 is the conducting voltage that output voltage VO UT deducts the first diode D1.In this transient process, because the voltage of node n1 is generally mostly the level of low voltage this suspension joint in the situation that, so the 2nd P transistor npn npn MP2 can open, and the first N-type transistor MN1 can close, and make the grid voltage of the second N-type transistor MN2 equal in fact the source voltage of the 2nd P transistor npn npn MP2.That is to say, the grid voltage of the second N-type transistor MN2 is the conducting voltage that output voltage VO UT deducts the first diode D1, to guarantee the unlatching of the second N-type transistor MN2 or current discharge passage, and then make electrostatic induced current IES flow to ground via the second N-type transistor MN2.

In order to illustrate in greater detail the operation workflow of bias circuit of the present invention, below by for one of at least doing further description in multiple embodiment.

In ensuing multiple embodiment, description is different to the part of above-mentioned Fig. 2～6 embodiment, and all the other clippeds are identical with the part of above-mentioned Fig. 2～6 embodiment.In addition,, for the purpose of facility is described, similar reference number or label are indicated similar element.

(embodiment again of bias circuit)

Please refer to Fig. 7, Fig. 7 is the physical circuit figure of bias circuit according to yet another embodiment of the invention.Different from above-mentioned Fig. 4 embodiment, the 3rd resistance R 3 in ESD protection circuit 200, in the present embodiment, is to replace with the 3rd P transistor npn npn MP3, to improve the allomeric function of bias circuit 700.Furthermore, in the present embodiment, ESD protection circuit 200 comprises the 3rd P transistor npn npn MP3, the second capacitor C 2, the 4th P transistor npn npn MP4, the 3rd N-type transistor MN3 and the 4th N-type transistor MN4.

The grid of the 3rd P transistor npn npn MP3 receives transformation enable signal ENS, and the source electrode of the 3rd P transistor npn npn MP3 is electrically connected output voltage VO UT.One end of the second capacitor C 2 is electrically connected the drain electrode of the 3rd P transistor npn npn MP3, and the other end of the second capacitor C 2 is electrically connected earthed voltage GND.The grid of the 4th P transistor npn npn MP4 is electrically connected the drain electrode of the 3rd P transistor npn npn MP3, and the source electrode of the 4th P transistor npn npn MP4 is electrically connected stable tertiary voltage V3.The grid of the 3rd N-type transistor MN3 is electrically connected the drain electrode of the 3rd P transistor npn npn MP3, and the drain electrode of the 3rd N-type transistor MN3 is electrically connected the drain electrode of the 4th P transistor npn npn MP4, and the source electrode of the 3rd N-type transistor MN3 is electrically connected earthed voltage GND.The grid of the 4th N-type transistor MN4 is electrically connected the drain electrode of the 3rd N-type transistor MN3, and the drain electrode of the 4th N-type transistor MN4 is electrically connected output voltage VO UT, and the source electrode of the 4th N-type transistor MN4 is electrically connected earthed voltage GND.

Below will illustrate, be the concrete start about bias circuit 700 in Fig. 7 embodiment.

Continue referring to Fig. 7, when bias circuit 700 is installed on after circuit board, low dropout voltage regulator 410 is with ESD protection circuit 200 meeting receptions and according to the transformation enable signal ENS of a high-voltage level and in normal operating conditions.The source electrode of the one P transistor npn npn MP1 couples input voltage VIN to receive input voltage VIN, and the size of output voltage OUT can be decided by the value of reference voltage VREF, the first resistance R 1 and the second resistance R 2.Because the configuration of the first amplifier OP is imaginary short relation, so feedback voltage V F can equal in fact reference voltage VREF, therefore designer can design according to circuit design demand or practical application request the size of predetermined output voltage VO UT according to equation (1).

Now; because the node n2 in ESD protection circuit 200 receives the transformation enable signal ENS of high-voltage level; so the 3rd P transistor npn npn MP3 can be in closed condition; so in the second capacitor C 2, electric charge can not have influence on via the 3rd P transistor npn npn MP3 electric leakage the voltage level of node n2, and then has influence on follow-up circuit operation.Then the inverter (inverter), forming due to the 4th P transistor npn npn MP4 and the 3rd N-type transistor MN3 also receives the transformation enable signal ENS of high-voltage level simultaneously.Therefore, the 4th P transistor npn npn MP4 can be in closed condition, and the 3rd N-type transistor MN3 can be in opening, and then the signal that makes inverter export a low voltage level is sent to the 4th N-type transistor MN4.That is to say, the grid of the 4th N-type transistor MN4 can receive or be electrically connected to earthed voltage GND, and makes the 4th N-type transistor MN4 in closed condition.What deserves to be explained is; in the present embodiment, the 4th N-type transistor MN4 is as the current discharge passage in ESD protection circuit, therefore; if the 4th N-type transistor MN4 is in closed condition, the current discharge passage in ESD protection circuit 200 is also in closed condition.Therefore, when low dropout voltage regulator 410 export a charging current IC to load capacitance CL when output voltage VO UT to be provided to next stage circuit blocks (Fig. 6 does not illustrate), charging current IC can't flow through current discharge passage and produce the phenomenon of leakage current (leakage current).

On the other hand, in the time that low dropout voltage regulator 410 can receive the transformation enable signal ENS of a low voltage level with ESD protection circuit 200, low dropout voltage regulator 410 can be disabled and switch to closed condition from normal operating conditions.Node n2 in ESD protection circuit 200 is receiving after the transformation enable signal ENS of low voltage level; the 3rd P transistor npn npn MP3 can be opened; and make the 4th P transistor npn npn MP4 in inverter can be in opening, the 3rd N-type transistor MN3 can be in closed condition.Then, inverter can be exported the grid of tertiary voltage V3 to the four N-type transistor MN4 to open the 4th N-type transistor MN4, and then opens the current discharge passage in ESD protection circuit 200.Then; discharging current ID can flow to from load capacitance CL ground through current discharge passage; that is to say; electric charge on load capacitance CL can be from the current discharge passage repid discharge of ESD protection circuit 200 inside; so that output voltage VO UT fast-descending, and avoid having influence on the action of other circuit.In one embodiment, more can increase the integral passage width of the 4th N-type transistor MN4 to reduce conducting resistance, and then improve discharging efficiency.

It is worth mentioning that, in the present embodiment, because the grid of the 4th N-type transistor MN4 is electrically connected to respectively stable tertiary voltage V3 and output voltage VO UT with drain electrode, so, in the transient process of circuit discharging, output voltage VO UT can constantly decline, but the grid voltage of the 4th N-type transistor MN4 still can keep stable tertiary voltage V3.That is to say, the grid source electrode cross-pressure of the 4th N-type transistor MN4 keeps tertiary voltage V3 that can be stable.Therefore, be coupled to output voltage VO UT compared to the source electrode of the 4th P transistor npn npn MP4 of the prior art, this disclosure contributes to the electric charge on load capacitance CL to discharge fast complete, and can effectively promote the speed of electric discharge.Subsidiary one carries, and tertiary voltage V3 can be system voltage or other stable voltage.

In addition, please refer to Fig. 8, Fig. 8 is the concrete schematic diagram of the bias circuit that do not power on according to yet another embodiment of the invention.ESD protection circuit 200 more comprises the second diode D2.The anode of the second diode D2 is electrically connected output voltage VO UT, and the negative electrode of the second diode D2 is electrically connected the source electrode of the 4th P transistor npn npn MP4.In the present embodiment, the second diode D2 in order to determine the voltage level (when being subjected to static when bombardment) of source electrode of the 4th P transistor npn npn MP4 before bias circuit 800 does not power on.

When bias circuit 800 is from having manufactured to being installed on the process of circuit board (that is not powering on), " do not power on " to be defined as and do not have any input voltage VIN, reference voltage VREF and transformation enable signal ENS, owing to human body may occur touching situation that pin position (pin) or other factors touch pin position (pin) and make the output voltage VO UT abnormal ascending of output, in the time reaching the trigger condition of ESD protection circuit 200, ESD protection circuit 200 can unlatching one static discharge passage make electrostatic induced current IES directly guide inflow place (ground) via static discharge passage, the function that reduces integrated circuit to avoid damageeing the inner member of low dropout voltage regulator 410.Therefore, when the pin position of integrated circuit (IC) chip or output are subjected to static bombardment and while making output voltage VO UT abnormal ascending, in order expliciting the position to go out the voltage level of the source electrode of the 4th P transistor npn npn MP4, the present embodiment utilizes the voltage-current characteristic of the second diode D2, the voltage level of the source electrode of the 4th P transistor npn npn MP4 is orientated as to output voltage VO UT and is deducted the forward conducting voltage of the second diode D2, in discharge process to suffer static bombardment at bias circuit 800 after firing current discharge channel, can determine and maintain the unlatching of current discharge passage, contribute to electrostatic induced current IES to be directed to ground.

Specifically, due in human-body model, the rise time of its discharge waveform is about 10 nanoseconds, and the voltage waveform rise time of integrated circuit is about millisecond grade, so the 3rd equivalent electric group of P transistor npn npn MP3 and the capacity resistance cime constant of the first capacitor C 1 (RC constant) are typically designed to the time between millisecond～nanosecond, wherein the equivalent resistance of the 3rd P transistor npn npn MP3 can decide according to the geometry in technique or material parameter.Therefore, in the time that bias circuit 800 suffers static bombardment, output voltage VO UT meeting abnormal ascending, now, the source voltage of the 4th P transistor npn npn MP4 is the conducting voltage that output voltage VO UT deducts the second diode D2.In this transient process, because the voltage of node n2 is generally all the level of low voltage this suspension joint in the situation that, so the 4th P transistor npn npn MP4 can open, and the 3rd N-type transistor MN3 can close, and make the grid voltage of the 4th N-type transistor MN4 equal in fact the source voltage of the 4th P transistor npn npn MP4.That is to say, the grid voltage of the second N-type transistor MN2 is the conducting voltage that output voltage VO UT deducts the second diode D2, to guarantee the unlatching of the 4th N-type transistor MN4 or current discharge passage, and then make electrostatic induced current IES flow to ground via the 4th N-type transistor MN4.

(embodiment of electronic installation)

Please refer to Fig. 9, the schematic diagram of the electronic installation that Fig. 9 is the embodiment of the present invention.Electronic installation 900 comprises the bias circuit 910 of load 920 and electric property coupling load 920, and wherein bias circuit 910 receives input voltage VIN.Bias circuit 910 can be one of them of bias circuit 300,400,600,700 and 800 in above-described embodiment, and in order to provide stable output voltage VO UT to load 920.Electronic installation 900 can be various types of electronic installations, such as display unit, hand-held device or running gear etc.

(possible effect of embodiment)

In sum; bias circuit that the embodiment of the present invention proposes and electronic installation; in the time that transformation enable signal is low voltage level; bias circuit cuts out from normal operating conditions; ESD protection circuit can be by enforced opening current discharge passage, makes the discharging current can be from load capacitance inflow current discharge channel.Accordingly, this disclosure does not only need to increase the discharge time that extra layout area just can efficient reduction load capacitance, more can make the cost of integrated circuit decline and improve the ability of ESD protection circuit.

The foregoing is only embodiments of the invention, it is not in order to limit to Patent right requirement scope of the present invention.

Claims

1. an ESD protection circuit, is characterized in that, this ESD protection circuit comprises:

Strangulation unit, couples between positive power line and negative power line;

Trigger element, has input and output, and this trigger element couples this negative power line and reference voltage, and this output is coupled to this strangulation unit and in order to trigger this strangulation unit; And

Control unit, is coupled to this input of this positive power line, this negative power line and this trigger element, and this control unit receives transformation enable signal to trigger this trigger element, and determine by this this strangulation unit current discharge passage unlatching or close,

Wherein, in the time that this transformation enable signal is low voltage level, this trigger element can be opened this current discharge passage of this strangulation unit.

2. ESD protection circuit as claimed in claim 1, is characterized in that, this control unit comprises:

Controlling resistance, its one end is electrically connected this positive power line, and its other end receives this transformation enable signal; And

Control capacitance, its one end is electrically connected the other end of this controlling resistance, and its other end is electrically connected this negative power line.

3. ESD protection circuit as claimed in claim 1, is characterized in that, this trigger element comprises:

P type triggers transistor, and its grid is electrically connected the other end of this controlling resistance, and its source electrode is electrically connected this reference voltage, in order in the time that this current discharge passage is opened, the electric charge in load capacitance can be released; And

N-type triggers transistor, and the electrical electricity of its grid connects the other end of this controlling resistance, and its drain electrode is electrically connected this P type and triggers transistorized drain electrode, and its source electrode is electrically connected this negative power line.

4. ESD protection circuit as claimed in claim 3, is characterized in that, this strangulation unit comprises:

N-type strangulation transistor, its grid is electrically connected this N-type and triggers transistorized drain electrode, and its drain electrode is electrically connected output capacitance, and its source electrode is electrically connected this negative power line,

Wherein this P type triggers this N-type of transistor AND gate and triggers transistor formation inverter, in the time that this transformation enable signal is high-voltage level, this P type triggering transistor is closed and this N-type triggering transistor unlatching, and the transistorized grid of this N-type strangulation receives the voltage of this negative power line, to close this current discharge passage, in the time that this transformation enable signal is low voltage level, this P type triggering transistor unlatching and this N-type triggering transistor are closed, and the transistorized grid of this N-type strangulation receives this reference voltage, to open this current discharge passage.

5. ESD protection circuit as claimed in claim 4, is characterized in that, this ESD protection circuit more comprises:

Catching diode, its anode is electrically connected this positive power line, and its negative electrode is electrically connected this P type and triggers transistorized source electrode, and this catching diode triggers the voltage level of transistorized source electrode in order to determine this P type.

6. ESD protection circuit as claimed in claim 1, is characterized in that, this negative power line couples earthed voltage.

7. a bias circuit, is characterized in that, this bias circuit comprises:

Voltage conversion circuit, in order to received input voltage is converted to output voltage, wherein this output voltage is stored in load capacitance;

ESD protection circuit, is electrically connected to this output voltage, and this ESD protection circuit receives and decides the unlatching of its inner current discharge passage or close according to transformation enable signal,

Wherein, in the time that this transformation enable signal is low voltage level, this bias circuit is in closed condition, and this ESD protection circuit is opened this current discharge passage; and discharging current flows into this current discharge passage from this load capacitance, so that the electric charge in this load capacitance is discharged.

8. bias circuit as claimed in claim 7; it is characterized in that; when this transformation enable signal is high-voltage level; this bias circuit is in normal operating conditions; and this voltage conversion circuit is enabled; and this ESD protection circuit is closed this current discharge passage, this voltage conversion circuit output charging current to this load capacitance to produce this output voltage.

9. bias circuit as claimed in claim 8, is characterized in that, this voltage conversion circuit is low dropout voltage regulator, in order to this input voltage is given to step-down and stablizes this output voltage.

10. bias circuit as claimed in claim 9, is characterized in that, this low dropout voltage regulator comprises:

The first amplifier, its negative input end receives reference voltage, and its output is exported the first voltage;

The one P transistor npn npn, its grid receives this first voltage, and its source electrode is electrically connected input voltage, its this output voltage of drain electrode output;

The first resistance, its one end is electrically connected the drain electrode of a P transistor npn npn, and its other end is exported feedback voltage and this feedback voltage is sent to the positive input terminal of this first amplifier; And

The second resistance, its one end is electrically connected the other end of this first resistance, and its other end is electrically connected earthed voltage,

Wherein in the time that this feedback voltage is greater than this reference voltage, this first voltage rises and flows through that this first declines with the electric current of this second resistance, and then reduce this output voltage, in the time that this feedback voltage is less than this reference voltage, this first voltage drop and flow through this first with the Current rise of this second resistance, and then increase this output voltage.

11. bias circuits as claimed in claim 10, wherein this ESD protection circuit comprises strangulation unit, trigger element and control unit, it is characterized in that, this control unit comprises:

The 3rd resistance, its one end is electrically connected the drain electrode of a P transistor npn npn, and its other end receives this transformation enable signal; And

The first electric capacity, its one end is electrically connected the other end of the 3rd resistance, and its other end is electrically connected this earthed voltage;

Wherein this trigger element comprises:

The 2nd P transistor npn npn, its grid is electrically connected the other end of the 3rd resistance, and its source electrode is electrically connected stable second voltage, in order in the time that this current discharge passage is opened, the electric charge in this load capacitance can be released; And

The first N-type transistor, the electrical electricity of its grid connects the other end of the 3rd resistance, and its drain electrode is electrically connected the drain electrode of the 2nd P transistor npn npn, and its source electrode is electrically connected this earthed voltage;

Wherein this strangulation unit comprises:

The second N-type transistor, its grid is electrically connected the transistorized drain electrode of this first N-type, and its drain electrode is electrically connected this output voltage, and its source electrode is electrically connected this earthed voltage,

Wherein the 2nd P transistor npn npn and this first N-type transistor form inverter, in the time that this transformation enable signal is high-voltage level, the 2nd P transistor npn npn is closed and this first N-type transistor unlatching, and the transistorized grid of this second N-type receives this earthed voltage, to close this current discharge passage, in the time that this transformation enable signal is low voltage level, the 2nd P transistor npn npn unlatching and this first N-type transistor are closed, and the transistorized grid of this second N-type receives this second voltage, to open this current discharge passage.

12. bias circuits as claimed in claim 11, is characterized in that, this ESD protection circuit more comprises:

The first diode, its anode is electrically connected this output voltage, and its negative electrode is electrically connected the source electrode of the 2nd P transistor npn npn, and this first diode is in order to determine the voltage level of source electrode of the 2nd P transistor npn npn.

13. bias circuits as claimed in claim 12, it is characterized in that, when this bias circuit is subject to static when bombardment and makes this output voltage abnormal ascending, the voltage of the source electrode of the 2nd P transistor npn npn is the conducting voltage that this output voltage deducts this first diode, in order to maintain the unlatching of current discharge passage in discharge process.

14. bias circuits as claimed in claim 10, is characterized in that, this ESD protection circuit comprises:

The 3rd P transistor npn npn, its grid receives this transformation enable signal, and its source electrode is electrically connected this output voltage;

The second electric capacity, its one end is electrically connected the drain electrode of the 3rd P transistor npn npn, and its other end is electrically connected this earthed voltage;

The 4th P transistor npn npn, its grid is electrically connected the drain electrode of the 3rd P transistor npn npn, and its source electrode is electrically connected stable tertiary voltage, in order in the time that this current discharge passage is opened, the electric charge in this load capacitance can be released;

The 3rd N-type transistor, the electrical electricity of its grid connects the drain electrode of the 3rd P transistor npn npn, and its drain electrode is electrically connected the drain electrode of the 4th P transistor npn npn, and its source electrode is electrically connected this earthed voltage; And

The 4th N-type transistor, its grid is electrically connected the transistorized drain electrode of the 3rd N-type, and its drain electrode is electrically connected this output voltage, and its source electrode is electrically connected this earthed voltage,

Wherein the 4th P transistor npn npn and the 3rd N-type transistor form inverter, in the time that this transformation enable signal is high-voltage level, the 3rd close with the 4th P transistor npn npn and the unlatching of the 3rd N-type transistor, and the transistorized grid of the 4th N-type receives this earthed voltage, to close this current discharge passage, in the time that this transformation enable signal is low voltage level, the 3rd close with the 4th P transistor npn npn unlatching and the 3rd N-type transistor, and the transistorized grid of the 4th N-type receives this tertiary voltage, to open this current discharge passage.

15. bias circuits as claimed in claim 14, is characterized in that, this ESD protection circuit more comprises:

The second diode, its anode is electrically connected this output voltage, and its negative electrode is electrically connected the source electrode of the 4th P transistor npn npn, and this second diode is in order to determine the voltage level of source electrode of the 4th P transistor npn npn.

16. bias circuits as claimed in claim 15, it is characterized in that, when this bias circuit is subject to static when bombardment and makes this output voltage abnormal ascending, the voltage of the source electrode of the 4th P transistor npn npn is the conducting voltage that this output voltage deducts this second diode, in order to maintain the unlatching of current discharge passage in discharge process.

17. 1 kinds of electronic installations, is characterized in that, this electronic installation comprises:

Bias circuit as claimed in claim 7; And

Load, receives this output voltage.