TWI391030B - Method for enhancing esd protection in an integrated circuit and related device and integrated circuit - Google Patents

Description

Method and related device and phase for improving electrostatic discharge protection in an integrated circuit Offset circuit

The invention relates to a method for improving electrostatic discharge protection in an integrated circuit and related electrostatic discharge protection device and integrated circuit, in particular to an electrostatic discharge protection method for using an output buffer unit to conduct an electrostatic current and related electrostatic discharge Protection device and integrated circuit.

Electrostatie Diseharge (ESD) protection is to prevent the permanent circuit from being permanently damaged by the electrostatic discharge during the production, testing or use. In general, the protection capability of an integrated circuit for electrostatic discharge is reduced as its size is reduced. With the continuous improvement of the integrated circuit process technology, the transistor size of the integrated circuit has progressed from submicron to deep micron. Therefore, how to improve the electrostatic discharge protection becomes more important.

Please refer to FIG. 1 , which is a schematic diagram of a conventional integrated circuit 10 having an electrostatic discharge protection function. The integrated circuit 10 includes a detecting unit 100, a core circuit 102, a P-type MOS transistor P2, an N-type MOS transistor N2, and a current switch 106. The detecting unit 100 is composed of a PMOS transistor P1, an NMOS transistor N1, a resistor R1 and a capacitor C1 for detecting the voltage pulse signal of the electrostatic discharge, so as to turn on the current switch 106 in time to enable the electrostatic current to be turned on. . In other words, the electrostatic current enters the pin from the outside of the integrated circuit 10, is forward biased to the power supply through D1, and the detecting unit 100 can be used when the electrostatic discharge occurs. The opening action of the current switch 106 is controlled to conduct an electrostatic current to the ground to prevent the electrostatic current from affecting the operation of other components. The PMOS transistor P2 and the NMOS transistor N2 are output buffer units for providing an output signal buffer function to prevent the load from affecting the operation of the core circuit 102. In addition, the output terminals of the integrated circuit 10 are further connected with diodes D1 and D2 to provide a function of clamping voltage pulses so that the electrostatic voltage is clamped in a fixed range. It should be noted that the diodes D1 and D2 can be respectively formed by a diode-connected PMOS transistor and an NMOS transistor.

Therefore, the integrated circuit 10 passes through the detecting unit 100, and the current switch 106 is turned on in time to turn on the electrostatic current, and the electrostatic voltage is clamped in a fixed range through the diodes D1 and D2. However, if the integrated circuit 10 is not turned on, the NMOS transistor N2 or the PMOS transistor P2 is in an indeterminate half-on state. In other words, there is a possibility that the NMOS transistor N2 or the PMOS transistor P2 is in a state in which current can be conducted. In this case, if the crystal width of the NMOS transistor N2 or the PMOS transistor P2 is small, when electrostatic discharge occurs, permanent damage may occur due to the inability to withstand the high heat caused by the conduction of the electrostatic current.

In order to avoid the above situation, in general, in addition to the NMOS transistor N2 and the PMOS transistor P2 must be laid out according to the relevant ESD protection layout specification (ESD Rule), the diodes D1 and D2 must also have a larger area. layout. However, in this way, not only the area of the chip must be increased, but also it may not be helpful to turn on the electrostatic current. In addition, in NMOS transistor N2, PMOS Between the transistor P2 and the diodes D1 and D2, a resistor RS may be additionally added to reduce the electrostatic current flowing through the NMOS transistor N2 and the PMOS transistor P2, but when the NMOS transistor N2 and the PMOS transistor P2 When in an indeterminate half-on state, the electrostatic current may still flow through the NMOS transistor N2 and the PMOS transistor P2. In other words, even if the resistance RS is applied, the electrostatic current has a chance to destroy the NMOS transistor N2 or the PMOS transistor P2.

Accordingly, it is a primary object of the present invention to provide a method for enhancing electrostatic discharge protection in an integrated circuit and associated electrostatic discharge protection device and integrated circuit.

The invention discloses a method for improving electrostatic discharge protection in an integrated circuit, comprising: detecting a power signal of a power channel of the integrated circuit to generate a detection result; and displaying the power channel according to the detection result When the power signal includes a pulse signal, the output of the plurality of output buffer units of the integrated circuit is respectively controlled to conduct the current caused by the pulse signal to a ground end.

The present invention further discloses a device for improving electrostatic discharge protection in an integrated circuit, comprising a switch including a first end coupled to the power channel, a second end coupled to the ground end, and a third end And a fourth end coupled to the dispatching unit, configured to control the signal connection of the first end to the fourth end according to the voltage difference between the first end and the third end to generate the detection result; a resistor coupled between the first end and the third end of the switch; and a capacitor coupled to the third end of the switch Between the second ends.

The invention further discloses an integrated circuit capable of improving electrostatic discharge protection, comprising a power channel for providing a power signal; a core circuit for generating a plurality of signal processing results; and a plurality of output buffer units coupled to the core The circuit is configured to output the plurality of signal processing results; and an electrostatic discharge protection device includes a detecting unit coupled to the power channel for detecting a power signal of the power channel to generate a detection result; And a dispatching unit coupled to the detecting unit and the plurality of output buffering units for controlling the output of the plurality of output buffering units when the power signal of the power channel includes a pulse signal In the case, the current caused by the pulse signal is conducted to a ground end.

Please refer to FIG. 2, which is a schematic diagram of an integrated circuit 20 according to an embodiment of the present invention. The integrated circuit 20 can enhance electrostatic discharge protection, and includes a power supply channel PWR_CH, a core circuit 200, output buffer units OB_1 OB_n, and an electrostatic discharge protection device 202. The power channel PWR_CH is used to provide a power signal to drive the core circuit 200 to operate normally, thereby outputting a signal processing result through the output buffer units OB_1 OB OB_n. The ESD protection device 202 includes a detection unit 204 and an dispatch unit 206 for providing electrostatic discharge protection. The detecting unit 204 is coupled to the power channel PWR_CH for detecting the power signal of the power channel PWR_CH to generate a detection result DCT. The dispatching unit 206 is coupled to the detecting unit 204 for displaying the power signal packet of the power channel PWR_CH for detecting the result DCT. When a pulse signal is included, the output buffer units OB_1 OB OB_n are respectively controlled so that the current caused by the pulse signal is turned on to a ground GND_CH.

Briefly, through the electrostatic discharge protection device 202, when the electrostatic discharge is triggered by the power supply channel PWR_CH, the detection unit 204 can detect the occurrence of electrostatic discharge, and the dispatch unit 206 controls each output buffer unit OB_1. ~OB_n, the current caused by the pulse signal is turned on to the ground GND_CH to avoid permanent damage to the circuit caused by electrostatic discharge. The operation of the electrostatic discharge protection device 202 can be summarized as an electrostatic discharge protection process 30, as shown in FIG. The ESD protection process 30 includes the following steps: Step 300: Start.

Step 302: The detecting unit 204 detects a power signal of the power channel PWR_CH to generate a detection result DCT.

Step 304: When the detection result DCT shows that the power signal of the power channel PWR_CH includes the pulse signal, the dispatching unit 206 controls the output situations of the output buffer units OB_1 OB OB_n to turn on the current caused by the pulse signal to the ground GND_CH.

Step 306: End.

It is particularly noted that when the detection result DCT indicates that the power signal of the power channel PWR_CH includes a pulse signal, the dispatch unit 206 controls the output of the output buffer units OB_1 OB OB_ separately. In other words, the dispatch unit 206 does not simultaneously start the output buffer units OB_1 OB OB_n or simultaneously close the output buffer unit OB_1~OB_n, according to the characteristics of each output buffer unit, is controlled to conduct current caused by the pulse signal to the ground GND_CH, or to prevent the current caused by the pulse signal from flowing and causing damage.

In the prior art, the function of the output buffer unit is relatively simple, mainly to provide a buffer function to prevent the load from affecting the operation of the core circuit. In contrast, in the present invention, the output buffer unit performs a function of sharing a power clamp transistor to conduct an electrostatic current, in addition to a buffer serving as an output signal during normal operation, and when electrostatic discharge occurs.

On the other hand, the integrated circuit 20 shown in Fig. 2 is for explaining the spirit of the present invention, and those skilled in the art can make different modifications. For example, as shown in FIG. 4, the architecture of the detecting unit 204 can be modeled by the structure of the detecting unit 100 in FIG. 1, that is, by the PMOS transistor P1, the NMOS transistor N1, the resistor R1, and the capacitor C1. composition. The combination of the PMOS transistor P1 and the NMOS transistor N1 implements a switch for controlling the signal from the power channel PWR_CH to the dispatch unit 206 according to the voltage across the resistor R1 (ie, the voltage difference between the power channel PWR_CH and the node ND). Link to generate the detection result DCT.

The operation of the detecting unit 204 will be described in detail as follows. First, since the capacitor C1 is connected in series with the resistor R1, the power supply channel PWR_CH charges the capacitor C1 to produce a time delay effect. Therefore, when the pulse voltage caused by the electrostatic discharge reaches the source of the PMOS transistor P1, the node ND is generated by the electrostatic pulse with respect to the pulse voltage. The moment is at a lower voltage. At this time, the voltage across the resistor R1 is sufficient to turn on the PMOS transistor P1, so that the drain of the PMOS transistor P1 also reaches a high voltage level in an instant to generate the detection result DCT. In other words, taking FIG. 4 as an example, when the detection result DCT is a high voltage level, it means that the power supply channel PWR_CH of the integrated circuit 20 emits a voltage pulse signal, indicating that electrostatic discharge occurs.

As described above, in the present invention, the dispatch unit 206 controls the turn-on or turn-off according to the characteristics of each output buffer unit, such as the current load capability, to conduct the current caused by the pulse signal to the ground GND_CH. For example, for an output buffer unit having a current load capability higher than a predetermined condition, such as an output buffer unit having a large channel transistor, the dispatch unit 206 can be turned on when an electrostatic discharge occurs to serve as a task of turning on the electrostatic current; Conversely, for an output buffer unit having a current load capability lower than a preset condition, such as an output buffer unit having a small channel transistor, the dispatch unit 206 can be turned off when electrostatic discharge occurs to avoid being affected by the electrostatic current. In this case, when an electrostatic discharge occurs, the electrostatic current is conducted to the ground by the output buffer unit of the high current load capability without causing damage to the output buffer unit of the low current load capability.

It is particularly noted that the dispatch unit 206 controls each output buffer unit separately, and its implementation should vary with different system requirements. For example, please refer to FIG. 5 to FIG. 8 , and FIG. 5 to FIG. 8 are schematic diagrams showing the integrated circuits 50 , 60 , 70 , 80 according to the embodiment of the present invention. The integrated circuits 50, 60, 70, 80 are all changed by the integrated circuit 20 of Fig. 2, and only include two output transistors (PI1, NI1, PI2). NI2, PI3, NI3, PI4, NI4) are used as output buffer units. In addition, the electrostatic discharge protection devices of the integrated circuits 50, 60, 70, and 80 are composed of the detecting unit 204 and an NMOS transistor N3 shown in FIG. The NMOS transistor N3 realizes the dispatching unit 206 in FIG. 2, and according to the current load capacity of the output transistor, the connection mode with the output transistor is also different, so as to implement an inverter or a transmitter, see The following instructions.

In FIG. 5, the channel width of the PMOS transistor PI1 is large. Therefore, the drain of the NMOS transistor N3 is coupled to the gate of the PMOS transistor PI1. In this way, when the electrostatic discharge occurs, the NMOS transistor N3 is turned on, and the gate of the PMOS transistor PI1 is turned on to turn on the PMOS transistor PI1, thereby assisting in turning on the electrostatic current. In this case, the NMOS transistor N3 is an inverter.

In FIG. 6, the channel width of the NMOS transistor NI2 is large. Therefore, the gate of the NMOS transistor N3 is coupled to the gate of the NMOS transistor NI2. As a result, when an electrostatic discharge occurs, the gate of the NMOS transistor NI2 is turned on to a high voltage level to turn on the NMOS transistor NI2, thereby assisting in turning on the electrostatic current. In this case, the NMOS transistor N3 can be regarded as a transmitter for outputting the detection result DCT to the gate of the NMOS transistor NI2.

In FIG. 7, the channel width of the PMOS transistor PI3 is small. Therefore, the gate of the NMOS transistor N3 is coupled to the gate of the PMOS transistor PI3. As a result, when an electrostatic discharge occurs, the gate of the PMOS transistor PI3 is turned on to a high voltage level. To turn off the PMOS transistor PI3, thereby blocking the electrostatic current. In this case, the NMOS transistor N3 can be regarded as a transmitter for outputting the detection result DCT to the PMOS transistor PI3.

In FIG. 8, the channel width of the NMOS transistor NI4 is small. Therefore, the drain of the NMOS transistor N3 is coupled to the gate of the NMOS transistor NI4. In this way, when the electrostatic discharge occurs, the NMOS transistor N3 is turned on, and the gate of the NMOS transistor NI4 is turned to the ground to turn off the NMOS transistor NI4, thereby preventing the NMOS transistor NI4 from being destroyed by the electrostatic current flowing. . In this case, the NMOS transistor N3 can be regarded as an inverter.

According to the fifth to eighth figures, according to the output transistor current load capacity, the NMOS transistor N3 can be a transmitter or an inverter, so that when the electrostatic discharge occurs, the PMOS transistor having a larger channel width and The NMOS transistor is turned on, and the PMOS transistor or NMOS transistor having a small channel width is turned off. In this way, the electrostatic current can be effectively conducted to the ground and the transistor can be protected from damage.

In the prior art, when the integrated circuit is not turned on, the NMOS transistor and the PMOS transistor system in the output buffer unit are in an indeterminate state, and thus the current may be turned on to cause permanent damage. In contrast, the present invention can control the opening or closing of a specific transistor when the electrostatic discharge occurs to achieve the purpose of diverting the electrostatic discharge current or protecting the transistor according to the current load capacity of the output buffer unit.

It is worth noting that since the present invention is directed to the characteristics of each output buffer unit, each output buffer unit is turned "on" or "off". When the output buffer unit is a large-channel transistor and can be used to conduct an electrostatic current, the clamp diode or diode-connected at the transistor of the large-channel transistor is connected. The transistor can be laid out in a smaller area to reduce the wafer area. In addition, since the output buffer unit can share the power clamp transistor to conduct the electrostatic current, the electrostatic protection capability is better. When the output buffer unit channel is small, the output buffer unit is turned off. Therefore, the present invention can reduce the required wafer area while increasing electrostatic protection.

In summary, the present invention controls each output buffer unit to generate a current buffering unit with a better current conducting capability to conduct current caused by the pulse signal to the ground end and turn off the current conduction when the electrostatic discharge occurs. A weaker output buffer unit to avoid permanent damage to the circuit caused by electrostatic discharge. Therefore, the present invention can effectively conduct an electrostatic current to the ground to avoid damage to other components.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 20, 50, 60, 70, 80‧‧ ‧ integrated circuits

100, 204‧‧‧Detection unit

102, 200‧‧‧ core circuits

106‧‧‧current switch

202‧‧‧Electrostatic discharge protection device

206‧‧‧Distribution unit

P1, P2, PI1, PI2, PI3, PI4‧‧‧ PMOS transistor

N1, N2, N3, NI1, NI2, NI3, NI4‧‧‧ NMOS transistors

R1, RS‧‧‧ resistance

C1‧‧‧ capacitor

D1, D2‧‧‧ diode

GND_CH‧‧‧Terminal

PWR_CH‧‧‧Power Channel

OB_1~OB_n‧‧‧Output buffer unit

DCT‧‧‧Detection results

30‧‧‧Process

300, 302, 304, 306‧‧ steps

Fig. 1 is a schematic view showing a conventional integrated circuit having an electrostatic discharge protection function.

FIG. 2 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

Figure 3 is a schematic diagram of an electrostatic discharge protection process for an integrated circuit of Figure 2.

Fig. 4 is a view showing a detecting unit used in one of the integrated circuits of Fig. 2.

FIG. 5 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

Figure 6 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

20‧‧‧ integrated circuit

204‧‧‧Detection unit

200‧‧‧ core circuit

202‧‧‧Electrostatic discharge protection device

206‧‧‧Distribution unit

GND_CH‧‧‧Terminal

PWR_CH‧‧‧Power Channel

OB_1~OB_n‧‧‧Output buffer unit

DCT‧‧‧Detection results

Claims (24)

A method for improving electrostatic discharge protection in an integrated circuit, comprising: detecting a power signal of a power channel of the integrated circuit to generate a detection result; and displaying the power channel in the detection result When the power signal includes a pulse signal, respectively controlling the output condition of the plurality of output buffer units of the integrated circuit to conduct the current caused by the pulse signal to a ground end; wherein the power channel is displayed in the detection result The power signal includes the pulse signal respectively controlling the output of the plurality of output buffer units of the integrated circuit, and controlling the output of each output buffer unit according to the current load capacity of the plurality of output buffer units. The method of claim 1, wherein the output of each of the output buffer units is controlled according to a current load capacity of the plurality of output buffer units, and the current load capacity of the output buffer unit of the plurality of output buffer units is high. The output function of the output buffer unit is activated during a preset condition. The method of claim 1, wherein the output of each of the output buffer units is controlled according to the current load capacity of the plurality of output buffer units, and the current load capacity of the output buffer unit of one of the plurality of output buffer units is low. The output function of the output buffer unit is turned off during a preset condition. An electrostatic discharge protection device for an integrated circuit, comprising: a detection unit for detecting a power signal of a power channel of the integrated circuit to generate a detection result; and a dispatching unit coupled to the detecting unit for displaying the detection result When the power signal of the power channel includes a pulse signal, respectively controlling the output of the plurality of output buffer units of the integrated circuit to conduct current caused by the pulse signal to a ground; wherein the dispatching unit is used When the detection result shows that the power signal of the power channel includes the pulse signal, the output of each output buffer unit is controlled according to the current load capacity of the plurality of output buffer units. The electrostatic discharge protection device of claim 4, wherein the detecting unit comprises: a switch comprising a first end coupled to the power channel, a second end coupled to the ground end, and a third end And a fourth end coupled to the dispatching unit, configured to control the signal connection of the first end to the fourth end according to the voltage difference between the first end and the third end to generate the detection result; a resistor coupled between the first end and the third end of the switch; and a capacitor coupled between the third end and the second end of the switch. The electrostatic discharge protection device of claim 5, wherein the switch comprises: a P-type transistor, a drain is coupled to the fourth end, a gate is coupled to the third end, and a source a pole is coupled to the first end; and an N-type transistor having a drain coupled to the fourth end, a gate coupled to the The third end, and a source are coupled to the second end. The electrostatic discharge protection device of claim 6, wherein the P-type electro-crystal system turns on the signal from the first end to the fourth end when a voltage difference between the first end and the third end is greater than a threshold voltage Link to generate the detection result. The electrostatic discharge protection device of claim 4, wherein the dispatching unit activates one of the plurality of output buffer units, the first output buffer unit, when the detection result indicates that the power signal of the power channel includes the pulse signal The output function, the current load capacity of the first output buffer unit is higher than a preset condition. The electrostatic discharge protection device of claim 8, wherein the first output buffer unit is a P-type transistor, and the dispatch unit is an inverter for outputting an inverted result of the detection result to the P The gate of a transistor. The electrostatic discharge protection device of claim 8, wherein the first output buffer unit is an N-type transistor, and the dispatch unit is a transmitter for outputting the detection result to the gate of the N-type transistor. . The electrostatic discharge protection device of claim 4, wherein when the detection result indicates that the power signal of the power channel includes the pulse signal, the dispatching unit turns off one of the plurality of output buffer units and the second output buffer unit The output function, the current output capability of the second output buffer unit is lower than a preset condition. The electrostatic discharge protection device of claim 11, wherein the second output buffer unit is a P-type transistor, and the dispatch unit is a transmitter for outputting the detection result to the gate of the P-type transistor. . The electrostatic discharge protection device of claim 11, wherein the second output buffer unit is an N-type transistor, and the dispatch unit is an inverter for outputting an inverse result of the detection result to the N The gate of a transistor. An integrated circuit for improving electrostatic discharge protection includes: a power supply channel for providing a power signal; a core circuit for generating a plurality of signal processing results; and a plurality of output buffer units coupled to the core circuit, And the method for detecting the power signal of the power channel to generate a detection result; And a dispatching unit coupled to the detecting unit and the plurality of output buffering units for controlling the output of the plurality of output buffering units when the power signal of the power channel includes a pulse signal In the case, the current caused by the pulse signal is conducted to a ground end. The integrated circuit of claim 14, wherein the detecting unit comprises: a switch includes a first end coupled to the power channel, a second end coupled to the ground end, a third end, and a fourth end coupled to the dispatching unit for a voltage difference to the third end, the signal connection of the first end to the fourth end is controlled to generate the detection result; a resistor is coupled between the first end and the third end of the switch; And a capacitor coupled between the third end of the switch and the second end. The integrated circuit of claim 15, wherein the switch comprises: a P-type transistor, a drain is coupled to the fourth end, a gate is coupled to the third end, and a source The first end is coupled to the first end; and an N-type transistor has a drain coupled to the fourth end, a gate coupled to the third end, and a source coupled to the second end. The integrated circuit of claim 16, wherein the P-type electro-crystal system turns on the signal connection of the first end to the fourth end when a voltage difference between the first end and the third end is greater than a threshold voltage To generate the detection result. The integrated circuit of claim 14, wherein the dispatching unit is configured to display, according to the detection result, the power signal of the power channel includes the pulse signal, according to the current load capacity of the plurality of output buffer units, respectively Control the output of each output buffer unit. The integrated circuit of claim 18, wherein the power is displayed in the detection result When the power signal of the channel includes the pulse signal, the dispatching unit activates an output function of the first output buffer unit of the plurality of output buffer units, and the current load capability of the first output buffer unit is higher than a preset condition. The integrated circuit of claim 19, wherein the first output buffer unit is a P-type transistor, and the dispatch unit is an inverter for outputting an inverted result of the detection result to the P-type The gate of the transistor. The integrated circuit of claim 19, wherein the first output buffer unit is an N-type transistor, and the dispatch unit is a transmitter for outputting the detection result to the gate of the N-type transistor. The integrated circuit of claim 18, wherein when the detection result indicates that the power signal of the power channel includes the pulse signal, the dispatching unit turns off the second output buffer unit of the plurality of output buffer units. The output function, the current output capability of the second output buffer unit is lower than a preset condition. The integrated circuit of claim 22, wherein the second output buffer unit is a P-type transistor, and the dispatch unit is a transmitter for outputting the detection result to the gate of the P-type transistor. The integrated circuit of claim 22, wherein the second output buffer unit is an N-type transistor, and the dispatch unit is an inverter for outputting the detection result. One of the inverse results is to the gate of the N-type transistor.