TWI455435B - Esd protection circuit, bias circuit and electronic apparatus - Google Patents

Description

Electrostatic discharge protection circuit, bias circuit and electronic device

The present invention relates to an electrostatic discharge protection circuit, and more particularly to a discharge channel that automatically turns on an electrostatic discharge protection circuit to rapidly discharge a bias circuit potential to a ground potential when the bias circuit is turned off.

Generally, in the design of the integrated circuit, the power management inside the integrated circuit often uses a Linear Low-dropout Regulator (LDO), and at the same time, in order to compensate the stability of the low-dropout regulator, it will be at the output. A capacitive component with a large capacitance value is attached. However, in the integrated circuit, the capacitive component occupies a considerable area, so most of them will choose to place the compensation capacitor on the outside of the integrated circuit, that is, on the printed circuit board.

Therefore, the output voltage terminal of the internal low-dropout regulator of the integrated circuit must be connected to the package pin through a pad via a bond wire to establish a connection relationship with the capacitor on the printed circuit board. Among them, the pad must be designed with Electrostatic discharge (ESD) protection to prevent electrostatic breakdown of the low-dropout regulator inside the integrated circuit. In general, the design of ESD protection must be in a high-impedance mode under normal operation, but it can provide a low-resistance ESD path when subjected to electrostatic bombardment to avoid the instantaneous large charge of the integrated circuit. The voltage (such as the kilovolt level) causes damage.

Please refer to FIG. 1A. FIG. 1A is a schematic circuit diagram of a conventional bias circuit. As shown in Figure 1A. The conventional bias circuit 10 includes a low dropout regulator 12 and an electrostatic discharge protection circuit 14, wherein the electrostatic discharge protection circuit 14 is coupled to the low dropout regulator 12. The low dropout regulator 12 includes an amplifier OP', a P-type transistor The body MP' and the feedback resistors R1' and R2'. The compensation capacitor CL' outside the wafer is connected to the drain of the P-type transistor MP' and the feedback resistor R1'. The negative input of the amplifier OP' receives a reference voltage VREF', and the positive input of the amplifier OP' receives the feedback voltage VF'. The source of the P-type transistor MP' receives the input voltage VIN'.

Since the ESD protection circuit 14 only acts when subjected to electrostatic bombardment, when the low dropout regulator 12 is turned off from normal operation, the charge stored on the load capacitor CL will only pass through the feedback resistors R1', R2'. The series connected paths are discharged to ground without flowing to the electrostatic discharge protection circuit 14. Generally, in order to save power of the low-dropout regulator 12 circuit, the resistance values of the feedback resistors R1 and R2 are designed to be in the kilo-ohm (kΩ) class, so that the low-dropout regulator 12 can achieve a lower static loss current (Quiescent Current). ). Therefore, when charge is discharged from the load capacitance CL' of the μF stage to the ground via the R1' and R2' resistances of the kΩ stage, it may take several tens of seconds or more to completely discharge the electricity.

Therefore, if the low voltage drop regulator 12 is intended to be turned off from normal operation, the output voltage VOUT can be quickly discharged to ground, usually with the addition of a discharge path.

Please refer to FIG. 1B. FIG. 1B is a schematic diagram of another conventional bias circuit. As shown in Fig. 1B, unlike Fig. 1A, the additional discharge path in Fig. 1B is composed of a resistor R3' (ohm level) and an N-type transistor MN'. The gate of the N-type transistor MN' receives a switching signal LDO_enb opposite to the enable signal LDO_en of the low-dropout regulator. Therefore, when the low dropout regulator 12 is operating normally, the N-type transistor MN' is turned off. When the low dropout regulator 12 is turned off from the normal operating state, the N-type transistor MN' is turned on to form a discharge path, so that the charge stored on the load capacitor CL' can be quickly passed through the resistor R3'. Discharge to the ground.

In FIG. 1B, the smaller the resistance value of the resistor R3' is, the larger the instantaneous discharge current is, the faster the discharge speed is. However, since the pin is directly connected to the outside, it is easily subjected to electrostatic bombardment, and is protected by the electrostatic discharge protection circuit. In design considerations, the resistance of R3 must be increased to increase the resistance of electrostatic bombardment. However, this design not only increases the layout area, but also reduces the speed of charge discharge on the load capacitance CL'.

Embodiments of the present invention provide an electrostatic discharge protection circuit including a clamping unit, a trigger unit, and a control unit. The clamping unit is coupled between the positive power line and the negative power line. The trigger unit has an input end and an output end. The trigger unit is coupled to the negative power line and the reference voltage, and the output end is coupled to the clamp unit and used to trigger the clamp unit. The control unit is coupled to the positive power line, the negative power line and the input end of the trigger unit, and the control unit receives the variable voltage enable signal to trigger the trigger unit, and thereby determines whether the current discharge channel of the clamp unit is turned on or off, wherein When the voltage-variable enable signal is at a low voltage level, the trigger unit turns on the current discharge channel of the clamp unit.

Embodiments of the present invention provide a bias circuit that includes a voltage conversion circuit and an electrostatic discharge protection circuit. The voltage conversion circuit is configured to convert the received input voltage into an output voltage, wherein the output voltage is stored in the load capacitor. The electrostatic discharge protection circuit is electrically connected to the output voltage, and the electrostatic discharge protection circuit receives and determines the opening or closing of the internal current discharge channel according to the variable voltage enable signal. When the voltage conversion enable signal is at a low voltage level, the bias circuit is in a closed state, and the electrostatic discharge protection circuit is turned on. The discharge channel is discharged, and a discharge current flows from the load capacitor into the current discharge channel to release the charge on the load capacitor.

In one of the embodiments of the invention, the control unit includes a control resistor and a control capacitor. One end of the control resistor is electrically connected to the positive power line, and the other end of the control resistor receives the variable voltage enable signal. One end of the control capacitor is electrically connected to the other end of the control resistor, and the other end of the control capacitor is electrically connected to the ground voltage.

In one embodiment of the invention, the trigger unit includes a P-type trigger transistor and an N-type trigger transistor. The gate of the P-type trigger transistor is electrically connected to the other end of the third resistor, and the source of the P-type trigger transistor is electrically connected to the reference voltage for discharging the charge on the load capacitor when the current discharge channel is turned on. . The gate of the N-type trigger transistor is electrically connected to the other end of the third resistor, the drain of the N-type trigger transistor is electrically connected to the drain of the second P-type transistor, and the source polarity of the N-type trigger transistor Connect the negative power cord.

In one of the embodiments of the invention, the clamping unit comprises an N-type clamped transistor. The gate of the N-type clamp transistor is electrically connected to the drain of the N-type trigger transistor, the drain of the N-type clamp transistor is electrically connected to the output capacitor, and the source of the N-type clamp transistor is electrically connected to the negative power supply line. The P-type trigger transistor and the N-type trigger transistor form an inverter. When the voltage-varying enable signal is at a high voltage level, the P-type trigger transistor is turned off and the N-type trigger transistor is turned on, and the N-type clamp transistor is turned on, and the N-type clamp transistor is turned on. The gate receives the voltage of the negative power line to turn off the current discharge channel. When the voltage conversion enable signal is at a low voltage level, the P-type trigger transistor is turned on and the N-type trigger transistor is turned off, and the N-type clamp transistor is turned off. The gate receives the reference voltage to turn on the current discharge channel.

In one embodiment of the invention, the ESD protection circuit further includes a positioning diode. The anode of the positioning diode is electrically connected to the positive power line, The cathode of the diode is electrically connected to the source of the P-type trigger transistor, and the positioning diode is used to determine the voltage level of the source of the P-type trigger transistor. In one embodiment of the present invention, when the voltage transformation enable signal is at a high voltage level, the bias circuit is in a normal working state, and the voltage conversion circuit is enabled, and the electrostatic discharge protection circuit turns off the current discharge channel, and the voltage is converted. The circuit outputs a charging current to the load capacitor to generate an output voltage.

In one embodiment of the invention, the voltage conversion circuit is a low dropout regulator for stepping down the input voltage and stabilizing the output voltage.

In one embodiment of the invention, the low dropout regulator includes a first amplifier, a first P-type transistor, a first resistor, and a second resistor. The negative input of the first amplifier receives the reference voltage, and the output of the first amplifier outputs the first voltage. The gate of the first P-type transistor receives the first voltage, the source of the first P-type transistor is electrically connected to the input voltage, and the drain of the first P-type transistor outputs the output voltage. One end of the first resistor is electrically connected to the drain of the first P-type transistor, and the other end of the first resistor outputs a feedback voltage and transmits the feedback voltage to the positive input terminal of the first amplifier. One end of the second resistor is electrically connected to the other end of the first resistor, and the other end of the second resistor is electrically connected to the ground voltage. When the feedback voltage is greater than the reference voltage, the first voltage rises and the current flowing through the first and second resistors decreases, thereby reducing the output voltage. When the feedback voltage is less than the reference voltage, the first voltage drops and flows through the first The current of one and the second resistor rises, thereby increasing the output voltage.

In one embodiment of the invention, the ESD protection circuit includes a clamping unit, a trigger unit and a control unit. The control unit includes a third resistor and a first capacitor. The trigger unit includes a second P-type transistor and a first N-type transistor. The clamping unit includes a second N-type transistor. One end of the third resistor is electrically connected to the drain of the first P-type transistor, and the third The other end of the resistor receives the variable voltage enable signal. One end of the first capacitor is electrically connected to the other end of the third resistor, and the other end of the first capacitor is electrically connected to the ground voltage. The gate of the second P-type transistor is electrically connected to the other end of the third resistor, and the source of the second P-type transistor is electrically connected to the stable second voltage for enabling the load capacitance when the current discharge channel is turned on. The charge on the top is released. The gate of the first N-type transistor is electrically connected to the other end of the third resistor, the drain of the first N-type transistor is electrically connected to the drain of the second P-type transistor, and the source of the first N-type transistor Very electrically connected to the ground voltage. The gate of the second N-type transistor is electrically connected to the drain of the first N-type transistor, the drain of the second N-type transistor is electrically connected to the output voltage, and the source of the second N-type transistor is electrically connected to the ground. Voltage. The second P-type transistor and the first N-type transistor form an inverter. When the voltage-variable enable signal is at a high voltage level, the second P-type transistor is turned off and the first N-type transistor is turned on. The gate of the second N-type transistor receives the ground voltage to turn off the current discharge channel. When the voltage-varying enable signal is at a low voltage level, the second P-type transistor is turned on and the first N-type transistor is turned off. The gate of the second N-type transistor receives a second voltage to turn on the current discharge channel.

In one embodiment of the invention, the ESD protection circuit further includes a first diode. The anode of the first diode is electrically connected to the output voltage, and the cathode of the first diode is electrically connected to the source of the second P-type transistor. When the bias circuit is subjected to electrostatic bombardment, the output voltage rises abnormally. The voltage of the source of the second P-type transistor is the output voltage minus the turn-on voltage of the first diode to maintain the opening of the current discharge channel during the discharge.

In one embodiment of the invention, the electrostatic discharge protection circuit includes a third P-type transistor, a second capacitor, a fourth P-type transistor, a third N-type transistor, and a fourth N-type transistor. Gate receiving change of the third P-type transistor The voltage-energy signal, the source of the third P-type transistor is electrically connected to the output voltage. One end of the second capacitor is electrically connected to the drain of the third P-type transistor, and the other end of the second capacitor is electrically connected to the ground voltage. The gate of the fourth P-type transistor is electrically connected to the drain of the third P-type transistor, and the source of the fourth P-type transistor is electrically connected to the stable third voltage for enabling the current discharge channel to be turned on. The charge on the load capacitor is released. The gate of the third N-type transistor is electrically connected to the drain of the third P-type transistor, and the drain of the third N-type transistor is electrically connected to the drain of the fourth P-type transistor, and the third N-type The source of the crystal is electrically connected to the ground voltage. The gate of the fourth N-type transistor is electrically connected to the drain of the third N-type transistor, the drain of the fourth N-type transistor is electrically connected to the output voltage, and the source of the fourth N-type transistor is electrically connected to the ground. Voltage. Wherein the fourth P-type transistor and the third N-type transistor form an inverter, and when the voltage-varying enable signal is at a high voltage level, the third and fourth P-type transistors are turned off and the third N-type transistor is turned off. Turning on, and the gate of the fourth N-type transistor receives the ground voltage to turn off the current discharge channel. When the voltage-varying enable signal is at a low voltage level, the third and fourth P-type transistors are turned on and the third N The transistor is turned off, and the gate of the fourth N-type transistor receives a third voltage to turn on the current discharge channel.

In one embodiment of the invention, the ESD protection circuit further includes a second diode. The anode of the second diode is electrically connected to the output voltage, and the cathode of the second diode is electrically connected to the source of the fourth P-type transistor. When the bias circuit is subjected to electrostatic bombardment, the output voltage rises abnormally. The voltage of the source of the fourth P-type transistor is the output voltage minus the turn-on voltage of the second diode to maintain the opening of the current discharge channel during the discharge.

An embodiment of the present invention further provides an electronic device, where the electronic device includes a bias circuit and a load, wherein the load is electrically connected to the bias circuit to receive The output voltage. The bias circuit includes a voltage conversion circuit and an electrostatic discharge protection circuit. The voltage conversion circuit is configured to convert the received input voltage into an output voltage, wherein the output voltage is stored in the load capacitor. The electrostatic discharge protection circuit is electrically connected to the output voltage, and the electrostatic discharge protection circuit receives and determines the opening or closing of the internal current discharge channel according to the variable voltage enable signal. When the voltage-varying enable signal is at a low voltage level, the bias circuit is in a closed state, and the electrostatic discharge protection circuit turns on the current discharge channel, and the discharge current flows from the load capacitor into the current discharge channel to release the charge on the load capacitor. .

In summary, the bias circuit and the electronic device are provided in the embodiment of the present invention. When the voltage-varying enable signal is at a low voltage level, the bias circuit is turned off from the normal working state, and the electrostatic discharge protection circuit is forcibly turned on. The current discharge channel enables the discharge current to flow from the load capacitor into the current discharge channel. Accordingly, the present disclosure can not only reduce the discharge time of the load capacitor without increasing the additional layout area, but also reduce the cost of the overall circuit and improve the antistatic capability of the bias circuit.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Specifically, provide such exemplary The present invention is intended to be thorough and complete, and the scope of the inventive concept will be fully conveyed by those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

[Embodiment of Electrostatic Discharge Protection Circuit]

Please refer to FIG. 2A. FIG. 2A is a block diagram of an ESD protection circuit according to an embodiment of the present invention. In the present embodiment, the electrostatic discharge protection circuit 200 includes a control unit 210, a trigger unit 220, and a clamping unit 230. The clamping unit 230 is coupled between the positive power line VDD and the negative power line VSS. The triggering unit 220 has an input terminal and an output terminal. The triggering unit 220 is coupled to the negative power supply line VSS and the reference voltage VR, and the output end of the triggering unit 220 is coupled to the clamping unit 230 for triggering the clamping unit 230. The control unit 210 is coupled to the positive power line VDD, the negative power line VSS, and the input end of the trigger unit 220. The control unit 210 receives the variable voltage enable signal ENS and triggers the trigger unit 220 according to the control signal CS, and thereby determines whether the current discharge channel in the clamp unit 230 is turned on or off.

In one embodiment, the positive power supply line VDD of the ESD protection circuit 200 is coupled to other circuit blocks (not shown in FIG. 2A), and other circuit blocks generate an output voltage at the output capacitor C. When the variable voltage enable signal ENS is at a low voltage level (that is, other circuit blocks are turned off in their working states) The control unit 210 transmits the control signal CS to the trigger unit 220 according to the received variable voltage enable signal ENS. Then, the trigger unit 220 turns on the current discharge channel of the clamp unit 230 according to the received control signal CS to release the output voltage on the output capacitor C. On the other hand, when the voltage-varying enable signal ENS is at a high voltage level (that is, other circuit blocks are working normally), the control unit 210 transmits the control signal CS to the trigger unit according to the received variable voltage enable signal ENS. 220. Then, the trigger unit 220 turns off the current discharge channel of the clamp unit 230 according to the received control signal CS to maintain the output voltage on the output capacitor C. It is worth mentioning that in an embodiment, the transformer enable signal ENS is equal to the control signal CS.

[Another embodiment of an electrostatic discharge protection circuit]

Please refer to FIG. 2B. FIG. 2B is a block diagram of an ESD protection circuit according to an embodiment of the present invention. Different from the above embodiment of FIG. 2A, the control unit 210 includes a control resistor R and a control capacitor TC. The trigger unit 220 includes a P-type trigger transistor MPT and an N-type trigger transistor MNT. The clamping unit 230 includes an N-type clamp transistor MNC.

One end of the control resistor R is electrically connected to the positive power supply line VDD, and the other end of the control resistor R receives the variable voltage enable signal ENS. One end of the control capacitor TC is electrically connected to the other end of the control resistor R, and the other end of the control capacitor TC is electrically connected to the negative power line VSS. The gate of the P-type trigger transistor MPT is electrically connected to the other end of the control resistor R. The source of the P-type trigger transistor MPT is electrically connected to the reference voltage VR for enabling an output capacitor C when the current discharge channel is turned on. The charge on the top is released. The gate of the N-type trigger transistor MNT is electrically connected to the other end of the control resistor R. The drain of the N-type trigger transistor MNT is electrically connected to the drain of the P-type trigger transistor MPT, and the N-type trigger transistor MNT The source is electrically connected to the negative power line VSS. N-type clamp transistor The gate of the MNC is electrically connected to the drain of the N-type trigger transistor MNT, the drain of the N-type clamp transistor MNC is electrically connected to an output capacitor C, and the source of the N-type clamp transistor MNC is electrically connected to the negative power line. VSS.

In this embodiment, it should be noted that since the gate of the P-type trigger transistor MPT and the N-type trigger transistor MNT are coupled to the variable voltage enable signal ENS, the control signal CS is equal to the variable voltage enable signal ENS. . The positive power supply line VDD of the ESD protection circuit 200 is coupled to other circuit blocks (not shown in FIG. 2B), and the other circuit blocks generate an output voltage when the output capacitor C generates an output voltage. When the voltage level is low (that is, when other circuit blocks are turned off), the P-type trigger transistor MPT and the N-type trigger transistor MNT constituting the inverter are based on the received variable voltage enable signal ENS. The current discharge channel of the N-type clamp transistor MNC is turned on to release the output voltage on the output capacitor C. In other words, the P-type trigger transistor MPT will be turned on and the N-type trigger transistor MNT will be turned off, so that the gate of the N-type clamp transistor MNC is coupled to the reference voltage VR to turn on the current discharge channel.

On the other hand, when the voltage-varying enable signal ENS is at a high voltage level (ie, other circuit blocks are in normal operation), the P-type trigger transistor MPT and the N-type trigger transistor MNT constituting the inverter are based on The variable voltage enable signal ENS is received to turn off the current discharge channel of the N-type clamp transistor MNC to maintain the output voltage on the output capacitor C. In other words, the P-type trigger transistor MPT is turned off and the N-type trigger transistor MNT is turned on, so that the gate of the N-type clamp transistor MNC is coupled to the negative power supply line to turn on the current discharge channel. In an embodiment, the negative power line VSS is coupled to the ground voltage, and is not limited to this embodiment.

In order to explain in more detail the operational flow of the biasing circuit 200 of the present invention, at least one of the various embodiments will be further described below.

In the following various embodiments, portions different from the above-described embodiments of Figs. 2A to 2B will be described, and the remaining omitted portions are the same as those of the above-described embodiments of Figs. 2A to 2B. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Embodiment of Bias Circuit]

Please refer to FIG. 3A. FIG. 3A is a schematic diagram of a bias circuit according to an embodiment of the invention. The bias circuit 300 includes a voltage conversion circuit 310 and an electrostatic discharge protection circuit 320. The ESD protection circuit 320 is electrically connected to the voltage conversion circuit 310. As shown in FIG. 3A, the voltage conversion circuit 310 is configured to convert the received input voltage VIN into an output voltage VOUT, wherein the output voltage VOUT is stored on the load capacitance CL. The electrostatic discharge protection circuit 320 receives and determines the on or off state of the internal current discharge channel based on the variable voltage enable signal ENS. Bias circuit 300 can be a bandgap reference circuit, or other step-up/down circuit.

In an embodiment of the present disclosure, when the voltage-variable enable signal ENS is at a low voltage level, the bias circuit 300 is in a closed state, and the electrostatic discharge protection circuit 320 turns on the current discharge channel. Moreover, the discharge current flows from the load capacitance CL into the current discharge channel inside the electrostatic discharge protection circuit 320 to quickly release the charge on the load capacitance CL. In a preferred embodiment, the charge of the load capacitance CL can be completely released. On the other hand, when the voltage-varying enable signal ENS is at a high voltage level, the bias circuit 300 is in a normal operating state, and the voltage conversion circuit 310 is enabled, and the electrostatic discharge protection circuit 320 The current discharge channel is turned off, thereby causing the voltage conversion circuit 310 to output a charging current to the load capacitance CL to generate a stable output voltage VOUT.

In order to explain the disclosure more clearly, the following will advance from three states. The detailed operation of the bias circuit 300 is taught step by step, wherein the three states indicate the operation of the bias circuit 300 from the completion of manufacture to the process of mounting on the circuit board (not powered) and the bias circuit 300 being mounted on the circuit board. Status and shutdown status.

Please refer to FIG. 3B. FIG. 3B is a schematic diagram of an unpowered bias circuit according to an embodiment of the invention. When the bias circuit 300 is completed from the completion of manufacture to the installation of the circuit board (ie, not powered), "unpowered" is defined as having no input voltage VIN, reference voltage VREF and variable voltage enable signal ENS . The electrostatic discharge protection circuit 320 is turned on when the output voltage VOUT of the output terminal rises abnormally due to the possibility that the human body contact pin (pin) or other factors contact the pin position, and the trigger condition of the electrostatic discharge protection circuit 320 is reached. An electrostatic discharge channel causes the electrostatic current IES to be directly directed to the ground via the electrostatic discharge channel to avoid damage to internal components of the voltage conversion circuit 310 and to reduce the functionality of the overall circuit.

On the other hand, please refer to FIG. 3C, which is a schematic diagram of a bias circuit in a normal operating state according to an embodiment of the invention. When the bias circuit 300 is mounted on the circuit board, the voltage conversion circuit 310 and the electrostatic discharge protection circuit 320 receive and are in a normal operating state according to a high voltage level variable voltage enable signal ENS. Next, the voltage conversion circuit 310 converts the input voltage VIN into an output voltage VOUT and outputs it to the next-stage circuit block (not shown in FIG. 2B). That is, the voltage conversion circuit 310 outputs a charging current IC to the load capacitance CL to store the charge to output a substantially stable output voltage VOUT to provide the next-stage circuit block use. It should be noted that at the same time, the ESD protection circuit 320 turns off the current discharge channel according to the variable voltage enable signal ENS to ensure that the charging current IC does not flow to the ground through the current discharge channel, thereby achieving the bias current. The output voltage VOUT of the predetermined output of the path 300.

Finally, please refer to FIG. 3D, which is a workmanship according to an embodiment of the present invention. A schematic diagram of a transient bias circuit that switches state to a closed state. When the bias circuit 300 is mounted on the circuit board, the voltage conversion circuit 310 and the electrostatic discharge protection circuit 320 receive and switch from the normal operating state to the closed state according to a low voltage level variable voltage enable signal ENS. At this time, the voltage conversion circuit 310 is disabled to stop outputting the charging current to the load capacitance CL, and the electrostatic discharge protection circuit 320 generates a current discharge channel according to the variable voltage enable signal ENS, thereby being capable of guiding the discharge. The current ID flows from the load capacitance CL to the current discharge channel inside the electrostatic discharge protection circuit 320 to quickly discharge the charge on the load capacitance CL. Therefore, when the bias circuit 300 is switched from the normal operating state to the off state, the output voltage VOUT can quickly drop to near zero voltage without affecting the operation of the next stage circuit. In another embodiment, the output voltage VOUT can be quickly dropped to zero voltage, which is not limited to this embodiment.

In order to explain in more detail the operational flow of the biasing circuit 300 of the present invention, at least one of the various embodiments will be further described below.

In the following various embodiments, portions different from the above-described embodiments of Figs. 3A to 3D will be described, and the remaining omitted portions are the same as those of the above-described embodiments of Figs. 3A to 3D. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Another embodiment of the bias circuit]

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a detailed circuit of a bias circuit according to another embodiment of the present invention. As shown in FIG. 4, in the embodiment, the voltage conversion circuit is a Low Dropout Regulator (LDO) for stepping down the input voltage VIN and outputting a stable output voltage VOUT. In other embodiments, the voltage conversion circuit may be another buck circuit or a boost circuit, and is not limited to this embodiment. For convenience of explanation, the following description will teach the bias voltage with the low dropout regulator 410 as an example. The overall operation of the road. The low dropout regulator 410 includes a first amplifier OP, a first P-type transistor MP1, a first resistor R1, and a second resistor R2. The electrostatic discharge protection circuit 200 includes a clamping unit 230, a trigger unit 220, and a control unit 210. The control unit 210 includes a third resistor R3 and a first capacitor C1. The trigger unit 220 includes a second P-type transistor MP2 and a first N-type transistor MN1. The clamping unit 230 includes a second N-type transistor MN2.

The negative input terminal T1 of the first amplifier OP receives the reference voltage VREF, and the output terminal of the second amplifier OP outputs the first voltage V1. The gate of the first P-type transistor MP1 receives the first voltage V1, the source of the first P-type transistor MP1 is electrically connected to the input voltage VIN, and the drain of the first P-type transistor MP1 outputs an output voltage VOUT. One end of the first resistor R1 is electrically connected to the drain of the first P-type transistor MP1, and the other end of the first resistor R1 outputs a feedback voltage VF and transmits the feedback voltage VF to the positive input terminal T2 of the first amplifier OP. . One end of the second resistor R2 is electrically connected to the other end of the first resistor R1, and the other end of the second resistor R2 is electrically connected to the ground voltage GND. One end of the third resistor R3 is electrically connected to the drain of the first P-type transistor MP1, and the other end of the third resistor R3 receives the variable voltage enable signal ENS. One end of the first capacitor C1 is electrically connected to the other end of the third resistor R3, and the other end of the first capacitor C1 is electrically connected to the ground voltage GND. The gate of the second P-type transistor MP2 is electrically connected to the other end of the third resistor R3, and the source of the second P-type transistor MP2 is electrically connected to the stable second voltage V2. The gate of the first N-type transistor MN1 is electrically connected to the other end of the third resistor R3, and the drain of the first N-type transistor MN1 is electrically connected to the drain of the second P-type transistor MP2, and the first N-type The source of the crystal MN1 is electrically connected to the ground voltage GND. The gate of the second N-type transistor MN2 is electrically connected to the drain of the first N-type transistor MN1, and the drain of the second N-type transistor MN2 is electrically connected to the output voltage VOUT, the second The source of the N-type transistor MN2 is electrically connected to the ground voltage GND.

The following is a detailed description of the operation of the bias circuit 400 in the embodiment of Fig. 4.

Referring to FIG. 4, after the bias circuit 400 is mounted on the circuit board, the low dropout regulator 410 and the ESD protection circuit 200 receive and operate normally according to a high voltage level variable voltage enable signal ENS. status. The source of the first P-type transistor MP1 is coupled to the input voltage VIN to receive the input voltage VIN, and the magnitude of the output voltage VOUT is determined by the reference voltage VREF, the values of the first resistor R1 and the second resistor R2. Further, since the configuration of the first amplifier OP is a virtual short circuit relationship, the feedback voltage VF is substantially equal to the reference voltage VREF, so the designer can design according to the circuit design requirement or the actual application requirement according to the equation (1). The size of the predetermined output voltage VOUT.

VOUT=[(R1+R2)/R2]x VREF Equation (1)

When the feedback voltage VF is greater than the reference voltage VREF, the first voltage V1 output by the first amplifier OP will rise, and the gate-source voltage of the first P-type transistor MP1 will decrease, thereby causing the first flow. The current I1 of the resistor R1 and the second resistor R2 drops. Therefore, according to the relationship of the current drop voltage drop (IR drop), the output voltage VOUT will decrease, which in turn causes the feedback voltage VF to drop until the feedback voltage VF is less than the reference voltage VREF. When the feedback voltage VF is less than the reference voltage VREF, the first voltage V1 output by the first amplifier OP is decreased, so that the gate-source voltage of the first P-type transistor MP1 rises, thereby causing the first flow. The current I1 of the resistor R1 and the second resistor R2 rises. Therefore, according to the relationship of the current drop (IR drop), the output voltage VOUT rises, which causes the feedback voltage VF to rise until the feedback voltage VF is less than the reference voltage VREF. Negative feedback according to the above (negative feedback) mechanism, the low dropout regulator 410 can provide a stable output voltage VOUT, and the designer can further determine the magnitude of the output voltage VOUT according to the reference voltage VREF, the values of the first resistor R1 and the second resistor R2.

At this time, since the node n1 in the electrostatic discharge protection circuit 200 receives the variable voltage enable signal ENS of the high voltage level, the reverse phase of the second P-type transistor MP2 and the first N-type transistor MN1 is formed. The inverter also receives the high voltage level variable voltage enable signal ENS. Therefore, the second P-type transistor MP2 will be in a closed state, and the first N-type transistor MN1 will be in an on state, thereby transmitting a signal of the inverter outputting a low voltage level to the second N-type transistor MN2. That is, the gate of the second N-type transistor MN2 is received or electrically connected to the ground voltage GND, so that the second N-type transistor MN2 is in the off state. It should be noted that in the present embodiment, the second N-type transistor MN2 serves as a current discharge channel in the ESD protection circuit 200. Therefore, if the second N-type transistor MN2 is in the off state, the ESD protection circuit 200 The current discharge channel in the middle is also in the off state. Therefore, when the low-dropout regulator 410 outputs a charging current IC to the load capacitor CL to provide the output voltage VOUT to the next-stage circuit block (not shown in FIG. 3), the charging current IC does not flow through the current discharging channel. The phenomenon of leakage current is generated.

On the other hand, when the low dropout regulator 410 and the ESD protection circuit 200 receive a low voltage level variable voltage enable signal ENS, the low dropout regulator 410 is disabled and switched from the normal operating state to Disabled. The node n1 in the ESD protection circuit 200, after receiving the voltage-varying enable signal ENS of the low voltage level, causes the second P-type transistor MP2 in the inverter to be in an on state, the first N-type transistor MN1 Is off. Then, invert The device outputs a second voltage V2 to the gate of the second N-type transistor MN2 to turn on the second N-type transistor MN2, thereby turning on the current discharge channel in the ESD protection circuit 200. Then, the discharge current ID flows from the load capacitor CL to the ground through the current discharge channel, that is, the charge on the load capacitor CL is quickly discharged from the current discharge channel inside the electrostatic discharge protection circuit 200, so that the output voltage VOUT is fast. Drop, and avoid affecting the actions of other circuits. In an embodiment, the overall channel width of the second N-type transistor MN2 can be increased to reduce the conduction group, thereby improving the discharge efficiency.

It is worth mentioning that, in this embodiment, since the gate of the second N-type transistor MN2 is electrically connected to the stable second voltage V2, the output voltage VOUT is continuously in the transient state of the circuit discharge. Falling, but the gate voltage of the second N-type transistor MN2 will still maintain a stable second voltage V2. That is, the gate-source voltage across the second N-type transistor MN2 maintains a stable second voltage V2. Therefore, compared with the source of the second P-type transistor MP2 in the prior art, the source is coupled to the output voltage VOUT, and the disclosure helps to quickly release the charge on the load capacitor CL, and can effectively increase the discharge. speed. Incidentally, the second voltage V2 may be a system voltage or another stable voltage.

In order to understand the disclosure more clearly, please refer to FIG. 5A and FIG. 5B at the same time. FIG. 5A is a voltage time waveform diagram of a discharge waveform of a conventional bias circuit. Fig. 5B is a voltage time waveform diagram of a discharge waveform corresponding to the bias circuit of Fig. 3D. As can be seen from FIG. 5A and FIG. 5B, the conventional bias circuit discharges the voltage of the load capacitor from 90% to 10%, and takes about 500 microseconds. However, in the present disclosure, the bias circuit 400 sets the voltage of the load capacitor CL from It takes only 2 microseconds to discharge from 90% to 10%. Therefore, the present disclosure can greatly reduce the discharge time compared to the prior art, and does not require an additional layout area.

In addition, please refer to FIG. 6. FIG. 6 is a detailed diagram of an unpowered bias circuit according to another embodiment of the present invention. The electrostatic discharge protection circuit 200 further includes a first diode D1. The anode of the first diode D1 is electrically connected to the output voltage VOUT, and the cathode of the first diode D1 is electrically connected to the source of the second P-type transistor MP2. In the present embodiment, the first diode D1 is used to determine the voltage level of the source of the second P-type transistor MP2 (when subjected to electrostatic bombardment) before the bias circuit 600 is powered.

When the bias circuit 600 is completed from the completion of manufacture to the installation of the circuit board (ie, no power-on), "unpowered" is defined as having no input voltage VIN, reference voltage VREF and variable voltage enable signal ENS The output voltage VOUT of the output terminal rises abnormally due to the possibility that the human body contacts the pin or other factors to contact the pin. When the trigger condition of the electrostatic discharge protection circuit 200 is reached, the electrostatic discharge is performed. The protection circuit 200 opens an electrostatic discharge channel such that the electrostatic current IES is directly directed to the ground via the electrostatic discharge channel to avoid damaging the internal components of the low dropout regulator 410 and reducing the overall circuit function. Therefore, when the pin or the output end of the integrated circuit chip is subjected to electrostatic bombardment to cause the output voltage VOUT to rise abnormally, in order to clearly locate the voltage level of the source of the second P-type transistor MP2, the embodiment utilizes The voltage and current characteristics of the first diode D1 are used to position the voltage level of the source of the second P-type transistor MP2 as the output voltage VOUT minus the forward voltage of the first diode D1 to be biased During the discharge process after the circuit 600 is subjected to electrostatic bombardment and the current discharge channel is turned on, the opening of the current discharge channel can be determined and maintained, which helps to guide the electrostatic current IES to the ground.

In detail, since the rise time of the discharge waveform is about 10 nanoseconds in the human body discharge mode, and the voltage rise time of the integrated circuit is about the millisecond level, the resistance of the third resistor R3 and the first capacitor C1 Time constant (RC Constant) is usually designed to be between milliseconds and nanoseconds. Therefore, when the bias circuit 600 is subjected to electrostatic bombardment, the output voltage VOUT will rise abnormally. At this time, the source voltage of the second P-type transistor MP2 is the output voltage VOUT minus the turn-on voltage of the first diode D1. During this transient process, since the voltage of the node n1 is generally at a lower voltage level in the case of the floating connection, the second P-type transistor MP2 is turned on, and the first N-type transistor MN1 is turned off. The gate voltage of the second N-type transistor MN2 is substantially equal to the source voltage of the second P-type transistor MP2. That is, the gate voltage of the second N-type transistor MN2 is the output voltage VOUT minus the turn-on voltage of the first diode D1 to ensure the opening of the second N-type transistor MN2 or the current discharge channel, thereby making the static electricity The current IES can flow to ground via the second N-type transistor MN2.

In order to explain in more detail the operational flow of the biasing circuit of the present invention, at least one of the various embodiments will be further described below.

In the following various embodiments, portions different from the above-described embodiments of Figs. 2 to 6 will be described, and the remaining omitted portions are the same as those of the above-described embodiments of Figs. 2 to 6. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Further embodiment of bias circuit]

Please refer to FIG. 7. FIG. 7 is a detailed circuit diagram of a bias circuit according to still another embodiment of the present invention. Different from the above embodiment of FIG. 4, the third resistor R3 in the ESD protection circuit 200 is replaced by the third P-type transistor MP3 in the present embodiment to improve the overall function of the bias circuit 700. Further, in the embodiment, the electrostatic discharge protection circuit 200 includes a third P-type transistor MP3, a second capacitor C2, a fourth P-type transistor MP4, a third N-type transistor MN3, and a fourth N-type battery. Crystal MN4.

The gate of the third P-type transistor MP3 receives the variable voltage enable signal ENS, The source of the third P-type transistor MP3 is electrically connected to the output voltage VOUT. One end of the second capacitor C2 is electrically connected to the drain of the third P-type transistor MP3, and the other end of the second capacitor C2 is electrically connected to the ground voltage GND. The gate of the fourth P-type transistor MP4 is electrically connected to the drain of the third P-type transistor MP3, and the source of the fourth P-type transistor MP4 is electrically connected to the stable third voltage V3. The gate of the third N-type transistor MN3 is electrically connected to the drain of the third P-type transistor MP3, and the drain of the third N-type transistor MN3 is electrically connected to the drain of the fourth P-type transistor MP4, and the third The source of the N-type transistor MN3 is electrically connected to the ground voltage GND. The gate of the fourth N-type transistor MN4 is electrically connected to the drain of the third N-type transistor MN3, the drain of the fourth N-type transistor MN4 is electrically connected to the output voltage VOUT, and the source of the fourth N-type transistor MN4 The grounding voltage GND is electrically connected.

The following is a detailed description of the operation of the bias circuit 700 in the embodiment of Fig. 7.

Referring to FIG. 7, after the bias circuit 700 is mounted on the circuit board, the low dropout regulator 410 and the electrostatic discharge protection circuit 200 receive and operate normally according to a high voltage level variable voltage enable signal ENS. status. The source of the first P-type transistor MP1 is coupled to the input voltage VIN to receive the input voltage VIN, and the magnitude of the output voltage VOUT is determined by the reference voltage VREF, the values of the first resistor R1 and the second resistor R2. Since the configuration of the first amplifier OP is a virtual short circuit relationship, the feedback voltage VF is substantially equal to the reference voltage VREF, so the designer can design the predetermined output voltage according to the circuit design requirement or the actual application requirement according to the equation (1). The size of VOUT.

When the feedback voltage VF is greater than the reference voltage VREF, the first voltage V1 output by the first amplifier OP rises, so that the first P-type transistor The gate-to-source voltage of MP1 drops, which in turn causes the current I1 flowing through the first resistor R1 and the second resistor R2 to drop. Therefore, according to the relationship of the current drop voltage drop (IR drop), the output voltage VOUT will decrease, which in turn causes the feedback voltage VF to drop until the feedback voltage VF is less than the reference voltage VREF. When the feedback voltage VF is less than the reference voltage VREF, the first voltage V1 output by the first amplifier OP is decreased, so that the gate-source voltage of the first P-type transistor MP1 rises, thereby causing the first flow. The current I1 of the resistor R1 and the second resistor R2 rises. Therefore, according to the relationship of the current drop (IR drop), the output voltage VOUT rises, which causes the feedback voltage VF to rise until the feedback voltage VF is less than the reference voltage VREF. According to the above negative feedback mechanism, the low dropout regulator 410 can provide a stable output voltage VOUT, and the designer can further determine the output according to the reference voltage VREF, the values of the first resistor R1 and the second resistor R2. The magnitude of the voltage VOUT.

At this time, since the node n2 in the electrostatic discharge protection circuit 200 receives the variable voltage enable signal ENS of the high voltage level, the third P-type transistor MP3 is in the off state, so the charge on the second capacitor C2 does not The leakage of the third P-type transistor MP3 affects the voltage level of the node n2, thereby affecting subsequent circuit operations. Then, the inverter formed by the fourth P-type transistor MP4 and the third N-type transistor MN3 simultaneously receives the variable voltage enable signal ENS of the high voltage level. Therefore, the fourth P-type transistor MP4 is in a closed state, and the third N-type transistor MN3 is in an on state, thereby transmitting a signal of the inverter outputting a low voltage level to the fourth N-type transistor MN4. That is, the gate of the fourth N-type transistor MN4 is received or electrically connected to the ground voltage GND, so that the fourth N-type transistor MN4 is in the off state. It is worth noting that in this embodiment The fourth N-type transistor MN4 serves as a current discharge channel in the ESD protection circuit. Therefore, if the fourth N-type transistor MN4 is in the off state, the current discharge channel in the ESD protection circuit 200 is also in the off state. Therefore, when the low-dropout regulator 410 outputs a charging current IC to the load capacitor CL to provide the output voltage VOUT to the next-stage circuit block (not shown in FIG. 6), the charging current IC does not flow through the current discharging channel. The phenomenon of leakage current is generated.

On the other hand, when the low dropout regulator 410 and the ESD protection circuit 200 receive a low voltage level variable voltage enable signal ENS, the low dropout regulator 410 is disabled and switched from the normal operating state to Disabled. After receiving the low voltage level variable voltage enable signal ENS, the node n2 in the ESD protection circuit 200 turns on the third P-type transistor MP3 and causes the fourth P-type transistor MP4 in the inverter. Will be in the on state, the third N-type transistor MN3 will be in the off state. Next, the inverter outputs a third voltage V3 to the gate of the fourth N-type transistor MN4 to turn on the fourth N-type transistor MN4, thereby turning on the current discharge channel in the ESD protection circuit 200. Then, the discharge current ID flows from the load capacitor CL to the ground through the current discharge channel, that is, the charge on the load capacitor CL is quickly discharged from the current discharge channel inside the electrostatic discharge protection circuit 200, so that the output voltage VOUT is fast. Drop, and avoid affecting the actions of other circuits. In an embodiment, the overall channel width of the fourth N-type transistor MN4 can be increased to reduce the on-resistance, thereby improving the discharge efficiency.

It is worth mentioning that, in this embodiment, since the gate and the drain of the fourth N-type transistor MN4 are electrically connected to the stable third voltage V3 and the output voltage VOUT, respectively, the transient in the circuit discharge During the process, the output voltage VOUT will continue to drop, but the gate voltage of the fourth N-type transistor MN4 will remain A stable third voltage V3. That is, the gate-source voltage across the fourth N-type transistor MN4 maintains a stable third voltage V3. Therefore, compared with the source of the fourth P-type transistor MP4 in the prior art, the source is coupled to the output voltage VOUT, and the disclosure helps to quickly release the charge on the load capacitor CL, and can effectively increase the discharge. speed. Incidentally, the third voltage V3 may be a system voltage or other stable voltage.

In addition, please refer to FIG. 8. FIG. 8 is a detailed diagram of an unpowered bias circuit according to still another embodiment of the present invention. The electrostatic discharge protection circuit 200 further includes a second diode D2. The anode of the second diode D2 is electrically connected to the output voltage VOUT, and the cathode of the second diode D2 is electrically connected to the source of the fourth P-type transistor MP4. In this embodiment, the second diode D2 is used to determine the voltage level of the source of the fourth P-type transistor MP4 (when subjected to electrostatic bombardment) before the bias circuit 800 is powered.

When the bias circuit 800 is completed from the completion of manufacture to the installation of the circuit board (ie, no power-on), "unpowered" is defined as having no input voltage VIN, reference voltage VREF, and variable voltage enable signal ENS. The output voltage VOUT of the output terminal rises abnormally due to the possibility that the human body contacts the pin or other factors to contact the pin. When the trigger condition of the electrostatic discharge protection circuit 200 is reached, the electrostatic discharge is performed. The protection circuit 200 opens an electrostatic discharge channel such that the electrostatic current IES is directly directed to the ground via the electrostatic discharge channel to avoid damaging the internal components of the low dropout regulator 410 and reducing the overall circuit function. Therefore, when the pin or output terminal of the integrated circuit chip is subjected to electrostatic bombardment to cause the output voltage VOUT to rise abnormally, in order to clearly locate the voltage level of the source of the fourth P-type transistor MP4, the embodiment utilizes The voltage and current characteristics of the second diode D2 are used to position the voltage level of the source of the fourth P-type transistor MP4 as the output voltage VOUT minus the second diode The forward voltage of the body D2 can determine and maintain the opening of the current discharge channel during the discharge process after the bias circuit 800 is subjected to electrostatic bombardment to turn on the current discharge channel, which helps to guide the electrostatic current IES to the ground. .

In detail, since the rise time of the discharge waveform is about 10 nanoseconds in the human body discharge mode, and the voltage rise time of the integrated circuit is about the millisecond level, the equivalent power of the third P-type transistor MP3 The RC constant with the first capacitor C1 is usually designed to be between milliseconds and nanoseconds, and the equivalent resistance of the third P-type transistor MP3 can be determined according to the geometry or material parameters in the process. Therefore, when the bias circuit 800 is subjected to electrostatic bombardment, the output voltage VOUT will rise abnormally. At this time, the source voltage of the fourth P-type transistor MP4 is the output voltage VOUT minus the turn-on voltage of the second diode D2. During this transient process, since the voltage of the node n2 is generally at a lower voltage level in the case of the floating connection, the fourth P-type transistor MP4 is turned on, and the third N-type transistor MN3 is turned off. The gate voltage of the fourth N-type transistor MN4 is substantially equal to the source voltage of the fourth P-type transistor MP4. That is, the gate voltage of the second N-type transistor MN2 is the output voltage VOUT minus the turn-on voltage of the second diode D2 to ensure the opening of the fourth N-type transistor MN4 or the current discharge channel, thereby making the static electricity The current IES can flow to the ground via the fourth N-type transistor MN4.

[Embodiment of Electronic Apparatus]

Please refer to FIG. 9. FIG. 9 is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device 900 includes a load 920 and a bias circuit 910 electrically coupled to the load 920, wherein the bias circuit 910 receives the input voltage VIN. The bias circuit 910 can be one of the bias circuits 300, 400, 600, 700, and 800 in the above embodiments, and is configured to provide a stable output voltage VOUT to the load 920. The electronic device 900 can be various types of electronic devices, such as Display device, handheld device or mobile device, and the like.

[Possible effects of the examples]

In summary, the bias circuit and the electronic device are provided in the embodiment of the present invention. When the voltage-varying enable signal is at a low voltage level, the bias circuit is turned off from the normal working state, and the electrostatic discharge protection circuit is forcibly turned on. The current discharge channel enables the discharge current to flow from the load capacitor into the current discharge channel. Accordingly, the present disclosure can not only reduce the discharge time of the load capacitor without increasing the additional layout area, but also reduce the cost of the overall circuit and improve the capability of the electrostatic discharge protection circuit.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

10, 20 ‧ ‧ conventional bias circuit

12‧‧‧Low Dropout Regulator

14‧‧‧Electrostatic discharge protection circuit

200‧‧‧Electrostatic discharge protection circuit

210‧‧‧Control unit

220‧‧‧Trigger unit

230‧‧‧Clamping unit

300, 400, 600, 700, 800‧‧‧ bias circuits

310‧‧‧Voltage conversion circuit

320‧‧‧Electrostatic discharge protection circuit

410‧‧‧Low Dropout Regulator

900‧‧‧Electronic devices

910‧‧‧Bias circuit

920‧‧‧load

C‧‧‧ output capacitor

C1‧‧‧first capacitor

C2‧‧‧second capacitor

CL', CL‧‧‧ load capacitance

CS‧‧‧Control signal

D1‧‧‧First Diode

D2‧‧‧ second diode

ENS‧‧‧Transformation enable signal

GND‧‧‧ Grounding voltage

I1‧‧‧ Current

IC‧‧‧Charging current

ID‧‧‧discharge current

IES‧‧‧Electrostatic current

LDO_en‧‧‧ enable signal

LDO_enb‧‧‧ switch signal

MN’‧‧‧N type transistor

MN1‧‧‧First N-type transistor

MN2‧‧‧Second N-type transistor

MN3‧‧‧ Third N-type transistor

MN4‧‧‧4th N-type transistor

MNT‧‧‧N type trigger transistor

MNC‧‧‧N type clamped crystal

MP’‧‧‧P type transistor

MP1‧‧‧First P-type transistor

MP2‧‧‧Second P-type transistor

MP3‧‧‧ Third P-type transistor

MP4‧‧‧4th P-type transistor

MPT‧‧‧P type trigger transistor

N1, n2‧‧‧ nodes

OP’‧‧Amplifier

OP‧‧‧First Amplifier

R‧‧‧Control resistor

R1‧‧‧first resistance

R1'‧‧‧Responsive resistor

R2', R2‧‧‧ second resistor

R3‧‧‧ third resistor

R3’‧‧‧resistance

T1‧‧‧n negative input

T2‧‧‧ positive input

TC‧‧‧Control Capacitor

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

VDD‧‧‧ positive power cord

VSS‧‧‧Negative power cord

VF', VF‧‧‧ feedback voltage

VIN', VIN‧‧‧ input voltage

VR, VREF', VREF‧‧‧ reference voltage

VOUT', VOUT‧‧‧ output voltage

The present invention will be described in detail with reference to the accompanying drawings, in which: FIG. 1A is a circuit diagram of a conventional biasing circuit.

FIG. 1B is a schematic diagram of another conventional bias circuit.

2A is a block diagram of an electrostatic discharge protection circuit in accordance with an embodiment of the present invention.

2B is a block diagram of an ESD protection circuit in accordance with an embodiment of the present invention.

3A is a schematic diagram of a bias circuit in accordance with an embodiment of the present invention.

3B is a schematic diagram of an unpowered bias circuit in accordance with an embodiment of the present invention.

3C is a schematic diagram of a bias circuit in a normal operating state in accordance with an embodiment of the present invention.

3D is a schematic diagram of a transient bias circuit that switches from an active state to a closed state in accordance with an embodiment of the present invention.

4 is a schematic diagram of a detailed circuit of a bias circuit in accordance with another embodiment of the present invention.

FIG. 5A is a voltage time waveform diagram of a discharge waveform of a conventional bias circuit.

Fig. 5B is a voltage time waveform diagram of a discharge waveform corresponding to the bias circuit of Fig. 3D.

6 is a detailed diagram of an unpowered bias circuit in accordance with another embodiment of the present invention.

Figure 7 is a detailed circuit diagram of a bias circuit in accordance with still another embodiment of the present invention.

Figure 8 is a detailed diagram of an unpowered bias circuit in accordance with yet another embodiment of the present invention.

FIG. 9 is a schematic diagram of an electronic device according to an embodiment of the present invention.

200‧‧‧Electrostatic discharge protection circuit

210‧‧‧Control unit

220‧‧‧Trigger unit

230‧‧‧Clamping unit

C‧‧‧ output capacitor

CS‧‧‧Control signal

ENS‧‧‧Transformation enable signal

VR‧‧‧reference voltage

VDD‧‧‧ positive power cord

VSS‧‧‧Negative power cord

Claims (17)

An electrostatic discharge protection circuit includes: a clamping unit coupled between a positive power line and a negative power line; a trigger unit having an input end and an output end, the trigger unit coupled to the negative power line and a a reference voltage, and the output terminal is coupled to the clamping unit and configured to trigger the clamping unit; and a control unit coupled to the positive power line, the negative power line, and the input end of the trigger unit, the control unit receives a variable voltage enable signal to trigger the trigger unit, and thereby determining whether the current discharge channel of one of the clamp units is turned on or off, wherein the trigger unit is turned on when the voltage change enable signal is at a low voltage level The current discharge channel of the clamping unit. The electrostatic discharge protection circuit of claim 1, wherein the control unit comprises: a control resistor, one end of which is electrically connected to the positive power supply line, the other end of which receives the variable voltage enable signal; and a control capacitor One end of the control resistor is electrically connected to one end of the control resistor, and the other end is electrically connected to the negative power line. The electrostatic discharge protection circuit of claim 1, wherein the trigger unit comprises: a P-type trigger transistor, wherein the gate is electrically connected to the other end of the control resistor, and the source is electrically connected to the reference voltage When the current discharge channel is turned on, the charge on a load capacitor can be released; and an N-type trigger transistor is electrically connected to the other end of the control resistor, and the gate is electrically connected. The P-type triggers the drain of the transistor, and the source is electrically connected to the negative power line. The electrostatic discharge protection circuit of claim 3, wherein the clamping unit comprises: an N-type clamped transistor, the gate of which is electrically connected to the drain of the N-type trigger transistor, and the gate is electrically connected An output capacitor, the source of which is electrically connected to the negative power line, wherein the P-type trigger transistor and the N-type trigger transistor form an inverter, and when the variable voltage enable signal is at a high voltage level, The P-type trigger transistor is turned off and the N-type trigger transistor is turned on, and the gate of the N-type clamp transistor receives the voltage of the negative power line to turn off the current discharge channel, when the variable voltage enable signal is low At the voltage level, the P-type trigger transistor is turned on and the N-type trigger transistor is turned off, and the gate of the N-type clamp transistor receives the reference voltage to turn on the current discharge channel. The electrostatic discharge protection circuit of claim 4, further comprising: a positioning diode, wherein the anode is electrically connected to the positive power line, and the cathode is electrically connected to the source of the P-type trigger transistor, The positioning diode is used to determine the voltage level of the source of the P-type trigger transistor. The electrostatic discharge protection circuit of claim 1, wherein the negative power supply line is coupled to a ground voltage. A bias circuit includes: a voltage conversion circuit for converting a received input voltage into an output voltage, wherein the output voltage is stored in a load capacitor; an electrostatic discharge protection circuit electrically connected to the An output voltage, the ESD protection circuit receives and determines whether an internal current discharge channel is turned on or off according to a variable voltage enable signal, wherein when the variable voltage enable signal is a low voltage level, the bias Pressure circuit In an off state, the ESD protection circuit turns on the current discharge channel, and a discharge current flows from the load capacitor into the current discharge channel to release the charge on the load capacitor. The bias circuit of claim 7, wherein when the variable voltage enable signal is at a high voltage level, the bias circuit is in a normal operating state, and the voltage conversion circuit is enabled. The ESD protection circuit turns off the current discharge channel, and the voltage conversion circuit outputs a charging current to the load capacitor to generate the output voltage. The bias circuit of claim 8, wherein the voltage conversion circuit is a low dropout regulator for stepping down the input voltage and stabilizing the output voltage. The bias voltage circuit of claim 9, wherein the low voltage drop regulator comprises: a first amplifier, a negative input terminal receiving a reference voltage, and an output terminal outputting a first voltage; a first P The transistor has a gate receiving the first voltage, a source electrically connected to an input voltage, and a drain outputting the output voltage; a first resistor having one end electrically connected to the first P-type transistor The other end outputs a feedback voltage and transmits the feedback voltage to the positive input terminal of the first amplifier; and a second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of which is electrically Connecting a ground voltage, wherein when the feedback voltage is greater than the reference voltage, the first voltage rises and the current flowing through the first and the second resistor decreases, thereby reducing the output voltage, when the feedback voltage When the reference voltage is less than the reference voltage, the first voltage drops and the current flowing through the first and the second resistors rises, thereby increasing The output voltage. The biasing circuit of claim 10, wherein the electrostatic discharge protection circuit comprises a clamping unit, a triggering unit and a control unit, wherein the control unit comprises: a third resistor electrically connected at one end thereof a drain of the first P-type transistor, the other end of which receives the voltage-varying enable signal; and a first capacitor electrically connected to the other end of the third resistor, and the other end of which is electrically connected to the ground voltage The trigger unit includes: a second P-type transistor, wherein the gate is electrically connected to the other end of the third resistor, and the source is electrically connected to stabilize a second voltage for opening the current discharge channel; When the charge on the load capacitor is released, and a first N-type transistor, the gate is electrically connected to the other end of the third resistor, and the gate is electrically connected to the second P-type transistor. The drain is electrically connected to the ground voltage; wherein the clamping unit comprises: a second N-type transistor, the gate of which is electrically connected to the drain of the first N-type transistor, and the gate is electrically Connect the output voltage, its source is electrically connected a ground voltage, wherein the second P-type transistor and the first N-type transistor form an inverter, and when the voltage-variable enable signal is at a high voltage level, the second P-type transistor is turned off and the The first N-type transistor is turned on, and the gate of the second N-type transistor receives the ground voltage to turn off the current discharge channel. When the voltage-variable enable signal is at a low voltage level, the second P The type transistor is turned on and the first N-type transistor is turned off, and the gate of the second N-type transistor receives the second voltage to turn on the current discharge channel. The bias circuit of claim 11, wherein the ESD protection circuit further comprises: a first diode, the anode is electrically connected to the output voltage, and the cathode is electrically connected to the second P-type a source of the transistor, the first diode is used to determine a voltage level of a source of the second P-type transistor. The bias circuit of claim 12, wherein when the bias circuit is subjected to electrostatic bombardment such that the output voltage rises abnormally, the voltage of the source of the second P-type transistor is the output The voltage of the first diode is subtracted from the voltage to maintain the opening of a current discharge channel during the discharge. The bias circuit of claim 10, wherein the ESD protection circuit comprises: a third P-type transistor, wherein the gate receives the variable voltage enable signal, and the source is electrically connected to the output a second capacitor, one end of which is electrically connected to the drain of the third P-type transistor, and the other end of which is electrically connected to the ground voltage; a fourth P-type transistor whose gate is electrically connected to the third a drain of the P-type transistor, the source of which is electrically connected to a stable third voltage for discharging the charge on the load capacitor when the current discharge channel is turned on; a third N-type transistor, The gate is electrically connected to the drain of the third P-type transistor, the drain is electrically connected to the drain of the fourth P-type transistor, the source is electrically connected to the ground voltage; and a fourth N The gate is electrically connected to the drain of the third N-type transistor, the drain is electrically connected to the output voltage, and the source is electrically connected to the ground voltage, wherein the fourth P-type transistor is The third N-type transistor constitutes an inverter When the voltage-variable enable signal is at a high voltage level, the third and fourth P-type transistors are turned off and the third N-type transistor is turned off, and the gate of the fourth N-type transistor is turned on. Receiving the ground voltage to turn off the current discharge channel. When the voltage transformation enable signal is at a low voltage level, the third and fourth P-type transistors are turned on and the third N-type transistor is turned off. The gate of the fourth N-type transistor receives the third voltage to turn on the current discharge channel. The bias circuit of claim 14, wherein the ESD protection circuit further comprises: a second diode, the anode is electrically connected to the output voltage, and the cathode is electrically connected to the fourth P-type The source of the transistor, the second diode is used to determine the voltage level of the source of the fourth P-type transistor. The bias circuit of claim 15, wherein the voltage of the source of the fourth P-type transistor is the output when the bias circuit is subjected to electrostatic bombardment such that the output voltage rises abnormally. The voltage is subtracted from the turn-on voltage of the second diode to maintain the opening of a current discharge channel during the discharge. An electronic device comprising: the bias circuit of claim 7; and a load receiving the output voltage.