KR20160150303A - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification - Google Patents
A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification Download PDFInfo
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- KR20160150303A KR20160150303A KR1020150088070A KR20150088070A KR20160150303A KR 20160150303 A KR20160150303 A KR 20160150303A KR 1020150088070 A KR1020150088070 A KR 1020150088070A KR 20150088070 A KR20150088070 A KR 20150088070A KR 20160150303 A KR20160150303 A KR 20160150303A
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- nmos fet
- power
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
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- H02M2001/0048—
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- Y02B70/16—
Abstract
There is no constitution of another ordinary transformer circuit and a structure of a zener diode element in a voltage converter for converting a high voltage of AC and DC power to a DC power of low voltage and the voltage between negative gate sources (NMOS) field-effect transistor (FET), that is, a negative threshold voltage 5-terminal NMOS transistor (negative threshold 5-terminal NMOS FET). Therefore, the circuit area of the transformer circuit 100 and the Zener diode 104 is usually removed to remove the area occupied by the circuit area of the transformer circuit 100 and the Zener diode 104, It is possible to implement a cost circuit and realize a circuit without power consumption in standby and operation power supply state by blocking standby and operation power loss and to realize free voltage operation up to high voltage supply region As shown in FIG.
Also, as a method of dividing an operation period into a voltage region and a high voltage region that are lower than the output voltage and supplying power by using a separate control signal, a method of using a high voltage capacitor to generate a negative threshold voltage 5-terminal NMOS transistor and a drain voltage of a negative threshold 5-terminal NMOS FET to control power amplification.
Description
(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current power source into a low voltage direct current power source, the constitution of the circuit region of the transformer circuit (100) and the zener diode (104) ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.
In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal
Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the
At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.
In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.
In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.
In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.
It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.
Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.
A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.
The embodiment of the present invention has the following features.
First, the circuit area of the
Second, by eliminating the configuration of the circuit region of the
Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.
Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .
Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.
Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.
Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >
Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification) is possible.
Ninth, a method of dividing an operation interval into a voltage region and a high voltage region which are lower than the output voltage and supplying power by using a separate control signal is proposed. Specifically, a high voltage capacitor is used to apply a negative threshold voltage, (Drain) voltage of a negative threshold 5-terminal NMOS FET to control power amplification.
A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the
In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.
A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.
As described above, the embodiment of the present invention has the following effects.
First, the circuit area of the
Second, by eliminating the configuration of the circuit region of the
Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.
Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.
Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.
Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.
Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.
Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification can be realized.
Ninth, a method of dividing an operation interval into a voltage region and a high voltage region which are lower than the output voltage and supplying power by using a separate control signal is proposed. Specifically, a high voltage capacitor is used to apply a negative threshold voltage, a drain voltage of a negative threshold 5-terminal NMOS FET can be controlled to realize power amplification.
It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is an operational waveform diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention. FIG.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.
A rectifying
The rectifying
Therefore, it becomes an obstacle factor in constructing a low cost circuit.
On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the
The output terminal 103 of the
At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.
The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate).
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .
The body (B) terminal may be connected to a common ground terminal for supplying a ground voltage of 0 V according to a design selection method, and to the source (S) terminal A second connection method is available which is used as an output terminal.
More specifically,
As a first method, the gate (G) terminal, the body (B) terminal and the P-substrate (P-sub) terminal are connected to a common ground terminal Respectively.
As another second selection method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, (body: B) terminal is connected to the source (S) terminal and is used as an output terminal.
And the gate (G) terminal may be supplied with a separate control voltage.
The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
In addition, the drain (D) terminal region may surround the body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region.
The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.
The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.
Additional operating characteristics of the PN varistor structure are as follows.
Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.
A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.
When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.
The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source (S) terminal may be connected to the body (B) terminal as an output terminal, or may be used as an output terminal using only the source (S) terminal. .
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
The rectifying circuit 401 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source into a DC power source. In addition, the present invention is also applicable to a rectifier diode configured to convert DC power to DC power.
That is, the present invention is characterized in that the rectifier diode can be used as a rectifier diode configured to be connected to a DC power source regardless of the polarity of the DC power source.
An
The rectifying output terminal 402 of the rectifying circuit 401 is connected to a drain of a plurality of N negative threshold 5-terminal NMOS FETs 403, 409, 415, D) terminals 404 (410; 416; 422).
The connection configuration of the first negative threshold voltage 5-terminal NMOS FET 403 is as follows.
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is connected to a semiconductor doping (not shown) having n-
The source S terminal 407 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 403, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 407. [
The drain (D) terminal 404 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.
The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The source (S) terminal 407 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-1 power supply terminal 408 as an output terminal for obtaining a target output power supply voltage. Is used.
The connection configuration of the second negative threshold voltage 5-terminal NMOS FET 409 is as follows.
The gate terminal G 411 of the negative threshold 5-terminal NMOS FET 409 and the P-substrate (P-substrate) terminal 411 of the negative threshold voltage 5-terminal NMOS FET 409 412 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.
The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 is a semiconductor doping having an n-
The source (S) terminal 413 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 409, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 413.
The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 409 may be, for example, -1 V, -2 V, -3 V, And has a negative value.
The gate (G) terminal 411 of the negative threshold 5-terminal NMOS FET 409 is connected to the negative threshold voltage 5-terminal NMOS transistor (negative) (S) terminal 407 of the threshold 5-terminal NMOS FET 403 or the Step-1 power supply terminal 408 serving as an output terminal. The P-substrate (P-sub) terminal 412 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The source (S) terminal 413 is a semiconductor doping region having n-type semiconductor characteristics, and a Step-2 power supply terminal 414 serving as an output terminal for obtaining a target output power supply voltage. Is used.
The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.
The gate terminal G 417 of the negative threshold 5-terminal NMOS FET 415 and the P-substrate P-sub terminal 417 of the negative threshold voltage 5- 418 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.
The source terminal 419 of the negative threshold 5-terminal NMOS FET 415 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics N power supply terminal 420, which is an output terminal for obtaining a target output power supply voltage as a power supply voltage and a doping region.
The source (S) terminal 420 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 415, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 420.
The drain (D) terminal 416 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.
The gate (G) terminal 417 of the negative threshold 5-terminal NMOS FET 415 is connected to the negative threshold voltage 5-terminal NMOS transistor 415 (S) terminal 413 of the threshold 5-terminal NMOS FET 409 or the Step-2 power supply terminal 414 which is an output terminal.
The P-substrate (P-sub) terminal 418 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The source (S) terminal 419 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-N power supply terminal 420 as an output terminal for obtaining a target output power supply voltage. Is used.
Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.
The control circuit is constituted by using the N-folded Step-N power supply terminal voltage generated as the power source.
The control circuit is composed mainly of an amplifier (OP amplifier) 430.
One terminal input of the control circuit amplifier (OP amplifier) 430 receives the reference voltage REF and the other terminal receives the voltage of the Power Amp power supply terminal 426 to be distributed to R1 427 and R2 428 One output sensing voltage Vs 429 is input.
The voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) 430 is a negative threshold 5-terminal NMOS FET 421, which is a power amplifier element. To the gate (G) terminal 423 of the flip-flop.
The negative (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 is common to the rectified output terminal 402 of the rectifying circuit 401 Lt; / RTI >
The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 is a semiconductor doping having an n-type semiconductor characteristic amp; power supply terminal 426, which is an output terminal for obtaining a target output power supply voltage in a " doping " region.
The source (S) terminal 425 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 421, And may have an optional feature that may be used as the Power Amp power supply terminal 426 using only the source (S) terminal 425. [
The Power Amp power supply terminal 426 is applied to a high current supply capability and a high power consumption load. Accordingly, the negative threshold 5-terminal NMOS FET 421 becomes a device of a power amplifier having a high power driving capability.
The P-substrate (P-sub) terminal 424 of the negative threshold 5-terminal NMOS FET 421 is connected to a ground terminal Respectively, to a common ground terminal.
An LV detector 432 for detecting a low voltage LV of the rectified output terminal 402 of the rectifying circuit 401 is connected to the power supply terminal 426. When the voltage of the external
When the voltage of the external
The input signals of the two respective AND (435) logic circuits perform an AND operation. therefore
The AND output terminal 436 signal of the AND 435 logic circuit is coupled to the gate (G) terminal 441 of the negative threshold 5-terminal NMOS FET 439 .
The input terminal of the high voltage diode 437 is connected to the rectifying output terminal 402 of the rectifying circuit 401 and the output terminal of the high voltage diode 437 is connected to the
The high voltage diode 437 is intended to prevent backflow. The
The source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics to an LVD
The LVD
The source (S) terminal 443 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 439, And may have an optional feature that may be used as the Power Amp power supply terminal 426 using only the source (S) terminal 443.
The Power Amp power supply terminal 426 is applied to a high current supply capability and a high power consumption load. Accordingly, the negative threshold voltage 5-terminal NMOS FET 439 becomes a device of a power amplifier having a high power driving capability.
The P-substrate (P-sub) terminal 442 of the negative threshold 5-terminal NMOS FET 439 is connected to a ground terminal Respectively, to a common ground terminal.
5 is an operational waveform diagram of a power amplification voltage conversion circuit using the negative threshold voltage 5-terminal NMOS FET of the present invention.
The input power source 500 passes through a rectifier circuit and is input to a drain (D) terminal 404 of a negative threshold 5-terminal NMOS FET 403.
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.
The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.
Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.
Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .
Power Amp power supply terminal 526 is applied to high current supply capability and high power consumption load. Therefore, by designing to have the Power Amp power supply terminal 526 that is lower than the voltage of Step-N
An LV detector 432 for detecting a low voltage LV of the rectified output terminal 402 of the rectifying circuit 401 is connected to the power supply terminal 426. When the voltage of the external
When the voltage of the external
Each of the two input signals of the AND 435 logic circuit performs an AND operation and outputs a High signal to the AND output terminal 436.
The High signal of the AND output terminal 436 of the AND 435 logic circuit is applied to the gate (G) terminal 441 of the negative threshold 5-terminal NMOS FET 439 .
Therefore, a signal of the LVD power supply terminal 544 is generated in a period in which the voltage of the external
(Negative threshold 5-terminal NMOS FET) 439 in a period in which the voltage of the external
100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 rectifier circuit
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal
426 Power Amp power supply terminal
444 LVD power supply terminal
Claims (7)
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
First, a negative threshold 5-terminal NMOS FET 403; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A step-1 power supply terminal connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying the output power, (408); And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-sub) A first body (B) connected to one of the terminals (406); And
Second, a negative threshold 5-terminal NMOS FET 409; And
A drain (D) terminal 410 of the negative threshold 5-terminal NMOS FET 409 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 407 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403, a gate (G) terminal 411 of a negative threshold 5-terminal NMOS FET 409; And
A common ground terminal connected to a P-substrate (P-substrate) terminal 412 to supply a ground voltage; And
A Step-2 power supply terminal connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 for supplying output power, (414); And
The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 or the P-substrate (P-sub) A second body (B) selectively connected to one of the terminals (412); And
Nth negative threshold 5-terminal NMOS FET 415; And
A drain (D) terminal 416 of the negative threshold 5-terminal NMOS FET 415 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 413 connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409, a gate (G) terminal 417 of a negative threshold 5-terminal NMOS FET 415; And
A common ground terminal connected to a P-substrate (P-sub) terminal 418 for supplying a ground voltage; And
And a Step-N power supply terminal connected to the source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 for supplying output power, (420); And
The source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 or the P-substrate (P-sub) An Nth body (B) terminal connected to one of the terminals of the first switch (418); And
N + 1 th negative threshold 5-terminal NMOS FET 421, which is a power amplifier device; And
A drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 connected to the rectified output terminal 402; And
A Power Amp power supply terminal (not shown) connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 for supplying output power 426); And
A series connection resistor R1 427 and an R2 (428) element of the voltage distribution circuit connected to the Power Amp power supply terminal 426; And
A control circuit amplifier (OP amplifier) 430 using the voltage of the Step-N power supply terminal 420 as a power source and using the distribution sense voltage Vs 429 of the voltage divider circuit and the reference voltage REF as inputs, ; And
A gate of a negative threshold 5-terminal NMOS FET 421 connected to the voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) ) Terminal 423; And
A common ground terminal connected to a P-substrate (P-sub) terminal 424 to supply a ground voltage; And
The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 or the P-substrate (P-substrate) 425 of the negative threshold voltage 5- An (N + 1) -th body (B) terminal connected to one terminal of the terminal 424; And
A negative threshold 5-terminal NMOS FET 439 as a power amplifier (N + 2) th power amplifier; And
A high voltage diode 437 having a forward input terminal connected to the rectified output terminal 402; And
A high voltage capacitor 438 connected to the forward output terminal of the high voltage diode 437; And
A drain (D) terminal 440 of the negative threshold 5-terminal NMOS FET 439 coupled to the forward output terminal of the high voltage diode 437; And
An LV detector 432 connected to the rectified output terminal 402 to sense a low voltage LV; And
An AND 435 logic element receiving the LVD output signal 433 of the LV detector 432 and the output terminal 431 signal of the control circuit amplifier (OP amplifier) 430 as inputs; And
(Gate: G) terminal of the negative threshold 5-terminal NMOS FET 439 coupled to the AND output terminal 436 of the AND 435 logic. 441); And
A common ground terminal connected to a P-substrate (P-sub) terminal 442 for supplying a ground voltage; And
And an LVD power supply terminal 444 connected to the source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 for supplying the output power. ); And
The Power Amp power supply terminal 426 connected to the LVD power supply terminal 444; And
The source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 or the P-substrate (P-sub) And an N + 2th body (B) terminal connected to one terminal of the terminal 442 selectively.
A smoothing capacitor capacitive element 420 is provided between the Step-1 power supply terminal 408, the Step-2 power supply terminal 414, the Step-N power supply terminal 420, or the Power Amp power supply terminal 426, Is further configured.
And a high-voltage power capacitor capacitive element is additionally provided between the rectified output terminal (402) and the ground terminal.
A plurality of output selection switches are additionally provided in the Step-1 power supply terminal 408, the Step-2 power supply terminal 414, the Step-N power supply terminal 420, or the Power Amp power supply terminal 426 Characterized by a power supply.
The drain (D) terminal 404, the drain D terminal 410, the drain D terminal 416, the drain D terminal 422, Drain (D) terminal 440 and the P-substrate 406, the P-substrate 412, and the P- (P-substrate) 414, a P-substrate (P-sub) terminal 424, and a P-substrate Characterized in that it is formed in a structure of a varistor function.
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
First, a negative threshold 5-terminal NMOS FET 403; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A step-1 power supply terminal connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying the output power, (408); And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-sub) A first body (B) connected to one of the terminals (406); And
Second, a negative threshold 5-terminal NMOS FET 409; And
A drain (D) terminal 410 of the negative threshold 5-terminal NMOS FET 409 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 407 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403, a gate (G) terminal 411 of a negative threshold 5-terminal NMOS FET 409; And
A common ground terminal connected to a P-substrate (P-substrate) terminal 412 to supply a ground voltage; And
A Step-2 power supply terminal connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 for supplying output power, (414); And
The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 or the P-substrate (P-sub) A second body (B) selectively connected to one of the terminals (412); And
Nth negative threshold 5-terminal NMOS FET 415; And
A drain (D) terminal 416 of the negative threshold 5-terminal NMOS FET 415 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 413 connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409, a gate (G) terminal 417 of a negative threshold 5-terminal NMOS FET 415; And
A common ground terminal connected to a P-substrate (P-sub) terminal 418 for supplying a ground voltage; And
And a Step-N power supply terminal connected to the source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 for supplying output power, (420); And
The source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 or the P-substrate (P-sub) An Nth body (B) terminal connected to one of the terminals of the first switch (418); And
N + 1 th negative threshold 5-terminal NMOS FET 421, which is a power amplifier device; And
A drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 connected to the rectified output terminal 402; And
A Power Amp power supply terminal (not shown) connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 for supplying output power 426); And
A series connection resistor R1 427 and an R2 (428) element of the voltage distribution circuit connected to the Power Amp power supply terminal 426; And
A control circuit amplifier (OP amplifier) 430 using the voltage of the Step-N power supply terminal 420 as a power source and using the distribution sense voltage Vs 429 of the voltage divider circuit and the reference voltage REF as inputs, ; And
A gate of a negative threshold 5-terminal NMOS FET 421 connected to the voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) ) Terminal 423; And
A common ground terminal connected to a P-substrate (P-sub) terminal 424 to supply a ground voltage; And
The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 or the P-substrate (P-substrate) 425 of the negative threshold voltage 5- An (N + 1) -th body (B) terminal connected to one terminal of the terminal 424; And
A negative threshold 5-terminal NMOS FET 439 as a power amplifier (N + 2) th power amplifier; And
A high voltage diode 437 having a forward input terminal connected to the rectified output terminal 402; And
A high voltage capacitor 438 connected to the forward output terminal of the high voltage diode 437; And
A drain (D) terminal 440 of the negative threshold 5-terminal NMOS FET 439 coupled to the forward output terminal of the high voltage diode 437; And
An LV detector 432 connected to the rectified output terminal 402 to sense a low voltage LV; And
An AND 435 logic element receiving the LVD output signal 433 of the LV detector 432 and the output terminal 431 signal of the control circuit amplifier (OP amplifier) 430 as inputs; And
(Gate: G) terminal of the negative threshold 5-terminal NMOS FET 439 coupled to the AND output terminal 436 of the AND 435 logic. 441); And
A common ground terminal connected to a P-substrate (P-sub) terminal 442 for supplying a ground voltage; And
And an LVD power supply terminal 444 connected to the source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 for supplying the output power. ); And
The Power Amp power supply terminal 426 connected to the LVD power supply terminal 444; And
The source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 or the P-substrate (P-sub) And an N + 2th body (B) terminal connected to one terminal of the terminal 442 selectively.
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
First, a negative threshold 5-terminal NMOS FET 403; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A step-1 power supply terminal connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying the output power, (408); And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-sub) A first body (B) connected to one of the terminals (406); And
Second, a negative threshold 5-terminal NMOS FET 409; And
A drain (D) terminal 410 of the negative threshold 5-terminal NMOS FET 409 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 407 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403, a gate (G) terminal 411 of a negative threshold 5-terminal NMOS FET 409; And
A common ground terminal connected to a P-substrate (P-substrate) terminal 412 to supply a ground voltage; And
A Step-2 power supply terminal connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 for supplying output power, (414); And
The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 or the P-substrate (P-sub) A second body (B) selectively connected to one of the terminals (412); And
Nth negative threshold 5-terminal NMOS FET 415; And
A drain (D) terminal 416 of the negative threshold 5-terminal NMOS FET 415 connected to the rectified output terminal 402; And
The negative threshold voltage emmos 5-terminal transistor element 413 connected to the source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409, a gate (G) terminal 417 of a negative threshold 5-terminal NMOS FET 415; And
A common ground terminal connected to a P-substrate (P-sub) terminal 418 for supplying a ground voltage; And
And a Step-N power supply terminal connected to the source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 for supplying output power, (420); And
The source (S) terminal 419 of the negative threshold 5-terminal NMOS FET 415 or the P-substrate (P-sub) An Nth body (B) terminal connected to one of the terminals of the first switch (418); And
N + 1 th negative threshold 5-terminal NMOS FET 421, which is a power amplifier device; And
A drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 connected to the rectified output terminal 402; And
A Power Amp power supply terminal (not shown) connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 for supplying output power 426); And
A series connection resistor R1 427 and an R2 (428) element of the voltage distribution circuit connected to the Power Amp power supply terminal 426; And
A control circuit amplifier (OP amplifier) 430 using the voltage of the Step-N power supply terminal 420 as a power source and using the distribution sense voltage Vs 429 of the voltage divider circuit and the reference voltage REF as inputs, ; And
A gate of a negative threshold 5-terminal NMOS FET 421 connected to the voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) ) Terminal 423; And
A common ground terminal connected to a P-substrate (P-sub) terminal 424 to supply a ground voltage; And
The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 or the P-substrate (P-substrate) 425 of the negative threshold voltage 5- An (N + 1) -th body (B) terminal connected to one terminal of the terminal 424; And
A negative threshold 5-terminal NMOS FET 439 as a power amplifier (N + 2) th power amplifier; And
A high voltage diode 437 having a forward input terminal connected to the rectified output terminal 402; And
A high voltage capacitor 438 connected to the forward output terminal of the high voltage diode 437; And
A drain (D) terminal 440 of the negative threshold 5-terminal NMOS FET 439 coupled to the forward output terminal of the high voltage diode 437; And
An LV detector 432 connected to the rectified output terminal 402 to sense a low voltage LV; And
An AND 435 logic element receiving the LVD output signal 433 of the LV detector 432 and the output terminal 431 signal of the control circuit amplifier (OP amplifier) 430 as inputs; And
(Gate: G) terminal of the negative threshold 5-terminal NMOS FET 439 coupled to the AND output terminal 436 of the AND 435 logic. 441); And
A common ground terminal connected to a P-substrate (P-sub) terminal 442 for supplying a ground voltage; And
And an LVD power supply terminal 444 connected to the source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 for supplying the output power. ); And
The Power Amp power supply terminal 426 connected to the LVD power supply terminal 444; And
The source (S) terminal 443 of the negative threshold 5-terminal NMOS FET 439 or the P-substrate (P-sub) And an (N + 2) -th body terminal connected to one terminal of the terminal 442, and is implemented as a semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150088070A KR20160150303A (en) | 2015-06-22 | 2015-06-22 | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150088070A KR20160150303A (en) | 2015-06-22 | 2015-06-22 | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification |
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| Publication Number | Publication Date |
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| KR20160150303A true KR20160150303A (en) | 2016-12-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020150088070A KR20160150303A (en) | 2015-06-22 | 2015-06-22 | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102411506B1 (en) | 2020-12-15 | 2022-06-21 | 부산대학교 산학협력단 | Apparatus and method for deriving deriving tropospheric ozone motion vector |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102411506B1 (en) | 2020-12-15 | 2022-06-21 | 부산대학교 산학협력단 | Apparatus and method for deriving deriving tropospheric ozone motion vector |
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