KR101822721B1 - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal - Google Patents

A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal Download PDF

Info

Publication number
KR101822721B1
KR101822721B1 KR1020150180518A KR20150180518A KR101822721B1 KR 101822721 B1 KR101822721 B1 KR 101822721B1 KR 1020150180518 A KR1020150180518 A KR 1020150180518A KR 20150180518 A KR20150180518 A KR 20150180518A KR 101822721 B1 KR101822721 B1 KR 101822721B1
Authority
KR
South Korea
Prior art keywords
terminal
voltage
circuit
power supply
roff
Prior art date
Application number
KR1020150180518A
Other languages
Korean (ko)
Other versions
KR20170072090A (en
Inventor
강희복
Original Assignee
강희복
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강희복 filed Critical 강희복
Priority to KR1020150180518A priority Critical patent/KR101822721B1/en
Publication of KR20170072090A publication Critical patent/KR20170072090A/en
Application granted granted Critical
Publication of KR101822721B1 publication Critical patent/KR101822721B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
    • G01R31/1236—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of surge arresters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

There is no constitution of another ordinary transformer circuit and a structure of a zener diode element in a voltage converter for converting a high voltage of AC and DC power to a DC power of low voltage and the voltage between negative gate sources (NMOS) field-effect transistor (FET), that is, a negative threshold voltage 5-terminal NMOS transistor (negative threshold 5-terminal NMOS FET). Therefore, the circuit area of the transformer circuit 100 and the Zener diode 104 is usually removed to remove the area occupied by the circuit area of the transformer circuit 100 and the Zener diode 104, It is possible to implement a cost circuit and realize a circuit without power consumption in standby and operation power supply state by blocking standby and operation power loss and to realize free voltage operation up to high voltage supply region As shown in FIG.
In addition, it is possible to stably detect and amplify a signal of a sensor element whose output signal is weak.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a power supply circuit device using a 5-terminal NMOS transistor device, and more particularly, to a power supply circuit device using a 5-terminal NMOS transistor device XOR logic operation of sensor signal}

(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current power source into a low voltage direct current power source, the constitution of the circuit region of the transformer circuit (100) and the zener diode (104) ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.

In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal voltage transforming circuit 100 is a circuit region causing a large area and cost in the circuit configuration.

Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.

In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.

In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication, ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.

It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.

Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.

A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.

The embodiment of the present invention has the following features.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Which makes it possible to implement a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss .

Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .

Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.

Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >

Eighth, the relay coil device is separately configured to turn off the power supply circuit in the control operation state, thereby enabling ON / OFF of the drive device.

Ninth, it is possible to stably detect and amplify a signal of a sensor element whose output signal is weak.

A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the transformer circuit 100 is usually removed to save a large area and power consumption in the constitution of the transformer circuit 100 So that a low-cost circuit can be constituted. In addition, the structure of the Zener diode 104 circuit area is removed to reduce the area occupied in the circuit area of the Zener diode 104, and the standby and operation power consumption, And to realize a circuit without power loss in standby and operation power supply states.

In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.

A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate: P-Sub). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.

As described above, the embodiment of the present invention has the following effects.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Thereby enabling implementation of a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss do.

Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.

Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.

Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.

Eighth, the relay coil device is separately formed, and the power supply circuit is cut off under the control operation condition, thereby enabling ON / OFF of the driving device.

Ninthly, it is possible to stably detect and amplify a signal of a sensor element whose output signal is weak.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is a schematic diagram of a power supply terminal synthesis configuration of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention. FIG.
6 is an operational waveform diagram of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.
7 is an XOR logic configuration diagram of the sensor sensing and amplifying operation circuit of the present invention.
8 is a waveform diagram of an XOR Logic operation of the sensor sensing and amplifying operation circuit of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.

A rectifying circuit 102 and a zener diode 104 in a voltage converting apparatus for converting an AC input power supply 100 into a low voltage DC power supply voltage do. The transformer circuit 100 is a circuit region for converting a high voltage input power source to a low voltage.

The rectifying circuit 102 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source to a DC power source. The transformer circuit 100 is usually a circuit area that causes a large area and cost in the construction of the circuit.

Therefore, it becomes an obstacle factor in constructing a low cost circuit.

On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

The output terminal 103 of the rectifying circuit 102 is used as the final output Step-1 power supply terminal 105. [

At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.

The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate).

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The P-type isolated body (B) terminal has an isolated element structure and is connected to a common ground terminal for supplying a 0V ground voltage according to a design selection method as follows The first connection method and the second connection method, which is connected to the source (S) terminal and used as an output terminal, are possible.

More specifically,

As a first method, the gate (G) terminal, the isolated body (B) terminal, and the P-substrate (P-sub) Respectively.

In another alternative method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, An isolated body (B) terminal is connected to the source (S) terminal and is used as an output terminal.

And the gate (G) terminal may be supplied with a separate control voltage.

The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

In addition, the drain (D) terminal region may surround the isolated body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region .

The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.

The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.

Additional operating characteristics of the PN varistor structure are as follows.

Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.

A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.

When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.

The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source S terminal may be connected to the isolated body B terminal as an output terminal or may be used as an output terminal using only the source S terminal. Specification characteristics.

3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).

4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention is a circuit region for converting AC input power to DC output power. It is also characterized in that it can be used for converting DC input power to DC output power.

That is, the present invention is also applicable to a case where a DC power source is connected to a DC power source regardless of the polarity of the DC power source.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460 and a second half-wave rectification power generator 470 circuit corresponding to two half- .

The relay circuit 491 cuts off the supply power applied to the separate load, and implements a switching switching operation that opens or closes the electric circuit of the load in accordance with the operation signal of the relay coil 492.

The first input terminal 401 which is the two input terminals of the single phase input power source 400 is connected to the input terminal of the first half wave rectification power generator 460 through the relay coil 492, Are respectively connected to the input terminals of the second half-wave rectification power generator 470.

Or the second input terminal 402 is connected to the input terminal of the first half-wave rectification power generator 460 which is the two input terminals of the single-phase input power supply 400 and the relay coils 492, Half-wave rectification power generator 470 through the second half-wave rectification power generator 470.

The circuit configurations of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 470 in the respective circuit areas are the same.

Wave rectification power generator 460 and the second half-wave rectification power generator 470 are the same as those in the circuit areas of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 470 470), the detailed circuit configuration will be described as follows.

The first input terminal 401 or the second input terminal 402 which are two input terminals of the single phase input power supply 400 are connected to the first half wave rectification power generator 460 or the second half wave rectification power generator 470, A drain (D) terminal (404; 410; 416; 426) of a plurality of N negative threshold 5-terminal NMOS FETs (403; 409; 415; 421) 422, respectively.

The connection configuration of the first negative threshold voltage 5-terminal NMOS FET 403 is as follows.

The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of the output PN diode D1. The N-type terminal of the output PN diode D1 is used as a Step-1 power supply terminal 408 which is an output terminal for obtaining a target output power supply voltage.

An ESD1 device 481 is formed between the source S terminal 407 and the ground terminal to remove the abnormal voltage applied to the Step-1 power supply terminal 408, Thereby enabling protection of the electronic device connected to the supply terminal 408.

The ESD1 device 481 is composed of a PN diode, an NMOS FET diode, or a device having a snap-back characteristic at a threshold voltage.

The drain of the negative threshold 5-terminal NMOS FET 403 of one of the abnormal voltages inputted to the Step-1 power supply terminal 408, for example, the abnormal voltage introduced by the punch-through characteristic between the drain (D) terminal 404 and the source (S) terminal 407 is also applicable.

The source (S) terminal 407 is connected to the P-type isolated body (B) terminal 403 of the negative threshold 5-terminal NMOS FET 403 And may be used as an output terminal by using only the source (S) terminal 407. In addition,

The drain (D) terminal 404 is connected to the first input terminal 401 or the second input terminal 401 of the single-phase input power supply 400 as a semiconductor doping region having n-type semiconductor characteristics 402, respectively. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the second negative threshold voltage 5-terminal NMOS FET 409 is as follows.

The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 is a semiconductor doping having an n-type semiconductor characteristic doping region connected to the P-type terminal of the output PN diode D2. The N-type terminal of the output PN diode D2 is used as a Step-2 power supply terminal 414 which is an output terminal for obtaining a target output power supply voltage.

An ESD2 element 482 is formed between the source terminal 413 and the ground terminal to remove the abnormal voltage flowing into the Step-2 power supply terminal 414, Thereby enabling protection of the electronic device connected to the supply terminal 414.

The source (S) terminal 413 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 409 And may be used as an output terminal, or may be used as an output terminal using only the source (S) terminal 413.

The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic and is connected to the first input terminal 401 or the second input terminal 401 of the single- 402, respectively. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 409 may be, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 411 of the negative threshold 5-terminal NMOS FET 409 is connected to the negative threshold voltage 5-terminal NMOS transistor (negative) (S) terminal 407 of the threshold 5-terminal NMOS FET 403 or the Step-1 power supply terminal 408 serving as an output terminal. The P-substrate (P-sub) terminal 412 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.

The source terminal 419 of the negative threshold 5-terminal NMOS FET 415 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of D3, the output PN diode. The N-type terminal of the output PN diode D3 is used as a Step-N power supply terminal 420 which is an output terminal for obtaining a target output power supply voltage.

An ESD3 element 483 is formed between the source S terminal 419 and the ground terminal to remove the abnormal voltage flowing into the Step-N power supply terminal 420, Thereby enabling protection of the electronic device connected to the supply terminal 420.

The source (S) terminal 420 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 415 Or may be used as an output terminal by using only the source (S) terminal 420. In addition,

The drain (D) terminal 416 is a semiconductor doping region having an n-type semiconductor characteristic. The first input terminal 401 or the second input terminal 416 of the single- 402, respectively. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 417 of the negative threshold 5-terminal NMOS FET 415 is connected to the negative threshold voltage 5-terminal NMOS transistor 415 (S) terminal 413 of the threshold 5-terminal NMOS FET 409 or the Step-2 power supply terminal 414 which is an output terminal.

The P-substrate (P-sub) terminal 418 is connected to a common ground terminal for supplying a ground voltage of 0V.

Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.

The Step-N power supply terminal 420 is connected to the RCSW 493, which is a relay coil switch. The RCSW 493, which is the Relay Coil Switch, performs an ON / OFF operation according to a control signal of the RCSW controller 494.

The RCSW 493, which is the Relay Coil Switch, includes a switch composed of semiconductor devices such as a mechanical drive switch, an SCR switch, and a transistor switch.

When the RCSW 493 is turned on, a relay current flows to the relay coil 492 so that the relay circuit 491 blocks the load power supply circuit.

Test_SW 495, which is a test switch, is separately configured to test the operation characteristics of the relay circuit 491.

The Step-N power supply terminal 420 is connected to the Test_SW 495 in parallel.

When the Test_SW 495 is turned on, a relay current flows to the relay coil 492 so that the relay circuit 491 blocks the load power supply circuit.

The Test_SW 495 as the test switch includes a switch composed of a semiconductor device such as a mechanical drive switch, an SCR switch, and a transistor switch.

5 is a diagram illustrating a power supply terminal synthesis configuration of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460 and a second half-wave rectification power generator 470 circuit corresponding to two half- .

A first input terminal 401 which is two input terminals of the single phase input power supply 400 is connected to an input terminal of the first half wave rectification power generator 460 and a second input terminal 402 is connected to the second half wave rectification power generator 460. [ (470).

The circuit configurations of the first half-wave rectification power generator 460 and the second half-wave rectification power generator 470 in the respective circuit areas are the same.

Step-1 power supply terminals 408 and Step-2 power supply terminals 414, which are the output power supply terminals of the first half-wave rectification power generator 460 or the second half-wave rectification power generator 470, And the Step-N power supply terminal 420 have the same circuit configuration in the circuit region.

Therefore, the Step-1 power supply terminal 408, which is the output power supply terminal of the first half-wave rectification power generator 460, and the Step-1 power supply terminal 1408, which is the output power supply terminal of the second half-wave rectification power generator 470, ) Are connected to each other to constitute a combined Step-1 power supply terminal 508. If the composite configuration is expanded as described above, the composite Step-2 power supply terminal 514 and the composite Step-N power supply terminal 520 are also configured in the same manner.

6 is an operation waveform diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The input power source 500 includes an AC waveform of a first half wave and a second half wave and has a negative threshold voltage 5-terminal in a circuit region of the first half wave rectification power generator 460 or the first half wave rectification power generator 460 And is input to the drain (D) terminal of a negative threshold 5-terminal NMOS FET.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.

Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.

Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .

7 is a block diagram of the XOR logic of the sensor sensing and amplifying operation circuit of the present invention.

The sensor 710 may include a zero current transformer (ZCT), temperature, humidity, gas, magnetic, light, acceleration, vibration, speed, revolution, angle, pressure, stress, strain, torque, And the like.

One output terminal SN_L of the sensor 710 is connected to the base terminal of the BJT 704 which is an NPN transistor.

The other output terminal SN_R of the sensor 710 is connected to the base terminal of the BJT 703 which is an NPN transistor.

The emitter terminals of the BJT 704 and the BJT 703, which are NPN transistors, are connected to the ground terminal GND.

The SN_L is commonly connected to the collector and base terminals of the BJT 702, which is an NPN transistor.

SN_R is commonly connected to the collector and base terminals of the BJT 701, which is an NPN transistor.

The emitter terminals of the BJT 702 and the BJT 701, which are the NPN transistors, are connected to the ground terminal GND.

The SN_L is connected to one terminal of a resistance element Rbias_L for supplying a bias voltage. The other terminal of Rbias_L is connected to the power supply terminal VDD.

The SN_R is connected to one terminal of a resistor element Rbias_R for supplying a bias voltage. The other terminal of the Rbias_R is connected to the power supply terminal VDD.

The collector terminal of the BJT 704, which is the NPN transistor, is commonly connected to one terminal of Roff_set_LT (-) and Roff_set_LB (+), which is a resistance element for controlling the off-set voltage.

The collector terminal of the BJT 703, which is the NPN transistor, is commonly connected to one terminal of Roff_set_RT (+) and a terminal of Roff_set_RB (-), which is a resistance element for controlling the off-set voltage.

The resistances of Roff_set_LB (+) and Roff_set_RT (+) are larger than resistance values of Roff_set_LT (-) and Roff_set_RB (-), respectively.

It may also be set to a resistance value opposite to the above state.

That is, the resistance values of the left and right resistance elements are configured to have an asymmetric value.

The other terminals of the resistor elements Roff_set_LT (-) and Roff_set_RT (+) are connected to the upper latch circuit 711, respectively.

The other terminals of the resistor elements Roff_set_LB (+) and Roff_set_RB (-) are connected to the lower latch circuit 712, respectively.

The upper latch circuit 711 and the lower latch circuit 712 are symmetrical with the same circuit configuration.

One inverter of the upper latch circuit 711 is composed of an NMOS NM 706 and a PMOS PM 708.

The other inverter of the upper latch circuit 711 is composed of an NMOS NM 705 and a PMOS PM 707.

The two inverters of the upper latch circuit 711 are connected to each other in a cross-coupled manner.

The power terminal of the upper latch circuit 711 is connected to the power terminal VDD.

One output terminal LO_T of the upper latch circuit 711 is connected to the first input terminal of the XOR 709 which is an exclusive-OR device.

One inverter of the lower latch circuit 712 is composed of an NMOS NM 714 and a PMOS PM 716.

The other inverter of the lower latch circuit 712 is composed of an NMOS NM 713 and a PMOS PM 715.

The two inverters of the lower latch circuit 712 are connected to each other in a cross-coupled manner.

The power supply terminal of the lower latch circuit 712 is connected to the power supply terminal VDD.

One output terminal LO_B of the lower latch circuit 712 is connected to the second input terminal of the exclusive-OR device XOR 709.

SOUT, which is an output signal of the exclusive OR device XOR 709, is used as a control signal of the RCSW 493 which is the relay coil switch.

The power supply terminal VDD is connected to the synthetic Step-N power supply terminal 520.

8 is an XOR Logic operation waveform diagram of the sensor sensing and amplifying operation circuit of the present invention.

When the output of the sensor 710 is less than the threshold value, a potential difference is formed between the SN_L, which is one output terminal, and the SN_R, which is the other output terminal, below the threshold value.

The potential difference less than the threshold value can equivalently be defined as not exceeding the difference between the resistance values of Roff_set_LT (-), Roff_set_RT (+), Roff_set_LB (+) and Roff_set_RB (-).

Therefore, one output terminal LO_T of the upper latch circuit 711 and one output terminal LO_B of the lower latch circuit 712 become the opposite signals, and the output signal SOUT of the exclusive-OR becomes the High signal.

On the contrary, when the output of the sensor 710 is formed above the threshold value, a potential difference is formed between the SN_L as one output terminal and the SN_R as the other output terminal with a threshold value or more.

The potential difference of the threshold value or more may be equivalently defined as exceeding the difference between the resistance values of Roff_set_LT (-), Roff_set_RT (+), Roff_set_LB (+) and Roff_set_RB (-).

Therefore, one output terminal LO_T of the upper latch circuit 711 and one output terminal LO_B of the lower latch circuit 712 become the same signal, and the output signal SOUT of the exclusive-OR becomes a low signal.

100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 first input terminal
402 second input terminal
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal

Claims (2)

1. An XOR Logic operation control apparatus for sensing and amplifying a sensor signal, comprising:
One output terminal SN_L of the sensor 710 is connected to the base terminal of the BJT 704 which is an NPN transistor,
The other output terminal SN_R of the sensor 710 is connected to the base terminal of the BJT 703 which is an NPN transistor,
The emitter terminals of the BJT 704 and the BJT 703, which are NPN transistors, are connected to a ground terminal GND,
The collector terminal of the BJT 704, which is the NPN transistor, is commonly connected to one terminal of Roff_set_LT (-) and a terminal of Roff_set_LB (+), which are resistance elements for controlling the off-set voltage,
The collector terminal of the BJT 703, which is the NPN transistor, is commonly connected to one terminal of Roff_set_RT (+) and a terminal of Roff_set_RB (-), which is a resistance element for controlling the off-set voltage,
The resistance value of each of Roff_set_LB (+) and Roff_set_RT (+) is greater than the resistance values of Roff_set_LT (-) and Roff_set_RB (-),
The other terminals of the resistor elements Roff_set_LT (-) and Roff_set_RT (+) are connected to the upper latch circuit 711, respectively,
The other terminals of the resistor elements Roff_set_LB (+) and Roff_set_RB (-) are connected to the lower latch circuit 712, respectively,
The upper latch circuit 711 and the lower latch circuit 712 are symmetrical with the same circuit configuration,
One inverter of the upper latch circuit 711 is composed of an NMOS NM 706 and a PMOS PM 708,
The other inverter of the upper latch circuit 711 is composed of an NMOS NM 705 and a PMOS PM 707,
The two inverters of the upper latch circuit 711 are connected in a cross-coupled manner to each other,
The power supply terminal of the upper latch circuit 711 is connected to the power supply terminal VDD,
One output terminal LO_T of the upper latch circuit 711 is connected to the first input terminal of the exclusive-OR device XOR 709,
One inverter of the lower latch circuit 712 is composed of an NMOS NM 714 and a PMOS PM 716,
The other inverter of the lower latch circuit 712 is composed of an NMOS NM 713 and a PMOS PM 715,
The two inverters of the lower latch circuit 712 are connected to each other in a cross-coupled manner,
The power supply terminal of the lower latch circuit 712 is connected to the power supply terminal VDD,
And one output terminal LO_B of the lower latch circuit 712 is connected to a second input terminal of the XOR 709 which is an exclusive-OR device. The XOR logic operation control device of the sensor signal sensing and amplifying circuit .
delete
KR1020150180518A 2015-12-16 2015-12-16 A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal KR101822721B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150180518A KR101822721B1 (en) 2015-12-16 2015-12-16 A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150180518A KR101822721B1 (en) 2015-12-16 2015-12-16 A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal

Publications (2)

Publication Number Publication Date
KR20170072090A KR20170072090A (en) 2017-06-26
KR101822721B1 true KR101822721B1 (en) 2018-03-08

Family

ID=59282710

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150180518A KR101822721B1 (en) 2015-12-16 2015-12-16 A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal

Country Status (1)

Country Link
KR (1) KR101822721B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102122677B1 (en) * 2019-02-06 2020-06-12 주식회사 에프램 A Sensing Signal Control Circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140145762A1 (en) 2012-08-06 2014-05-29 Texas Instruments Incorporated Power supply sensing circuits in integrated circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140145762A1 (en) 2012-08-06 2014-05-29 Texas Instruments Incorporated Power supply sensing circuits in integrated circuits

Also Published As

Publication number Publication date
KR20170072090A (en) 2017-06-26

Similar Documents

Publication Publication Date Title
KR101734767B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for Offset-decoder strong-ARM amplifier
KR101734766B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for Offset-generation strong-ARM amplifier
KR101661085B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for fuse offset-decoder strong-ARM amplifier
KR101729838B1 (en) An earth leakage breaker system using a five-terminal NMOS FET device embedded with power LDMOS trip driver
KR101661881B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for calibration offset-decoder strong-ARM amplifier
KR101801450B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for application of Sensor
KR101822721B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for XOR logic operation of Sensor signal
KR101734768B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for double strong-ARM amplifier
KR101801451B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for application of Off-set Reconfiguration Sensor
KR101694091B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for Flyback inductor schematic application
KR101689971B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for single-phase full-wave driver
KR101689974B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for three-phase driver
KR101689972B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for single-phase full-wave application
KR101775831B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for Mirror-decoder strong-ARM amplifier
KR101689973B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for three-phase rectifier
KR101971361B1 (en) A Sensing Detection Voltage Generation Strong-ARM Amplifier
KR101689970B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for single-phase full-wave rectifier
KR101677387B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for power amplification using power save mode control
KR101689969B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter
KR20170027225A (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for power amplification using power save leakage control
KR101694101B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for full-wave rectifier regulation
KR101705453B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for power RF
KR101706016B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for Power Clock Counter
KR101694100B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device for full-wave rectifier using case-embedded antenna
KR101694013B1 (en) A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for boosting voltage

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant