KR101689969B1 - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter - Google Patents
A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter Download PDFInfo
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- KR101689969B1 KR101689969B1 KR1020150125189A KR20150125189A KR101689969B1 KR 101689969 B1 KR101689969 B1 KR 101689969B1 KR 1020150125189 A KR1020150125189 A KR 1020150125189A KR 20150125189 A KR20150125189 A KR 20150125189A KR 101689969 B1 KR101689969 B1 KR 101689969B1
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- 239000000758 substrate Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 abstract description 30
- 230000003321 amplification Effects 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 230000005669 field effect Effects 0.000 abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
- 150000004706 metal oxides Chemical class 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000007792 addition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010187 selection method Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
- H02M7/066—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode particular circuits having a special characteristic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current (DC) power source to a low voltage direct current power source, characterized in that the constitution of the circuit region of the transformer circuit (101) and the zener diode ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.
In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal
Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying
At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.
In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.
In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.
In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.
It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.
Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.
A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.
The embodiment of the present invention has the following features.
First, the circuit area of the
Second, by eliminating the configuration of the circuit region of the
Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.
Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .
Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.
Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.
Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >
Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification) is possible.
Ninth, Negative DC / DC Converter circuit is used to make negative voltage generation and supply possible.
A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the
In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.
A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.
As described above, the embodiment of the present invention has the following effects.
First, the circuit area of the
Second, by eliminating the configuration of the circuit region of the
Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.
Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.
Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.
Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.
Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.
Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification can be realized.
Ninth, the negative DC / DC converter circuit can be used to generate and supply negative voltage.
It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is an operational waveform diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention. FIG.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.
A rectifying
The rectifying
Therefore, it becomes an obstacle factor in constructing a low cost circuit.
On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the
The
At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.
The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate).
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .
The body (B) terminal may be connected to a common ground terminal for supplying a ground voltage of 0 V according to a design selection method, and to the source (S) terminal A second connection method is available which is used as an output terminal.
More specifically,
As a first method, the gate (G) terminal, the body (B) terminal and the P-substrate (P-sub) terminal are connected to a common ground terminal Respectively.
As another second selection method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, (body: B) terminal is connected to the source (S) terminal and is used as an output terminal.
And the gate (G) terminal may be supplied with a separate control voltage.
The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
In addition, the drain (D) terminal region may surround the body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region.
The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.
The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.
Additional operating characteristics of the PN varistor structure are as follows.
Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.
A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.
When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.
The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source (S) terminal may be connected to the body (B) terminal as an output terminal, or may be used as an output terminal using only the source (S) terminal. .
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
The rectifying
That is, the present invention is characterized in that the rectifier diode can be used as a rectifier diode configured to be connected to a DC power source regardless of the polarity of the DC power source.
An
The rectifying
The connection configuration of the first negative threshold voltage 5-
The
The source (S)
The source S terminal 407 is commonly connected to the body (B) terminal of the negative threshold 5-
The drain (D) terminal 404 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-
The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The source (S) terminal 407 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-1
The connection configuration of the second negative threshold voltage 5-
delete
The source (S)
The source (S) terminal 413 is connected in common to the body (B) terminal of the negative threshold 5-
The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-
The gate (G)
The source (S) terminal 413 is a semiconductor doping region having n-type semiconductor characteristics, and a Step-2
The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.
delete
The
The source (S) terminal 420 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 415, And may have an optional characteristic that may be used as an output terminal using only the source (S)
The drain (D) terminal 416 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.
The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.
The gate (G)
The P-substrate (P-sub)
The source (S) terminal 419 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-N
Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.
The control circuit is constituted by using the N-folded Step-N power supply terminal voltage generated as the power source.
The control circuit is composed mainly of an amplifier (OP amplifier) 430.
The
The
The other terminal of the resistor element R1 442 is connected to the Step-N power supply terminal and to the other ground terminal of the Zener diode 440.
Meanwhile, the other terminal of the resistor R1 442 is connected to any one of the Step-1 power supply terminal, the Step-2 power supply terminal, or the Step-N power supply terminal.
The control output voltage of the Zener diode 440 is equal to the
The resistance element R1 442 serves as a control resistance element for supplying a minimum bias voltage for generating the control output voltage of the Zener diode 440. [
The voltage of the
The negative (D)
The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 is a semiconductor doping having an n-type semiconductor characteristic amp; power supply terminal 426, which is an output terminal for obtaining a target output power supply voltage in a " doping " region.
The source (S) terminal 425 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 421, And may have an optional feature that may be used as the Power Amp power supply terminal 426 using only the source (S) terminal 425. [
The Power Amp power supply terminal 426 is applied to a high current supply capability and a high power consumption load. Accordingly, the negative threshold 5-terminal NMOS FET 421 becomes a device of a power amplifier having a high power driving capability.
The P-substrate (P-sub)
The input power of the negative DC / DC converter 450 circuit is input to the Power Amp power supply terminal 426. The negative DC / DC converter 450 generates a negative voltage and supplies a negative voltage to the negative voltage power supply terminal 451, which is an output terminal.
5 is an operational waveform diagram of a power amplification voltage conversion circuit using the negative threshold voltage 5-terminal NMOS FET of the present invention.
The input power source 500 passes through a rectifier circuit and is input to a drain (D)
The threshold voltage (Vt: Vgs) of the negative threshold 5-
The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.
The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.
Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.
Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .
Power Amp power supply terminal 526 is applied to high current supply capability and high power consumption load. Therefore, by designing to have the Power Amp power supply terminal 526 that is lower than the voltage of Step-N power supply terminal 520 which is N times the voltage, it is designed to be a device of Power Amplifier having high power driving capability under high Vgs voltage driving condition .
The Negative Voltage power supply terminal 551, which is the negative output terminal signal of the Negative DC / DC Converter 450 circuit, is a power supply characterized by a negative voltage implementation.
100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 rectifier circuit
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal
426 Power Amp power supply terminal
Claims (7)
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
A negative threshold 5-terminal NMOS FET 421; And
A drain (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 connected to the rectified output terminal 402; And
A Power Amp power supply terminal (not shown) connected to the source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 for supplying output power 426);
A gate (G) terminal 423 of the negative threshold 5-terminal NMOS FET 421; And
A common ground terminal connected to a P-substrate (P-sub) terminal 424 to supply a ground voltage; And
A structure having a PN varistor function between the drain (D) terminal 422 and the P-substrate (P-sub) terminal 424; And
And a Negative DC / DC Converter (450) circuit connected to the Power Amp power supply terminal (426) to generate a negative voltage.
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KR1020150125189A KR101689969B1 (en) | 2015-09-04 | 2015-09-04 | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter |
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KR1020150125189A KR101689969B1 (en) | 2015-09-04 | 2015-09-04 | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter |
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KR101689969B1 true KR101689969B1 (en) | 2016-12-26 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000060110A (en) * | 1998-08-11 | 2000-02-25 | Oki Electric Ind Co Ltd | Drive control circuit for charge pump circuit |
JP2002247838A (en) * | 2001-02-15 | 2002-08-30 | Denso Corp | Voltage boosting circuit, and inverter circuit for alleviating voltage between drain and source |
KR101985373B1 (en) * | 2019-01-04 | 2019-06-04 | 김진경 | Waste Plastic Recycling Extrusion System and Plastic Recycling Method Using Thereof |
-
2015
- 2015-09-04 KR KR1020150125189A patent/KR101689969B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000060110A (en) * | 1998-08-11 | 2000-02-25 | Oki Electric Ind Co Ltd | Drive control circuit for charge pump circuit |
JP2002247838A (en) * | 2001-02-15 | 2002-08-30 | Denso Corp | Voltage boosting circuit, and inverter circuit for alleviating voltage between drain and source |
KR101985373B1 (en) * | 2019-01-04 | 2019-06-04 | 김진경 | Waste Plastic Recycling Extrusion System and Plastic Recycling Method Using Thereof |
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