KR101645888B1 - A power supply circuit system using a negative threshold five-terminal NMOS FET device with Drain Terminal Power Capacitor - Google Patents

A power supply circuit system using a negative threshold five-terminal NMOS FET device with Drain Terminal Power Capacitor Download PDF

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Publication number
KR101645888B1
KR101645888B1 KR1020150088063A KR20150088063A KR101645888B1 KR 101645888 B1 KR101645888 B1 KR 101645888B1 KR 1020150088063 A KR1020150088063 A KR 1020150088063A KR 20150088063 A KR20150088063 A KR 20150088063A KR 101645888 B1 KR101645888 B1 KR 101645888B1
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terminal
voltage
negative threshold
power
nmos fet
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KR1020150088063A
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Korean (ko)
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강희복
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강희복
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H02M2001/0048—
    • Y02B70/16—

Abstract

There is no constitution of another ordinary transformer circuit and a structure of a zener diode element in a voltage converter for converting a high voltage of AC and DC power to a DC power of low voltage and the voltage between negative gate sources (NMOS) field-effect transistor (FET), that is, a negative threshold voltage 5-terminal NMOS transistor (negative threshold 5-terminal NMOS FET). Therefore, the circuit area of the transformer circuit 100 and the Zener diode 104 is usually removed to remove the area occupied by the circuit area of the transformer circuit 100 and the Zener diode 104, It is possible to implement a cost circuit and realize a circuit without power consumption in standby and operation power supply state by blocking standby and operation power loss and to realize free voltage operation up to high voltage supply region As shown in FIG.
In addition, a power capacitor is connected to the drain (D) terminal, which is a high voltage terminal of a negative threshold voltage 5-terminal NMOS FET, and a small-capacity power capacitor And a power supply unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a power supply circuit device using a five-terminal NMOS transistor device,

(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current power source into a low voltage direct current power source, the constitution of the circuit region of the transformer circuit (100) and the zener diode (104) ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.

In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal voltage transforming circuit 100 is a circuit region causing a large area and cost in the circuit configuration.

Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.

In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.

In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.

It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.

Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.

A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.

The embodiment of the present invention has the following features.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Which makes it possible to implement a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss .

Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .

Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.

Sixth, it has features that enable the implementation of the PN varistor function as the role of power surge, rational brain surge, and ESD (electrostatic discharge) protection.

Seventh, a power capacitor is connected to the drain terminal, which is a high voltage terminal of a negative threshold voltage 5-terminal NMOS FET, to enable the implementation of a small-area power capacitor by high voltage effect. .

A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the transformer circuit 100 is usually removed to save a large area and power consumption in the constitution of the transformer circuit 100 So that a low-cost circuit can be constituted. In addition, the structure of the Zener diode 104 circuit area is removed to reduce the area occupied in the circuit area of the Zener diode 104, and the standby and operation power consumption, And to realize a circuit without power loss in standby and operation power supply states.

In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.

A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate, the drain D is connected to the terminal to which the power before the voltage conversion is input, and the source is connected to the power after voltage conversion. Supply terminals, respectively.

As described above, the embodiment of the present invention has the following effects.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Thereby enabling implementation of a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss do.

Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.

Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.

Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.

Seventh, it is possible to implement a small-sized power capacitor by the effect of high voltage by connecting a power capacitor to a drain terminal which is a high voltage terminal of a negative threshold voltage 5-terminal NMOS FET (negative threshold 5-terminal NMOS FET) .

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
5 is an operational waveform diagram of a voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
6 is a configuration diagram of a smoothing capacitor capacitive element parallel additional voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
7 is a configuration diagram of a multiple output voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.
8 is a configuration diagram of a multiple output selection voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.

A rectifying circuit 102 and a zener diode 104 in a voltage converting apparatus for converting an AC input power supply 100 into a low voltage DC power supply voltage do. The transformer circuit 100 is a circuit region for converting a high voltage input power source to a low voltage.

The rectifying circuit 102 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source to a DC power source. The transformer circuit 100 is usually a circuit area that causes a large area and cost in the construction of the circuit.

Therefore, it becomes an obstacle factor in constructing a low cost circuit.

On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

And the output terminal 103 of the rectifying circuit 102 is used as the final output power supply terminal 105. [

At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.

The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate).

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The body (B) terminal may be connected to a common ground terminal for supplying a ground voltage of 0 V according to a design selection method, and to the source (S) terminal A second connection method is available which is used as an output terminal.

More specifically,

As a first method, the gate (G) terminal, the body (B) terminal and the P-substrate (P-sub) terminal are connected to a common ground terminal Respectively.

As another second selection method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, (body: B) terminal is connected to the source (S) terminal and is used as an output terminal.

And the gate (G) terminal may be supplied with a separate control voltage.

The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

In addition, the drain (D) terminal region may surround the body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region.

The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.

The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.

Additional operating characteristics of the PN varistor structure are as follows.

Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.

A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.

When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.

The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source (S) terminal may be connected to the body (B) terminal as an output terminal, or may be used as an output terminal using only the source (S) terminal. .

3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).

4 is a configuration diagram of a voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectifying circuit 401 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source into a DC power source. In addition, the present invention is also applicable to a rectifier diode configured to convert DC power to DC power.

That is, the present invention is characterized in that the rectifier diode can be used as a rectifier diode configured to be connected to a DC power source regardless of the polarity of the DC power source.

The rectifier circuit 401 has a configuration of a full wave rectifier diode circuit in which an input power source 400 is connected to an input terminal and a rectified output terminal 1 is connected to a rectified output terminal 402 of a rectifier circuit 401, Terminal 0 is connected to the common ground terminal (GND).

The rectifying circuit 401 rectifying output terminal 402 is connected to the drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403.

A gate terminal 405 of a negative threshold voltage 5-terminal NMOS FET 403 and a P-substrate 406 Are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

Negative Threshold Voltage The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is a semiconductor doping (n-type) semiconductor having n- ) Region is used as a power supply terminal 408 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 407 may be connected in common to the body (B) terminal of FIG. 2 and used as an output terminal. The source terminal S 407 may be connected to the output Terminal. ≪ / RTI >

The drain (D) terminal 404 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

A power capacitor 409 is connected to the drain (D) terminal 404, which is a high voltage terminal of the negative threshold 5-terminal NMOS FET 403, to a high voltage The power capacitor 409 having a small area can be realized. That is, because the power capacitor 409 is charged with a high voltage, the capacitance of the power capacitor 409 may be small, and a feature that the area of the power capacitor 409 can be reduced in realizing the same charging capacity is used.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The gate (G) terminal may be supplied with a separate reference voltage.

The source terminal S is used as a power supply terminal 408 serving as an output terminal for obtaining a target output power supply voltage to a semiconductor doping region having n-type semiconductor characteristics .

5 is an operational waveform diagram of a voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The input power source 500 passes through a rectifier circuit and is input to a drain (D) terminal 404 of a negative threshold 5-terminal NMOS FET 403.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The voltage of the power supply terminal 508 of the source S terminal corresponds to the threshold voltage Vt of the negative threshold 5-terminal NMOS FET Have positive output supply voltage values of + 1V, + 2V, + 3V, and + 4V, respectively

6 is a configuration diagram of a smoothing capacitor capacitive element parallel additional voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

A smoothing capacitor capacitance element 610 is additionally provided to the power supply terminal 408 as an output terminal of FIG. 4 so that a smoothing capacitor capacitance element 610 is further provided to provide the smoothing characteristic of the power supply terminal 408 .

7 is a configuration diagram of a multiple output voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectifying circuit 701 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source into a DC power source. In addition, the present invention is also applicable to a rectifier diode configured to convert DC power to DC power.

That is, the present invention is characterized in that the rectifier diode can be used as a rectifier diode configured to be connected to a DC power source regardless of the polarity of the DC power source.

An input power supply 700 is connected to the input terminal of the rectifier circuit 701. The rectifier output terminal 1 is connected to the output terminal 702 of the rectifier circuit 701, (0) is connected to the common ground terminal (GND).

The output terminal 702 of the rectifying circuit 701 is connected to a drain (D) terminal 704 and a drain (D) terminal 704 of a plurality of multiple negative threshold 5-terminal NMOS FETs. D) terminal 710, respectively.

A gate terminal G 705 and a gate terminal G 711 of the negative threshold 5-terminal NMOS FET are connected to the P-substrate P Substrate: P-sub) 706 and a P-substrate (P-sub) 712 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The source terminal S of the negative threshold 5-terminal NMOS FET is a semiconductor doping region having an n-type semiconductor characteristic. And is used as the power supply terminal 708 and the power supply terminal 714, which are output terminals for obtaining the output power supply voltage, respectively.

The multi-drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic and is a terminal structure for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be set to a negative value such as -1 V, -2 V, -3 V, Value.

The plurality of gate (G) terminals and the P-substrate (P-sub) terminals are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The plurality of the gate (G) terminals may be supplied with a separate reference voltage.

The multi-source terminal S is a semiconductor doping region having an n-type semiconductor characteristic, and includes a power supply terminal 708 and an output terminal 708 for obtaining a target output power supply voltage. 714, respectively.

8 is a configuration diagram of a multiple output selection voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

An output supply terminal 807 and an output supply terminal 817, which are the multiple source (S) output terminals of FIG. 7, are used as inputs to the multiple output selection switch 815 to select one of the output supply terminals And is characterized by the output power supply of the single power supply terminal 816. [

100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Power supply terminal
400 input power
401 rectifier circuit
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 power supply terminal
409 Power Capacitor
610 Smoothing Capacitor Capacitor
815 Multiple output selection switch

Claims (7)

1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
A negative threshold 5-terminal NMOS FET 403; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
A high voltage Power Capacitor 409 connected to the drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A power supply terminal 408 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying output power, ; And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-substrate) 407 of the negative threshold voltage 5- And a body (B) terminal that is selectively connected to one of the terminals (406). The method according to claim 1,
And a smoothing capacitor capacitance element (609) is additionally formed between the power supply terminal (408) and the ground terminal. The method according to claim 1,
A negative threshold 5-terminal NMOS FET 709 is connected in parallel to the negative threshold 5-terminal NMOS FET 403, And further comprising a plurality of output voltage conversion circuits. The method of claim 3,
Wherein the multiple output voltage conversion circuit further comprises a multiple output selection switch (815). The method according to claim 1,
And a PN varistor function is formed between the drain (D) terminal 404 and the P-substrate 406. The P- 1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
A negative threshold 5-terminal NMOS FET 403; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
A high voltage Power Capacitor 409 connected to the drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A power supply terminal 408 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying output power, ; And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-substrate) 407 of the negative threshold voltage 5- And a body (B) terminal that is selectively connected to one of the terminals (406). 1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
A rectifying circuit (401) composed of a rectifying diode for converting AC power into DC power; And
A negative threshold 5-terminal NMOS FET 403; And
An input power terminal 400 connected to the input terminal of the rectifying circuit 401; And
A rectifying output terminal 402 connected to an output terminal of the rectifying circuit 401; And
A drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403 coupled to the rectified output terminal 402; And
A high voltage Power Capacitor 409 connected to the drain (D) terminal 404 of the negative threshold 5-terminal NMOS FET 403; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A power supply terminal 408 connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 for supplying output power, ; And
The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 or the P-substrate (P-substrate) 407 of the negative threshold voltage 5- And a body (B) terminal that is selectively connected to one of the terminals (406), and is implemented as a semiconductor integrated circuit.
KR1020150088063A 2015-06-22 2015-06-22 A power supply circuit system using a negative threshold five-terminal NMOS FET device with Drain Terminal Power Capacitor KR101645888B1 (en)

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KR1020150088063A KR101645888B1 (en) 2015-06-22 2015-06-22 A power supply circuit system using a negative threshold five-terminal NMOS FET device with Drain Terminal Power Capacitor

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000060110A (en) * 1998-08-11 2000-02-25 Oki Electric Ind Co Ltd Drive control circuit for charge pump circuit
JP2002247838A (en) * 2001-02-15 2002-08-30 Denso Corp Voltage boosting circuit, and inverter circuit for alleviating voltage between drain and source
KR101985373B1 (en) * 2019-01-04 2019-06-04 김진경 Waste Plastic Recycling Extrusion System and Plastic Recycling Method Using Thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000060110A (en) * 1998-08-11 2000-02-25 Oki Electric Ind Co Ltd Drive control circuit for charge pump circuit
JP2002247838A (en) * 2001-02-15 2002-08-30 Denso Corp Voltage boosting circuit, and inverter circuit for alleviating voltage between drain and source
KR101985373B1 (en) * 2019-01-04 2019-06-04 김진경 Waste Plastic Recycling Extrusion System and Plastic Recycling Method Using Thereof

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