CN103872133A - 短沟道沟槽式金属氧化物半导体场效应管 - Google Patents

短沟道沟槽式金属氧化物半导体场效应管 Download PDF

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CN103872133A
CN103872133A CN201310680613.XA CN201310680613A CN103872133A CN 103872133 A CN103872133 A CN 103872133A CN 201310680613 A CN201310680613 A CN 201310680613A CN 103872133 A CN103872133 A CN 103872133A
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gate electrode
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谢福渊
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LISHI TECHNOLOGY Co Ltd
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Abstract

本发明公开了一种具有短沟道的沟槽式金属氧化物半导体场效应管，可以降低沟道电阻。其中，在体区下方的外延层中包括至少一个场释放区，其自对准于沟槽式源-体接触区，可以防止发生漏-源之间的穿通现象。

Description

短沟道沟槽式金属氧化物半导体场效应管
相关申请的交叉引用
本申请案要求对于2012年12月12日提交的美国专利申请第13／711,857号的优先权，该专利申请披露的内容通过全文引用而结合与本文中。
技术领域
本发明主要涉及功率半导体器件的单元结构和器件构造。更具体地，本发明涉及一种新型改良的短沟道金属氧化物半导体场效应管(shortchannel trenched Metal oxide Semiconductor Field EffectTransistor)。
背景技术
图1A公开了现有技术中的一种传统的沟槽MOSFET 100(金属氧化物半导体场效应管，下同)，其形成于一个N型外延层104中，能够防止N+漏区和n+源区之间产生穿通(punch-through)效应。在图1A的有源区中，一个沟槽式源-体接触区101穿过n+源区102并延伸入位于每两个相邻的栅沟槽105之间的P型体区103中，其中，所述的n+源区102沿与所述的N型外延层104上表面等距离的方向上具有相同的掺杂浓度和相同的结深。每个所述的栅沟槽105填充以一个栅电极106并衬有栅极氧化层107，其中所述栅极氧化层沿所述栅电极106的侧壁和底部的厚度相等。当该沟槽式MOSFET位于开启状态时，在所述的栅沟槽105附近的P型体区103中，沿从n+源区102到N+漏区之间形成沟道区，由于传统的沟槽式MOSFET具有较长的沟道长度，因而会产生较大的沟道电阻。
因此，在半导体功率器件领域中，特别是对于沟槽式MOSFET的设计和制造，仍需要提供一种新型的器件结构和制造方法可以解决上述现有技术具有的困难和设计限制。
发明内容
本发明提供了一种沟槽式MOSFET，其具有短沟道结构，可以有效降低沟道电阻。此外，根据本发明的沟槽式MOSFET可以在降低源漏电阻的同时不发生穿通效应。
根据本发明的实施例，提供了一种具有短沟道的沟槽式MOSFET，其形成于第一导电类型的外延层中，并位于第一导电类型的衬底之上，该沟槽式MOSFET进一步包括：
(a)多个栅沟槽，位于有源区中，从所述外延层的上表面垂直向下延伸，每个所述的栅沟槽都填充有一个栅电极并衬有一层栅极氧化层；
(b)第二导电类型的体区，位于所述外延层的上部分，并位于每两个相邻的所述栅沟槽之间；
(c)第一导电类型的源区，包含于所述体区中；
(d)至少一个第二导电类型的场释放区，位于每个所述的体区下方，并位于每两个相邻的所述栅沟槽之间的外延层中。
在一些优选的实施例中，所述短沟槽的长度小于0.5um。
在一些优选的实施例中，根据本发明的沟槽式MOSFET进一步包括：一个沟槽式源-体接触区，其填充以一个接触金属插塞，穿过所述的源区并延伸入所述的体区；一个第二导电类型的体接触区，位于所述的体区中，至少包围所述的沟槽式源-体接触区的底部。
在一些优选的实施例中，所述的场释放区自对准于所述的沟槽式源-体接触区。
在一些优选的实施例中，所述的源区沿与所述外延层上表面等距离的方向上具有相等的掺杂浓度和相同的结深。在另一个优选的实施例中，在与所述外延层上面等距离的方向上，所述的源区靠近所述的沟槽式源-体接触区侧壁处比靠近所述的短沟道处具有较大的掺杂浓度和较深的结深。
在一些优选的实施例中，位于所述的栅沟槽中的栅电极是单栅电极结构，并衬有所述的栅极氧化层。在另一些优选的实施例中，所述的栅电极位于一个屏蔽电极之上，所述的屏蔽电极衬有一层屏蔽电极氧化层并与所述的外延层绝缘，所述的栅电极与所述的屏蔽电极之间由一层电极绝缘层绝缘。
在一些优选的实施例中，所述的栅极氧化层沿所述栅电极底部的厚度大于其沿所述栅电极侧壁的厚度。在另一些优选的实施例中，所述的栅极氧化层沿所述栅电极底部的厚度等于或小于其沿所述栅电极侧壁的厚度。在另一些优选的实施例中，所述的栅极氧化层沿所述栅电极底部和下部分侧壁的厚度大于其沿所述栅电极上部分侧壁的厚度。
在一些优选的实施例中，包括两个第二导电类型的场释放区，其都位于所述的体区下方，并且其中一个所述的场释放区位于另一个上方。在另一些优选的实施例中，包括多个第二导电类型的场释放区，其都位于所述的体区下方，并且该多个场释放区自下而上依此分布。
在一些优选的实施例中，还包括一个终端区，其进一步包括多个具有悬浮电压的沟槽栅，其中每个所述的具有悬浮电压的沟槽栅之间由所述的体区分开，且该体区中不包含所述的源区。
本发明的一个优点是，相比于现有技术可以显著沟道电阻。
本发明的另一个优点是，可以有效降低源漏电阻。
本发明的另一个优点是，可以预防穿通效应。
附图说明
本发明的这些和其他实施方式的优点将通过下面结合附图的详细说明和所附权利要求书，使得本领域的普通技术人员明了，其中：
图1示出了现有技术所揭示的一种沟槽式金属氧化物半导体场效应管的剖面图。
图2示出了根据本发明的一个优选实施例的剖面图。
图3示出了根据本发明的另一个优选实施例的剖面图。
图4示出了根据本发明的另一个优选实施例的剖面图。
图5示出了根据本发明的另一个优选实施例的剖面图。
图6示出了根据本发明的另一个优选实施例的剖面图。
图7示出了根据本发明的另一个优选实施例的剖面图。
图8示出了根据本发明的另一个优选实施例的剖面图。
图9示出了根据本发明的另一个优选实施例的剖面图。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2所示的是本发明的一个优选的实施例的有源区结构，其中N沟道沟槽式MOSFET200形成于一个N外延层201中(本发明中的导电类型并不用于限制作用，也可以是P沟道沟槽式MOSFET形成在位于P+衬底之上的P外延层中)，该N外延层位于一个N+衬底202之上，其中该N+衬底202的底部覆盖有金属层作为漏极金属层203。多个栅沟槽204从所述N外延层201的上表面向下延伸至所述N外延层201内，每个所述的栅沟槽204都填充以一个栅电极205并衬有一层栅极氧化层206，其中，所述的栅极氧化层206沿所述栅电极205底部的厚度等于或小于其沿所述栅电极205侧壁的厚度。所述的栅电极205优选地可以为掺杂的多晶硅层。一个n+源区211包含于一个P型体区207中，并位于每两个所述的栅沟槽204之间的所述N外延层201的上部分，与现有技术相比，所述的P型体区207具有较小的结深以形成短沟道结构。同时，在沿与所述N外延层201的上表面等距离的方向上，所述的n+源区211具有相等的掺杂浓度和相同的结深。一个沟槽式源-体接触区208位于每两个相邻的栅沟槽204之间，其填充以一个接触金属插塞209，并穿过一个接触夹层210、所述的n+源区211且进一步延伸入所述的P型体区207，将所述的P型体区207和所述的n+源区211连接至源极金属层220，其中，所述的接触夹层210包括一个BPSG(硼磷硅玻璃，下同)层2101以及下方的一个NSG(未掺杂的磷硅玻璃)层2102，，所述的接触金属插塞209优选地可以为钨插塞，并衬有一层由Ti／TiN或Co／TiN或Ta／TiN组成的势垒层。在每个所述的沟槽式源-体接触区208的下方，包括一个p+体接触掺杂区212，其位于所述的P型体区207中，并至少包围所述的沟槽式源-体接触区208的底部，以降低所述的P型体区207和所述的接触金属插塞209之间的接触电阻。在一些优选的实施例中，所述的p+体接触掺杂区212可以包围所述沟槽式源-体接触区208位于所述的n+源区211以下的侧壁和底部。根据本发明，在形成所述的沟槽式源-体接触区208的开口之后，通过该开口处进行p型离子注入，形成一个p型岛区(Pi，如图2所示)214，其位于所述的P型体区207的下方，并位于每两个相邻的栅沟槽204之间的N外延层201中，该p型岛区214的作用是作为一个场释放区，且自对准于所述的沟槽式源-体接触区208，能够防止漏-源之间产生穿通现象。当该沟槽式MOSFET200位于开启状态时，在靠近所述的栅沟槽204的P型体区207中形成短沟道，因此可以降低沟道电阻。
图3所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET300具有与图2相似的有源区结构，除了在图3中没有使用源区掩模版，因此每个n+源区311在于所述的N外延层301上表面等距离的方向上，其靠近所述的沟槽式源-体接触区308处较靠近短沟道处具有更高的掺杂浓度和更大的结深，并且沿从所述的沟槽式源-体接触区308到短沟道的方向上，所述的n+源区311的掺杂浓度呈现高斯分布，这种结构在节省源区掩模版的同时可以增强器件的雪崩特性。
图4所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET400具有与图3相似的有源区结构，除了在图4中，栅极氧化层406沿栅电极405的底部的厚度大于其沿所述栅电极405侧壁的厚度。
图5所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET500具有与图3相似的有源区结构，除了在图5中，栅极氧化层506沿栅电极505底部和下部分侧壁的厚度大于其沿所述栅电极505上部分侧壁的厚度。
图6所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET600具有与图3相似的有源区结构，除了在图6中，每个栅沟槽604中都填充以双电极结构：一个位于下方的屏蔽电极(S，如图6所示)605和一个位于上方的栅电极(G，如图6所示)606。其中，所述屏蔽电极605的侧壁和底部都衬有一层屏蔽电极绝缘层607，所述的栅电极606的侧壁衬有栅极氧化层608，并且所述的屏蔽电极605和所述的栅电极606之间由一层电极绝缘层609所绝缘。同时，所述的屏蔽电极605被连接至源极金属层610。
图7所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET700具有与图3相似的有源区结构，除了在图7中，具有两个p型岛区(第一p型岛区“Pi1”和第二p型岛区“Pi2”，如图7所示)分别作为两个场释放区701和702，其中场释放区701形成于场释放区702之上，其二者位于P型体区707下方，并位于每两个相邻的栅沟槽704之间的N外延层703中，且该两个场释放区都自对准于沟槽式源-体接触区708，以进一步防止漏-源之间发生穿通现象。
图8所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET800具有与图2相似的有源区结构，除了在图8中，进一步包括一个终端区，其包括多个具有悬浮电压的沟槽栅801，该多个沟槽栅801之间由P型体区807所隔开，同时该P型体区807不包含n+源区，并且其下方没有场释放区。
图9所示的是根据本发明的另一个优选的实施例，其中N沟道沟槽式MOSFET900具有与图3相似的有源区结构，除了在图9中，进一步包括一个终端区，其包括多个具有悬浮电压的构成哦啊山901，该多个沟槽栅901之间由P型体区907所隔开，同时该P型体区907不包含n+源区，并且其下方没有场释放区。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围的所附权利要求书的范围内，通过所述的指导，可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构。

Claims (14)

1.一种沟槽式MOSFET，具有短沟道结构，其形成于第一导电类型的外延层中，并位于第一导电类型的衬底之上，该沟槽式MOSFET进一步包括：
多个栅沟槽，位于有源区中，从所述外延层的上表面垂直向下延伸，每个所述的栅沟槽都填充有一个栅电极并衬有一层栅极氧化层；
第二导电类型的体区，位于所述外延层的上部分，并位于每两个相邻的所述栅沟槽之间；
第一导电类型的源区，包含于所述体区中；
至少一个第二导电类型的场释放区，位于每个所述的体区下方，并位于每两个相邻的所述栅沟槽之间的外延层中。
2.根据权利要求1所述的沟槽式MOSFET，其中所述的所述短沟槽的长度小于0.5um。
3.根据权利要求1所述的沟槽式MOSFET，进一步包括：
一个沟槽式源-体接触区，其填充以一个接触金属插塞，穿过所述的源区并延伸入所述的体区；
一个第二导电类型的体接触区，位于所述的体区中，至少包围所述的沟槽式源-体接触区的底部。
4.根据权利要求3所述的沟槽式MOSFET，其中所述的场释放区自对准于所述的沟槽式源-体接触区。
5.根据权利要求3所述的沟槽式MOSFET，其中所述的源区沿与所述外延层上表面等距离的方向上具有相等的掺杂浓度和相同的结深。
6.根据权利要求3所述的沟槽式MOSFET，其中在与所述外延层上面等距离的方向上，所述的源区靠近所述的沟槽式源-体接触区侧壁处比靠近所述的短沟道处具有较大的掺杂浓度和较深的结深。
7.根据权利要求1所述的沟槽式MOSFET，其中位于所述的栅沟槽中的栅电极是单栅电极结构，并衬有所述的栅极氧化层。
8.根据权利要求7所述的沟槽式MOSFET，其中所述的栅极氧化层沿所述栅电极底部的厚度大于其沿所述栅电极侧壁的厚度。
9.根据权利要求7所述的沟槽式MOSFET，其中所述的栅极氧化层沿所述栅电极底部的厚度等于或小于其沿所述栅电极侧壁的厚度。
10.根据权利要求7所述的沟槽式MOSFET，其中所述的栅极氧化层沿所述栅电极底部和下部分侧壁的厚度大于其沿所述栅电极上部分侧壁的厚度。
11.根据权利要求1所述的沟槽式MOSFET，所述的栅电极位于一个屏蔽电极之上，所述的屏蔽电极衬有一层屏蔽电极绝缘层并与所述的外延层绝缘，所述的栅电极与所述的屏蔽电极之间由一层电极绝缘层绝缘。
12.根据权利要求1所述的沟槽式MOSFET，进一步包括两个第二导电类型的场释放区，其都位于所述的体区下方，并且其中一个所述的场释放区位于另一个上方。
13.根据权利要求1所述的沟槽式MOSFET，进一步包括多个第二导电类型的场释放区，其都位于所述的体区下方，并且该多个场释放区自下而上依此分布。
14.根据权利要求1所述的沟槽式MOSFET，还包括一个终端区，其进一步包括多个具有悬浮电压的沟槽栅，其中每个所述的具有悬浮电压的沟槽栅之间由所述的体区分开，且该体区中不包含所述的源区。
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