CN103854986B - 一种后栅工艺假栅的制造方法和后栅工艺假栅 - Google Patents

一种后栅工艺假栅的制造方法和后栅工艺假栅 Download PDF

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Publication number
CN103854986B
CN103854986B CN201210510352.2A CN201210510352A CN103854986B CN 103854986 B CN103854986 B CN 103854986B CN 201210510352 A CN201210510352 A CN 201210510352A CN 103854986 B CN103854986 B CN 103854986B
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China
Prior art keywords
hard mask
amorphous silicon
mask layer
ono structure
layer
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CN201210510352.2A
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English (en)
Chinese (zh)
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CN103854986A (zh
Inventor
李春龙
李俊峰
闫江
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210510352.2A priority Critical patent/CN103854986B/zh
Priority to PCT/CN2012/086401 priority patent/WO2014086054A1/fr
Publication of CN103854986A publication Critical patent/CN103854986A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
CN201210510352.2A 2012-12-03 2012-12-03 一种后栅工艺假栅的制造方法和后栅工艺假栅 Active CN103854986B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201210510352.2A CN103854986B (zh) 2012-12-03 2012-12-03 一种后栅工艺假栅的制造方法和后栅工艺假栅
PCT/CN2012/086401 WO2014086054A1 (fr) 2012-12-03 2012-12-12 Procédé de fabrication de grille factice dans un processus à formation de grille en dernier et grille factice dans un processus à formation de grille en dernier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210510352.2A CN103854986B (zh) 2012-12-03 2012-12-03 一种后栅工艺假栅的制造方法和后栅工艺假栅

Publications (2)

Publication Number Publication Date
CN103854986A CN103854986A (zh) 2014-06-11
CN103854986B true CN103854986B (zh) 2017-03-01

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Country Status (2)

Country Link
CN (1) CN103854986B (fr)
WO (1) WO2014086054A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762071B (zh) * 2014-12-17 2019-06-21 中国科学院微电子研究所 鳍式场效应晶体管及其鳍的制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1531018A (zh) * 2003-03-10 2004-09-22 联华电子股份有限公司 图案光阻的微缩制程
CN101211770A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 形成半导体器件栅极的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7576386B2 (en) * 2005-08-04 2009-08-18 Macronix International Co., Ltd. Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
CN100452317C (zh) * 2005-09-09 2009-01-14 联华电子股份有限公司 缩小特征尺寸的方法和半导体蚀刻方法
KR100831571B1 (ko) * 2006-12-28 2008-05-21 동부일렉트로닉스 주식회사 플래시 소자 및 이의 제조 방법
CN101236899A (zh) * 2007-01-30 2008-08-06 力晶半导体股份有限公司 栅极的制造方法
US20090130836A1 (en) * 2007-11-16 2009-05-21 Jong-Won Sun Method of fabricating flash cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1531018A (zh) * 2003-03-10 2004-09-22 联华电子股份有限公司 图案光阻的微缩制程
CN101211770A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 形成半导体器件栅极的方法

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Publication number Publication date
WO2014086054A1 (fr) 2014-06-12
CN103854986A (zh) 2014-06-11

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