201125105 六、發明說明： 【發明所屬之技術領域】 本發明係與互補式金氧半導體（CM〇s)有關，更詳 而言之是指一種三維多重閘極互補式金氧半導體及其 製法者。 〃 【先前技術】 按，互補式金氧半導體（CM0S)尺寸之微縮可以帶 來兩大好處，一是元件性能的提高，二是功耗的降低。 然而，這個趨勢如今卻已經達到了極限，元件中的銅 互連已經導致了串擾、功耗與電阻_電容（Rc)延遲方 面的問題。 一般來說’互補式金氧半導體尺寸的微縮是將關鍵 的閘極氧化層以降低厚度的方式達成最佳化的目的， 然^當時程進入奈米節點’傳統的二氧化石夕已無法 再藉由持續降低厚度達成良好的通道控制能力，其過 高=漏電流將使得尺寸向下縮小變得無以為繼，雖= 目别有使用氮氧化矽（Si0N)的方案，然其有限的介電 係=並無法有效延展互補式金氧半導體的世代演進， 目前各大互補式金氧半導體製造廠皆嘗試著不同的幾 個方向來達成元件特性的改善’例如加入局部或全面 的應變結構藉由應變力改變通道中石夕晶格常數來提升 載子傳輸速度，以提升元件效能，然而單靠應變技術 可此依然#法持續達成45nm或32nm以下所期盼的元 201125105 件效旎。而導入高介電常數介電質及穩定的功函數閘 極至屬層之方式，由於帶電載子可藉由穿隧效應穿透 介電質而形成漏電流，導入高介電常數介電質取代傳 ’-·充、i 〇2或S i 0N成為可行的方案之一，以求降低漏電 流並達成等效電容以控制通道開關。 此外，亦有廠商改變了過去五十年以來一直都採 用的軚準平面（tw〇_dimensi〇nal，二度空間）電晶體架 #構形成了二度空間（three-dimensional)的架構。例 如，科技（Infineon Technologies)發表 了多 f fy1 握眾放field-effect transistor)技 術’在未來是面對眾多挑戰的解決方法之一。在面積 小又需要眾多功能的積體電路上，可比今曰的平面星_ 里&技術（Planar single-gate)所消耗的功率要小很 夕。在此新技術的一項展示中，英飛凌的研究人員測 • 试了採用全新65nm多重閘極場效電晶體架構，所製造 全球第一個高複雜性電路，和目前的單閘極技術所生 產出相同功能和效能的產品相比較，其面積幾乎要縮 小約30% ’這類新電晶體的靜態電流是之前的十分之 一而已。依據研究人員的計算，和目前在生產製程使 用的65nm技術相比，如此之靜態電流將會使採用之攜 ▼式裂置的能量使用效率和電池壽命增加達一倍左 右’未來的製裎技術（32nm及以下的技術）還將進一步 大巾备提南此比例。 · 201125105 由英坻凌研究員所測試的65nm電路包括超過 3, 000個主動式電晶體，許多結果均確認三度空間多 重閘極技術和當今的各種成熟技術—樣的優異，但以 相同的各種功能來說，_耗的能量只有傳統平面閉 極-半左右’在未來的技術世代來說，此優勢將確信 會愈來愈重要。 目前為止’㈣多重難結構之互補式金氧半導 體專利甚多，此處不一一贅述，而關於三維閘極互補 式金氧半導胆之專利’如中華民國發明第％ ^ 謝號 「具源極/本體單—接點及側邊環繞㈣之垂直式金 氧半場效電晶體及其製作方法」及美國發㈣7378309 號「Wh〇d〇ffabricatlngl〇calinterc〇nnects〇n awhcon-germanium 3DCM〇s」等專利所示，皆 =重問極結構。換言之，三維之多重閉極互補二 H體結構顯然是半導體產業未來發展之趨 【發明内容】 補^ Γ之主要目的即在提供一種三維多重間極互 及其製法，其不僅符合半導體產業未 朝一，、隹、夕重閘極結構發展之趨勢，且，全 維開極結構相較於m/PMGS之料道可且有更古— 之驅動電流流動性，實用價值甚佳者。、- 唯多達成前述之目的，本發明係提供-種-甲’極互補式金氧半導體’包含有一矽基底；一 201125105 隔離層’形成於該石夕基底表 該絕緣層表面 A ，數間極’垂直設置於 形成於該石夕，鳍片’ 一石夕錯通道層’ 成於該石夕錯通道層外側，一H常數間極介電層，形 成於該㈣片1錯物=，係經熱處理，形 頂端。 、阿介電常數閘極介電層 該隔離層係埋入氧化層。 該保護層係氮化矽材質。 M +有—第—硬遮罩層’係形成於 各該閘極與隔離層表面更形成有一金 進—步地 進一步地 進一步地 該保護層表面 進一步地 屬閘極。 進一步地，該第一硬遮置展办一# AL ΛΙ , , . ’、 S係一氧化矽蝕刻形成。 惫 ’明更提供—種三維多重閘極互補式金 乳+導體之製法，苴牛挪s , 補式金 半埸4雷曰…士 少包含有：^提供一韓式 千％效電晶體結構，兮銼 、 ^，4式+場效電晶體結構包含一 矽基底、形成於矽基底 傅已3 絕❹矣…* 隔離層及垂直設置於 端·―料m主 ，b)沉積一保護層於矽鰭片頂 褐’ c)於保邊層表面沉藉 硬神罢s w 積並餘刻、圖案化形成一第一 遮罩層，d)進行熱處理 形成-犧牲氧化層；e)移除片外侧壁分別 該石夕轉片外側形成犧牲氧化層；f)於各 層外桕& ^八 、、層，S)於各該矽鍺通道 #外側开> 成一向介雷沓也_ , 電书數閘極介電層；h)沉積一金屬 201125105 i)將該金屬閘極層 閘極層於各該閘極與隔離層表面 钱刻、圖案化。 進一步地，沉積之 傾 < 方式係利用係化學氣相沉積 術，蝕刻、圖案化之方 又 力式係利用反應離子蝕刻機進杆 蝕刻'圖案化至蝕刻終止層。 進一步地，熱處理之方 氣化層係二氧化石夕。 進一步地，係利用稀釋 刻劑移除各該犧牲氧化層。 式係熱氧化處理，該犧牲 之氫氣酸或緩衝氧化層|虫 土、進纟地，係以蟲晶成長法於各該石夕趙片外側形 战矽鍺通道層。 進#地係利用原子沉積技術於各石夕錯通道層 卜側形成高介電常數閘極介電層。 進一步地’沉積之方式係制係化學氣相沉積技 ，’㈣、®案化之方式係、利用反應離子㈣機進 仃蝕刻、圖案化至蝕刻終止層。 【實施方式】 ^下级舉本發明二較佳實施例，並配合圖式做 進一步之詳細說明如後： :首先，明參閱圖-所示，本發明一較佳實施例之 ^維多重閘極互補式金氧半導體1G，包含有—石夕基底 2、—隔離層13與數閘極14。 該隔離層13，係埋入氧化層（Buried Oxide， 201125105 BOX) ’形成於該矽基底12表面，係絕緣層，可降低 寄生電容現象。 各該閘極14 ’分別包含一矽鰭片（Si_fin) 22， 係垂直設置於該絕緣層14表面（以上屬鰭狀半場效電 晶體結構），一矽鍺通道層（SiGe channel) 24，形 成於該矽鰭片22外側，一高介電常數（Hi_K)閘極介 電層26 ’形成於s亥>5夕錯通道層24外側，一保護層28， 鲁係經熱處理（Thermal treatment)之氮化石夕（siNx ) 材質，形成於該矽鰭片22、矽鍺通道層24與高介電 常數閘極介電層2 6頂端。 此外，該二維多重閘極互補式金氧半導體丨〇更包 含有一第一硬遮罩層15，係二氧化矽，蝕刻形成於該 保護層28表面，一閘極金屬層16，形成於各該閘極 14與隔離層13表面。 詳言之，如圖二所示，該三維多重閘極互補式金 • 氧半導體10之製法如下： 如圖三所示，第一步驟110係提供一鰭式半場效 電晶體⑺禮）、结構30:該縛式半場效電晶體結構 30包含一矽基底12、形成於矽基底12表面之一隔離 層13及垂直設置於絕緣層13表面之數矽鰭片22。 第二步驟120係沉積保護層28於矽鰭片22頂 端’該保護層28並經熱處理。 第三步驟13G係於保護層28表面沉積並餘刻、圖 201125105 案化形成第-硬遮罩層15:沉積之方式係利用化學氣 相沉積技術（Chemical Vap〇r Dep〇siti〇n，cvd)， 而韻刻、圖案化之方^係利用反應離子餘刻機 (Reactive丨on Etcher, R i E )進行蝕刻、圖案化 至蝕刻終止層（Etch Stop Uyer)。 ” 如圖四所示，第四步驟14〇係進行熱處理，使各 該石夕鰭片22外側壁分卿成—犧牲氧化層31 :熱處 理之方式係熱氧化處理，該犧牲氧化層31係二氧化 如圖五所示，第五步驟15〇係移除各該犧牲氧化 層30:利用稀釋之氫氟酸（DUutedHF，卿）或缓 衝氧化層㈣劑（HF+NH4F，職）移除各該犧牲氧化 層31而於矽鰭片22外側形成一凹陷部位& 如圖六所示’第六步驟⑽係於各該料片22外 側之凹陷部位32内形成一矽鍺通道層24 :以磊晶成 長法（Ep卜growth)於各該凹陷部位32形成石夕鍺通道 層2 4。 第七步驟170係於各該石夕錯通道層24外側形成一 向介電常數問極介電層26 :係利用原子沉積技術 (At_ Layer Depositi〇n，或化學氣相沉積 於切鍺通道層24外側形μ介 介電層26。 第八步驟180係沉積閘極金屬層16於各該問極 201125105 14與隔離層13表面。 刻、=第九步驟⑽係於該問極金屬層“表面钮 . ’亦利用化學氣相沉積技術及反應離子蝕 指術進彳了㈣、圖案化錄刻終止層。 前揭蝕刻終止層主要係用以控制蝕刻程度。 稭此，本發明該三維多重閘極互補式金氧 1 〇可至少獲致以下特色： 虹 該三維多重閘極互補式金氧半導體 半導體產業未來朝三維、多重間極結構發展之趨7 率、提升攜帶式裝置的能量使用效 二、電池命"效果，且，高介電常數（Hi_" 開極將居於小於65灿之CMOS技術之主流。此外，： = 目較於#Ν_之料道具有相 =驅動電流流動性’而各該間極14之保護㈣ '私中使用稀釋氫氣酸或緩衝氧化層韻刻劑移除 生减層3G及㈣金屬層關過封料销片、 由上可知，本發明所提供之三維 金:半導體及其製法，其不僅符合半導體產業π 多重閘極結構發展之趨勢，^，包切錯通道 :及焉介電常數問極介電層之全新三維金屬閉極結構201125105 VI. Description of the Invention: [Technical Field] The present invention relates to a complementary metal oxide semiconductor (CM〇s), and more particularly to a three-dimensional multiple gate complementary metal oxide semiconductor and its maker . 〃 [Prior Art] According to the miniature size of complementary metal oxide semiconductor (CM0S), it can bring two major advantages, one is the improvement of component performance, and the other is the reduction of power consumption. However, this trend has now reached its limit, and copper interconnects in components have caused problems with crosstalk, power dissipation, and resistance-capacitance (Rc) delay. In general, the size reduction of the complementary CMOS is to optimize the key gate oxide layer in a way that reduces the thickness. However, it is no longer possible to enter the nano node 'the traditional sulphur dioxide. By achieving a good channel control capability by continuously reducing the thickness, its excessive = leakage current will make the size down to become unsustainable, although there is a scheme using yttrium oxynitride (Si0N), but its limited introduction Electrical system = can not effectively extend the evolution of complementary MOS semiconductors. At present, major complementary MOS manufacturers have tried different directions to achieve improvement of component characteristics. For example, adding local or comprehensive strain structure The strain force changes the channel density in the channel to increase the carrier transmission speed to improve the component performance. However, the strain technique alone can continue to achieve the expected 201125105 effect of 45nm or less. The introduction of a high dielectric constant dielectric and a stable work function gate to the genus layer, since the charged carrier can penetrate the dielectric by tunneling to form a leakage current, and a high dielectric constant dielectric is introduced. Replacing the '-·charge, i 〇 2 or S i 0N becomes one of the feasible solutions to reduce leakage current and achieve equivalent capacitance to control the channel switch. In addition, some manufacturers have changed the 〇 di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di di 。 。 。 。 。 。 。 。 。 。 For example, Infineon Technologies has published a multi-f fy1 field-effect transistor technology that is one of the solutions to many challenges in the future. On integrated circuits that require a small number of functions, the power consumed by today's Planar single-gate is much smaller. In a demonstration of this new technology, Infineon's researchers tested the new 65nm multi-gate field-effect transistor architecture, the world's first high-complexity circuit, and the current single-gate technology. Compared to products that produce the same function and performance, the area is almost 30% smaller. 'The quiescent current of this new transistor is one tenth of the previous one. According to the researchers' calculations, compared with the 65nm technology currently used in the production process, such quiescent current will increase the energy use efficiency and battery life of the adopted type of shattering by about one time. (Technology of 32nm and below) will further increase the proportion of large towels. · 201125105 The 65nm circuit tested by Ying Lingling researchers includes more than 3,000 active transistors. Many of the results confirm that the three-dimensional space multiple gate technology and the various mature technologies of today are excellent, but in the same variety In terms of function, the energy consumed is only the traditional plane closed-half - in the future technology generation, this advantage will be more and more important. So far, '(4) there are many patents for complementary MOS semiconductors with multiple difficult structures, so I won’t go into details here, and the patent on the three-dimensional gate-complementary MOS semi-conductor’s invention, such as the Republic of China’s invention, Source/body single-contact and side-wrap (4) vertical type gold-oxygen half-field effect transistor and its manufacturing method" and American (4) 7378309 "Wh〇d〇ffabricatlngl〇calinterc〇nnects〇n awhcon-germanium 3DCM〇s As shown in the patents, all = re-question of the polar structure. In other words, the three-dimensional multi-closed-complementary two-H structure is obviously the future development of the semiconductor industry. [The content of the invention] The main purpose of the supplement is to provide a three-dimensional multi-interpole mutual method, which not only conforms to the semiconductor industry. The trend of the development of the gate structure of the 隹, 隹, 夕, and the full-dimension open-structure is comparable to that of the m/PMGS, and the drive current mobility is more impressive. For the purpose of the foregoing, the present invention provides a seed-type A-pole complementary MOS semiconductor comprising a substrate; a 201125105 isolation layer is formed on the surface of the insulating layer A, a plurality of The pole 'is vertically disposed on the stone eve, and the fin 'a stone-shaped channel layer' is formed on the outer side of the stone-shaped channel layer, and an H-constant dielectric layer is formed on the (four) sheet 1 wrong object. Heat treated, shaped top. A dielectric constant gate dielectric layer The isolation layer is buried in the oxide layer. The protective layer is made of tantalum nitride. The M+-first hard mask layer is formed on each of the gates and the surface of the spacer layer to form a gold step further. Further, the surface of the protective layer is further a gate. Further, the first hard-shielding exhibition is performed by an #AL ΛΙ , , .惫 'Ming is provided - a three-dimensional multi-gate complementary gold milk + conductor method, yak s s, supplementary gold half 埸 4 thunder ... ... less includes: ^ provides a Korean-style thousand-effect transistor structure,兮锉, ^, 4 type + field effect transistor structure consists of a ruthenium substrate, formed on the ruthenium substrate, 3 ❹矣...* isolation layer and vertical set at the end · material m main, b) deposit a protective layer The 矽 fin top brown ' c) is deposited on the surface of the edge layer by the hard god and then patterned, forming a first mask layer, d) heat treatment to form a sacrificial oxide layer; e) removing the outer side wall Separately forming a sacrificial oxide layer on the outside of the Shixi revolving piece; f) outside each layer 桕& ^8, layer, S) opening on the outer side of each of the 矽锗 channels# a gate dielectric layer; h) depositing a metal 201125105 i) etching and patterning the gate layer of the metal gate layer on the surface of each of the gate and the isolation layer. Further, the deposition is performed by chemical vapor deposition, and the etching and patterning is performed by a reactive ion etching machine to perform patterning to the etch stop layer. Further, the heat-treated square gasification layer is sulphur dioxide. Further, each of the sacrificial oxide layers is removed using a diluent. The thermal oxidation treatment, the sacrificial hydrogen acid or the buffer oxide layer, the insect soil, and the shovel are formed by the insect crystal growth method on the outer side of each of the Shi Xi Zhao tablets. Into the ground system, an atomic deposition technique is used to form a high dielectric constant gate dielectric layer on each side of the channel. Further, the method of deposition is a system of chemical vapor deposition, and the method of '(4), ® is etched, patterned by an reactive ion (4), and patterned to an etch stop layer. [Embodiment] The following is a second preferred embodiment of the present invention, and further detailed description with reference to the following figures: First, as shown in the accompanying drawings, a multi-gate gate of a preferred embodiment of the present invention is shown. The complementary MOS 1G includes a shi shi base 2, an isolation layer 13 and a plurality of gates 14. The isolation layer 13 is formed by embedding an oxide layer (Buried Oxide, 201125105 BOX) on the surface of the crucible substrate 12, and is an insulating layer to reduce parasitic capacitance. Each of the gates 14' includes a fin fin (Si_fin) 22, which is vertically disposed on the surface of the insulating layer 14 (the above fin-shaped half field effect transistor structure), and a channel layer (SiGe channel) 24 is formed. Outside the yoke sheet 22, a high dielectric constant (Hi_K) gate dielectric layer 26' is formed on the outside of the shovel layer 5, a protective layer 28, and a thermal treatment. The material of the nitride nitride (siNx) is formed on the top of the fin fin 22, the tantalum channel layer 24 and the high dielectric constant gate dielectric layer 26. In addition, the two-dimensional multiple-gate complementary MOS device further includes a first hard mask layer 15 which is erbium dioxide and is etched on the surface of the protective layer 28, and a gate metal layer 16 is formed on each layer. The gate 14 and the surface of the isolation layer 13 are provided. In detail, as shown in FIG. 2, the three-dimensional multiple gate complementary gold oxide semiconductor 10 is manufactured as follows: As shown in FIG. 3, the first step 110 provides a fin half field effect transistor (7), structure. 30: The bonded half field effect transistor structure 30 comprises a germanium substrate 12, an isolation layer 13 formed on the surface of the germanium substrate 12, and a plurality of fins 22 disposed perpendicularly on the surface of the insulating layer 13. A second step 120 deposits a protective layer 28 at the top end of the samarium fins 22 of the protective layer 28 and is heat treated. The third step 13G is deposited on the surface of the protective layer 28 and is left to form a first hard mask layer 15 : deposition is performed by chemical vapor deposition (Chemical Vap〇r Dep〇siti〇n, cvd) And the rhyme and patterning are etched and patterned into an Etch Stop Uyer using a Reactive 丨on Etcher (R i E ). As shown in FIG. 4, the fourth step 14 is performed by heat treatment, so that the outer sidewalls of each of the arc fins 22 are separated into a sacrificial oxide layer 31: a heat treatment process is performed, and the sacrificial oxide layer 31 is two. Oxidation As shown in FIG. 5, the fifth step 15 removes each of the sacrificial oxide layers 30: using diluted hydrofluoric acid (DUutedHF, qing) or buffered oxide (4) agent (HF+NH4F, position) to remove each The sacrificial oxide layer 31 forms a recessed portion on the outer side of the fin fin 22. The sixth step (10) shown in FIG. 6 forms a channel layer 24 in the recessed portion 32 outside each of the webs 22: The epitaxial growth method (Ep) increases the formation of the channel layer 24 in each of the recessed portions 32. The seventh step 170 forms a dielectric constant dielectric layer 26 on the outer side of each of the outer channel layers 24. : using the atomic deposition technique (At_ Layer Depositi〇n, or chemical vapor deposition on the outside of the dicing channel layer 24 to form a dielectric layer 26. The eighth step 180 is to deposit the gate metal layer 16 on each of the pedestals 201125105 14 and the surface of the isolation layer 13. Engraved, = the ninth step (10) is attached to the surface of the metal layer Button. 'The chemical vapor deposition technique and reactive ion eclipse are also used to enter (4), the patterned recording stop layer. The etch stop layer is mainly used to control the etching degree. The straw is the three-dimensional multiple gate of the present invention. The extremely complementary type of gold oxide 1 〇 can at least achieve the following characteristics: The three-dimensional multi-gate complementary MOS semiconductor industry in the future will move towards the development of three-dimensional and multi-interpole structure, and improve the energy efficiency of portable devices. The battery life " effect, and high dielectric constant (Hi_" open pole will be in the mainstream of less than 65 CMOS technology. In addition, : = compared to #Ν_ of the channel has phase = drive current mobility' Protection of each of the interpoles (4) 'In the private use of dilute hydrogen acid or buffer oxide layer engraving agent to remove the reduced layer 3G and (4) metal layer off the sealing pin, from the above, the three-dimensional gold provided by the present invention : Semiconductors and their methods, which not only meet the trend of the development of π multiple gate structures in the semiconductor industry, ^, the gap-cutting channel: and the new three-dimensional metal closed-pole structure of the dielectric constant dielectric layer
☆較於習％ N/PM〇s之石夕通道可具有更高之驅動電流 流動性，實用價值甚高。 'L 201125105 雖然本發明已以輕 平乂佳貝％例揭路如上，然其並非 用以限定本發明，任何 ’、、、’、 7 “、、，e此項技藝者，在不脫離本 發明之精神和範圍内，者 m ^ ^ ^ 田了作更動與潤飾，因此本發 準。 申明專利乾圍所界定者為 【圖式簡單說明】 圖一係本發明一較佳眘尬/sF + 阁"丄 乂佳貫允例之剖面示意圖。 l施例之製作流程圖。 面示意圖 圖一至圖六係本發明一較 。 杈佳貫轭例製作流程之剖 【主要元件符號說明】 10二維多重閘極互補式金氧半導 U矽基底 13隔離層 14：閘極 15第一硬遮罩層 16閘極金屬層 22矽鰭片 24矽鍺通道層 2 6高介電常數閘極介電層 28保護層 30鳍式半場效電晶體結構 201125105 1 ] 〇提供—鰭式半場效電晶體結構 =冗積保護層於鰭式半場效電晶體結構之㈣片 J30於保護層表 罩層 面沉積並蝕刻圖案化形成第一硬遮 14〇熱處理使石夕鰭片外側壁形成 150移除犧牲氧化層 層☆ Compared with Xi% N/PM〇s, Shishi channel can have higher driving current and high practical value. 'L 201125105 Although the present invention has been disclosed above as a lighter example, it is not intended to limit the present invention, and any skilled person of ',,, ', 7', ', e, does not deviate from this. Within the spirit and scope of the invention, the m ^ ^ ^ field has been modified and retouched, so this is issued. The definition of the patent dry circumference is defined as a simple description of the drawing. Figure 1 is a preferred embodiment of the present invention / sF + 阁"丄乂佳贯例's cross-section diagram. l Production flow chart of the example. Surface diagrams Figure 1 to Figure 6 are a comparison of the present invention. 杈 贯 贯 轭 轭 制作 制作 【 【 【 【 【 【 【 【 【 【 【 【 Two-dimensional multiple gate complementary MOS semi-conductive U 矽 substrate 13 isolation layer 14: gate 15 first hard mask layer 16 gate metal layer 22 矽 fin 24 矽锗 channel layer 2 6 high dielectric constant gate Dielectric layer 28 protective layer 30 fin half field effect transistor structure 201125105 1 ] 〇 provide - fin half field effect transistor structure = redundant protective layer in the fin half field effect transistor structure (four) sheet J30 on the protective layer surface layer Deposition and etching patterning to form a first hard mask 14 heat treatment to make the stone Fins 150 are formed outer sidewall oxide layer is removed sacrificial layer
160於矽鰭片外側形成一矽鍺通道層 170於料通外側形成—高介以㈣極介電 180沉積閘極金屬層於各閘極與隔離層表面 190於該閘極金屬層表面蝕刻圖案化A channel layer 170 is formed on the outer side of the fin fin to form a drain layer on the outside of the material pass—a high dielectric (IV) pole dielectric 180 deposit gate metal layer is etched on the surface of each gate and isolation layer 190 on the surface of the gate metal layer. Chemical