CN103840001B - 具有额外漏极od增加的高压漏极延伸mosfet - Google Patents
具有额外漏极od增加的高压漏极延伸mosfet Download PDFInfo
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Abstract
一种集成电路包括:具有第一掺杂类型的高压阱,嵌入高压阱中的第一掺杂区和第二掺杂区,第一掺杂区和第二掺杂区具有第二掺杂类型并且通过高压阱中的沟道间隔开;在第一掺杂区和第二掺杂区中形成的源极/漏极区,每个源极/漏极区都具有第二掺杂类型并且比第一掺杂区和第二掺杂区更重度地掺杂;与每个源极/漏极区都间隔开的第一隔离区;和围绕每个源极/漏极区形成环的电阻保护氧化物。本发明公开了具有额外漏极OD增加的高压漏极延伸MOSFET。
Description
技术领域
本发明涉及集成半路及其制造方法,具体而言,涉及金属氧化物半导体晶体管。
背景技术
传统的双扩散漏极(DDD)金属氧化物半导体(MOS)结构(DDDMOS)的击穿电压是有限的。当掺杂物浓度较轻时,规则扩展(rule extension)仅会略微地改进器件击穿电压。另外,在聚酰亚胺栅极下方插入浅沟槽隔离(STI)区将降低接通电阻(通常称为RDS(on))并降低器件的失配性能。
发明内容
为了解决现有技术中存在的问题,根据本发明的一方面,提供了一种集成电路,包括:具有第一掺杂类型的高压阱;嵌入所述高压阱中的第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;形成在所述第一掺杂区和所述第二掺杂区中的源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;第一隔离区,每个所述第一隔离区都与每个所述源极/漏极区间隔开;以及位于所述高压阱上方的电阻保护氧化物,所述电阻保护氧化物围绕每个所述源极/漏极区形成环。
在所述的集成电路中,所述电阻保护氧化物位于设置在所述源极/漏极区和所述隔离区之间的第一掺杂区和第二掺杂区上方。
在所述的集成电路中,所述第一隔离区通过部分所述第一掺杂区和部分所述第二掺杂区与所述源极/漏极区横向间隔开。
在所述的集成电路中,所述电阻保护氧化物的一部分设置在所述源极/漏极区的与所述沟道相对的一侧上。
在所述的集成电路中,每个所述环的一部分位于形成在所述沟道上方的栅极结构上。
在所述的集成电路中,所述电阻保护氧化物部分地覆盖所述第一隔离区。
在所述的集成电路中,所述电阻保护氧化物的端部处于与所述源极/漏极区的端部垂直对准和部分地覆盖所述源极/漏极区的端部中的至少一种。
在所述的集成电路中,所述环是矩形环。
在所述的集成电路中,从所述第一隔离区的边缘到所述源极/漏极区的边缘的第一距离是从多晶硅栅极的端部到所述电阻保护氧化物的终端的第二距离的约0.5至约1.5倍。在一个实施例中,所述第一距离为约0.4μm至约1.2μm,而所述第二距离约为0.8μm。
在所述的集成电路中,击穿电压大于约38伏特。
在所述的集成电路中,第二隔离区通过第三掺杂区与所述第一隔离区间隔开,所述第三掺杂区具有所述第一掺杂类型并且比所述高压阱更重度地掺杂。
在所述的集成电路中,所述第一掺杂类型是n型掺杂物,而所述第二掺杂类型是p型掺杂物。
根据本发明的另一方面,还提供了一种集成电路,包括:具有第一掺杂类型的高压阱;嵌入所述高压阱中的第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;形成在所述第一掺杂区和所述第二掺杂区中的源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;隔离区,每个所述隔离区都与每个所述源极/漏极区间隔开;以及形成窗口的电阻保护氧化物,所述窗口处于与每个所述源极/漏极区对准和部分地覆盖每个所述源极/漏极区中的至少一种。
在所述的集成电路中,所述电阻保护氧化物位于设置在所述源极/漏极区和所述隔离区之间的第一掺杂区和第二掺杂区的上方。
在所述的集成电路中,所述隔离区通过部分所述第一掺杂区和部分所述第二掺杂区与所述源极/漏极区横向间隔开。
在所述的集成电路中,所述窗口由所述电阻保护氧化物的方形环和矩形环中的至少一种形成。
根据本发明的又一方面,提供了一种形成集成电路的方法,包括:形成具有第一掺杂类型的高压阱;在所述高压阱中注入形成第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;在所述第一掺杂区和所述第二掺杂区中形成源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;形成第一隔离区,所述第一隔离区与每个所述源极/漏极区间隔开;以及围绕每个所述源极/漏极区形成电阻保护氧化物的环。
所述的方法还包括:在所述第一掺杂区和所述第二掺杂区设置在所述源极/漏极区和所述隔离区之间的部分上方形成所述电阻保护氧化物。
所述的方法还包括:通过部分所述第一掺杂区和部分所述第二掺杂区使所述第一隔离区与所述源极/漏极区横向间隔开。
附图说明
为了更充分地理解本发明及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1是具有以形成窗口的电阻保护氧化物(RPO)形式的漏极-有源区(OD)增加的实施例DDDMOS器件的俯视图;
图2是图1的实施例DDDMOS器件的截面图;
图3是比较标准DDDMOS器件预期的击穿电压和图1的DDDMOS器件预期的击穿电压的模拟;
图4是示出不具有形成窗口的电阻保护氧化物(RPO)的标准DDDMOS器件相对于图1的实施例DDDMOS器件的晶圆验收测试(WAT)结果的图表;
图5是具有在接触插塞下方形成的硅化物的图1的实施例DDDMOS器件的截面图;
图6是示出的具有某些尺寸的图1的实施例DDDMOS器件的俯视图;
图7是图6的实施例DDDMOS器件的截面图;以及
图8是示出形成图1的实施例DDDMOS器件的方法的流程图。
除非另有说明,不同附图中的相应标号和符号通常指相应部件。绘制附图用于清楚地示出实施例的相关方面而不必成比例绘制。
具体实施方式
下面,详细讨论本发明优选实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅是示例性的,而不用于限制本发明的范围。
参照具体环境中的优选实施例描述本发明,即金属氧化物半导体(MOS)晶体管(例如双扩散漏极MOS(DDDMOS)等)。然而,本发明的发明构思也可以适用于集成电路或其他半导体结构。
共同参照图1和图2,示出了实施例DDDMOS器件10。如下文将要充分描述的,相对于传统的DDDMOS器件,实施例DDDMOS器件10具有高击穿电压。实施例DDDMOS器件10还具有与传统的DDDMOS器件相当的接通电阻(通常用RDS(on)表示)和失配。
如图1和图2所示,DDDMOS器件10包括高压阱12,高压阱12具有第一掺杂类型(例如n型)。第一掺杂区14和第二掺杂区16通过注入工艺形成并且嵌入高压阱12中。在一实施例中,第一掺杂区14和第二掺杂区16是轻掺杂漏极区。第一掺杂区14和第二掺杂区16具有第二掺杂类型(例如p型)并且通过高压阱12中的沟道18彼此间隔开。沟道18设置在栅极20的下方。在一实施例中,栅极20由多晶硅或另一合适的栅极材料形成。
仍参照图1和图2,源极/漏极区22形成在第一掺杂区14和第二掺杂区16中。每个源极/漏极区22均具有第二掺杂类型(例如p型)并且比第一掺杂区14和第二掺杂区16更重度地掺杂。通过使用图2中的P+符号表示第一掺杂区14和第二掺杂区16的更重度的掺杂。如图1所示,栅极20、第一掺杂区14和第二掺杂区16以及源极/漏极区22大体上建立DDDMOS器件10的有源区(OD)。
如图1和图2所示,每个第一隔离区24与每个源极/漏极区22都间隔开。在一实施例中,第一隔离区24包括嵌入一部分第一掺杂区14和第二掺杂区16和一部分高压阱12中的浅沟槽隔离(STI)区。换言之,第一隔离区24横跨过第一掺杂区14和第二掺杂区16与高压阱12之间的界面。在一实施例中,第一隔离区24通过部分第一掺杂区14和部分第二掺杂区16与源极/漏极区22横向间隔开。
仍参照图1和图2,电阻保护氧化物(RPO)26围绕每个源极/漏极区22形成环。如图1所示,电阻保护氧化物26的环限定出一般与每个源极/漏极区22对准或部分覆盖每个源极/漏极区22的窗口28或开口。在一实施例中,电阻保护氧化物26位于设置在源极/漏极区22和第一隔离区24之间的第一掺杂区14和第二掺杂区16的上面。在一实施例中,电阻保护氧化物26部分覆盖第一隔离区24。在一实施例中,电阻保护氧化物26的一部分设置在源极/漏极区22的与沟道18相对的一侧上。
如图2所示,在一实施例中,每个电阻保护氧化物环26的一部分都位于设置在沟道18之上的栅极20的上面。另外,在一实施例中,电阻保护氧化物26的端部与源极/漏极区22的端部垂直对准或部分覆盖源极/漏极区22的端部,如图2所示。此外,在一实施例中,利用电阻保护氧化物26形成的环26是方形环、矩形环等。应该认识到,在其他实施例中环可以具有其他合适的形状(例如圆形、椭圆形、三角形或另一能形成窗口的闭合多边形)。
参照图2,在一实施例中,第二隔离区30通过第三掺杂区32与第一隔离区24间隔开。第三掺杂区32具有第一掺杂类型(例如n型)并且比高压阱12更重度地掺杂。利用图2中的N+符号表示第三掺杂区32的更重度的掺杂。
现参照图3,提供了比较标准DDDMOS器件10(标记为STD)预期的击穿电压(即30V)和图1的实施例DDDMOS器件10(标记为S2增加)预期的击穿电压(例如38.2V)的模拟34。如图所示,实施例DDDMOS器件10的击穿电压明显更高。
现参照图4,提供了图表36,图表36示出了不具有(W/O)电阻保护氧化物(RPO)的标准DDDMOS器件和图1的实施例DDDMOS器件10的晶圆验收测试(WAT)结果。注意到,在图4中包括了图1中标记的各种尺寸(即W、L、B、S1、D和S2)的数值(以μm计)。另外,提供了对称和不对称的PMOS器件的结果。
现参照图5,描述了具有接触插塞38的实施例DDDMOS器件10。如图所示,硅化物层40形成在或位于外侧接触插塞38和源极/漏极区22之间以及中心接触插塞38和栅极20之间。如图所示,电阻保护氧化物26有利地阻止或防止硅化物40在部分邻近的第一掺杂区14和第二掺杂区16上方形成。
现参照图6和图7,实施例DDDMOS器件10具有多个标记的尺寸,即A和B。一般而言,A是从多晶硅栅极20的端部到电阻保护氧化物26的终端的距离,而B是从第一隔离区24的边缘到源极/漏极区22的边缘的距离。在一实施例中,B是A的约0.5至约1.5倍。举例来说,如果A是大约0.8μm,则B是在约0.4μm至约1.2μm之间。
现参照图8,提供了示出形成图1的实施例DDDMOS器件10的方法42的流程图。在框44中,形成具有第一掺杂类型的高压阱12。在框46,将第一掺杂区14和第二掺杂区16嵌入高压阱12中。如上所述,第一掺杂区14和第二掺杂区16具有第二掺杂类型并通过高压阱12中的沟道18间隔开。
在框48中,在第一掺杂区14和第二掺杂区16中形成源极/漏极区22。每个源极/漏极区22都具有第二掺杂类型并且比第一掺杂区14和第二掺杂区16更重度地掺杂。在框50中,形成第一隔离区24。第一隔离区24与每个源极/漏极区22都间隔开。
在框52中,围绕每个源极/漏极区22形成电阻保护氧化物26的环26。通过以这种方式形成环26从而产生窗口28(图1),相对于传统的DDDMOS器件,图1的DDDMOS器件10具有高击穿电压。另外,实施例DDDMOS器件10还具有与传统的DDDMOS器件相当的接通电阻RDS(on)和失配。
一种实施例集成电路包括:具有第一掺杂类型的高压阱;嵌入高压阱中的第一掺杂区和第二掺杂区,第一掺杂区和第二掺杂区具有第二掺杂类型并且通过高压阱中的沟道间隔开;形成在第一掺杂区和第二掺杂区中的源极/漏极区,每个源极/漏极区都具有第二掺杂类型并且比第一掺杂区和第二掺杂区更重度地掺杂;与每个源极/漏极区都间隔开的第一隔离区;和位于高压阱上方的电阻保护氧化物,该电阻保护氧化物围绕每个源极/漏极区形成环。
一种实施例集成电路包括:具有第一掺杂类型的高压阱;嵌入高压阱中的第一掺杂区和第二掺杂区,第一掺杂区和第二掺杂区具有第二掺杂类型并且通过高压阱中的沟道间隔开;在第一掺杂区和第二掺杂区中形成的源极/漏极区,每个源极/漏极区都具有第二掺杂类型并且比第一掺杂区和第二掺杂区更重度地掺杂;与每个源极/漏极区都间隔开的隔离区;和形成窗口的电阻保护氧化物,该窗口处于与每个源极/漏极区对准和部分地覆盖每个源极/漏极区中的至少一种。
一种形成集成电路的实施例方法包括:形成具有第一掺杂类型的高压阱;在高压阱中嵌入第一掺杂区和第二掺杂区,第一掺杂区和第二掺杂区具有第二掺杂类型并且通过高压阱中的沟道间隔开;在第一掺杂区和第二掺杂区中形成源极/漏极区,每个源极/漏极区都具有第二掺杂类型并且比第一掺杂区和第二掺杂区更重度地掺杂;形成第一隔离区,第一隔离区与每个源极/漏极区都间隔开;以及围绕每个源极/漏极区形成电阻保护氧化物的环。
虽然本发明提供了示例性实施例,但是不应该以限制的含义解释本说明书。在参考了本说明书的基础上,这些示例性实施例的各种变化和组合以及其他实施例对于本领域的技术人员是显而易见的。因此,所附的权利要求意图涵盖任何这种变化或实施例。
Claims (16)
1.一种集成电路,包括:
具有第一掺杂类型的高压阱;
嵌入所述高压阱中的第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;
形成在所述第一掺杂区和所述第二掺杂区中的源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;
第一隔离区,每个所述第一隔离区都与每个所述源极/漏极区间隔开,所述第一隔离区比所述源极/漏极区距离所述沟道较远;以及
位于所述高压阱上方的电阻保护氧化物,所述电阻保护氧化物分别围绕每个所述源极/漏极区而分别形成单环,
其中,所述电阻保护氧化物的一部分位于设置在所述源极/漏极区和所述第一隔离区之间的所述第一掺杂区和所述第二掺杂区上方,所述电阻保护氧化物的另一部分位于形成在所述沟道上方的栅极结构上。
2.根据权利要求1所述的集成电路,其中,所述第一隔离区通过部分所述第一掺杂区和部分所述第二掺杂区与所述源极/漏极区横向间隔开。
3.根据权利要求1所述的集成电路,其中,所述电阻保护氧化物的一部分设置在所述源极/漏极区的与所述沟道相对的一侧上。
4.根据权利要求1所述的集成电路,其中,所述电阻保护氧化物部分地覆盖所述第一隔离区。
5.根据权利要求1所述的集成电路,其中,所述电阻保护氧化物的端部处于与所述源极/漏极区的端部垂直对准和部分地覆盖所述源极/漏极区的端部中的至少一种。
6.根据权利要求1所述的集成电路,其中,所述环是矩形环。
7.根据权利要求1所述的集成电路,其中,从所述第一隔离区的边缘到所述源极/漏极区的边缘的第一距离是从多晶硅栅极的端部到所述电阻保护氧化物的终端的第二距离的0.5至1.5倍。
8.根据权利要求7所述的集成电路,其中,所述第一距离为0.4μm至1.2μm,而所述第二距离为0.8μm。
9.根据权利要求1所述的集成电路,其中,击穿电压大于38伏特。
10.根据权利要求1所述的集成电路,其中,第二隔离区通过第三掺杂区与所述第一隔离区间隔开,所述第三掺杂区具有所述第一掺杂类型并且比所述高压阱更重度地掺杂。
11.根据权利要求1所述的集成电路,其中,所述第一掺杂类型是n型掺杂物,而所述第二掺杂类型是p型掺杂物。
12.一种集成电路,包括:
具有第一掺杂类型的高压阱;
嵌入所述高压阱中的第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;
形成在所述第一掺杂区和所述第二掺杂区中的源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;
隔离区,每个所述隔离区都与每个所述源极/漏极区间隔开,并且每个所述隔离区比每个所述源极/漏极区距离所述沟道较远;以及
形成窗口的电阻保护氧化物,所述窗口处于与每个所述源极/漏极区对准和部分地覆盖每个所述源极/漏极区中的至少一种,并且所述窗口分别围绕每个所述源极/漏极区而分别形成单环,
其中,所述电阻保护氧化物的一部分位于设置在所述源极/漏极区和所述隔离区之间的第一掺杂区和第二掺杂区的上方,所述电阻保护氧化物的另一部分位于形成在所述沟道上方的栅极结构上。
13.根据权利要求12所述的集成电路,其中,所述隔离区通过部分所述第一掺杂区和部分所述第二掺杂区与所述源极/漏极区横向间隔开。
14.根据权利要求12所述的集成电路,其中,所述窗口由所述电阻保护氧化物的方形环和矩形环中的至少一种形成。
15.一种形成集成电路的方法,包括:
形成具有第一掺杂类型的高压阱;
在所述高压阱中注入形成第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区具有第二掺杂类型并且通过所述高压阱中的沟道间隔开;
在所述第一掺杂区和所述第二掺杂区中形成源极/漏极区,每个所述源极/漏极区都具有所述第二掺杂类型并且比所述第一掺杂区和所述第二掺杂区更重度地掺杂;
形成第一隔离区,所述第一隔离区与每个所述源极/漏极区间隔开,并且所述第一隔离区比所述源极/漏极区距离所述沟道较远;以及
分别围绕每个所述源极/漏极区而分别形成电阻保护氧化物的单环,
其中,所述电阻保护氧化物的一部分位于设置在所述源极/漏极区和所述第一隔离区之间的所述第一掺杂区和所述第二掺杂区上方,所述电阻保护氧化物的另一部分位于形成在所述沟道上方的栅极结构上。
16.根据权利要求15所述的方法,还包括通过部分所述第一掺杂区和部分所述第二掺杂区使所述第一隔离区与所述源极/漏极区横向间隔开。
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