CN106206734B - 一种超结mos晶体管 - Google Patents
一种超结mos晶体管 Download PDFInfo
- Publication number
- CN106206734B CN106206734B CN201610542698.9A CN201610542698A CN106206734B CN 106206734 B CN106206734 B CN 106206734B CN 201610542698 A CN201610542698 A CN 201610542698A CN 106206734 B CN106206734 B CN 106206734B
- Authority
- CN
- China
- Prior art keywords
- type
- well region
- type column
- column
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001235 sensitizing effect Effects 0.000 claims description 32
- 238000000407 epitaxy Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 12
- 239000002245 particle Substances 0.000 abstract description 12
- 230000005855 radiation Effects 0.000 abstract description 9
- 230000003014 reinforcing effect Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 29
- 238000000034 method Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种超结MOS晶体管,其特征在于,包括:外延层,外延层中交替设有多根P型立柱和多根N型立柱,其中,每相邻两根P型立柱之间的区域为一根N型立柱;多个表面MOS结构,包括:P阱区、N阱区、栅氧化层和栅极;其中,每个表面MOS结构的敏感区域均与P型立柱的中轴线错位;每个表面MOS结构的敏感区域均与N型立柱的中轴线错位;其中,敏感区域包括:栅氧化层与外延层交界的界面区域。本发明提供的晶体管,用以解决现有技术中SJ‑MOSFET应用在空间领域时,存在易出现SEB和SEGR,导致失效的技术问题。实现了单粒子辐射加固的效果,进而提高器件在空间应用时的可靠性的技术效果。
Description
技术领域
本发明涉及半导体领域,尤其涉及一种超结MOS晶体管。
背景技术
在功率半导体领域内,以垂直双扩散工艺形成的纵向金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)称为VDMOSFET,简称VDMOS。对于传统的VDMOS,一般通过增大外延层厚度和降低外延层掺杂浓度的方式提高击穿电压。超结金属氧化物半导体场效应晶体管(Super Juction Metal OxideSemiconductor Field Effect Transistor,SJ-MOSFET)是VDMOS器件的一种改进结构,如图1所示,通过在外延层内加入交替的P-N结构,形成P型立柱和N型立柱,使器件处于阻断状态时,外延层内的纵向电场几乎为恒值,这使器件的导通电阻对击穿电压的依赖关系大大降低,从而降低器件的通态损耗。因此,该结构在高击穿电压的器件中得到广泛的应用。
当SJ-MOSFET应用在空间领域时,由于空间环境中存在持续不断的重离子辐射,当重离子轰击到硅片表面后,在其运动路径上会产生大量的电子空穴对,可使器件发生单粒子效应而失效。以N沟道SJ-MOSFET为例,当处于阻断状态时,其体内电场如图1中箭头所示,硅片受到轰击后,电子空穴对中的电子会从漏极流出,而空穴会在空间电场的作用下向阱区及栅介质层表面下方流动。一方面,当流入阱区的空穴电流过大,使阱区与源掺杂区结表面压降超过0.7V时,源掺杂区-阱区-外延层组成的寄生三极管将开启,在外部条件允许的前提下,该寄生三极管会发生二次击穿,使电流密度过度集中导致器件发生单粒子烧毁(Single Event Burnout,SEB)。另一方面,若过多的空穴堆积在Si/SiO2界面处,则等效于在栅介质层上附加一个瞬态电场,导致栅介质层内电场超过临界击穿电场,发生栅介质层击穿,即发生单粒子栅穿(Single Event Gate Rupture,SEGR)。
也就是说,现有技术中的SJ-MOSFET应用在空间领域时,存在易出现SEB和SEGR,导致失效的技术问题。
发明内容
本发明通过提供一种超结MOS晶体管,解决了现有技术中的SJ-MOSFET应用在空间领域时,存在易出现SEB和SEGR,导致失效的技术问题。
一方面,为解决上述技术问题,本发明提供了如下技术方案:
一种超结MOS晶体管,所述晶体管包括:
外延层,所述外延层中交替设有多根P型立柱和多根N型立柱,其中,每相邻两根P型立柱之间的区域为一根N型立柱;
多个表面MOS结构,所述表面MOS结构包括:P阱区、N阱区、栅氧化层和栅极;
其中,每个所述表面MOS结构的敏感区域均与所述P型立柱的中轴线错位;每个所述表面MOS结构的敏感区域均与所述N型立柱的中轴线错位;其中,所述敏感区域包括:所述栅氧化层与所述外延层交界的界面区域。
可选的,所述敏感区域还包括:所述P阱区的边界与所述外延层的表面交界的区域。
可选的,每个所述表面MOS结构的栅氧化层均位于所述P型立柱和所述N型立柱的交界处;其中,以一个P型立柱和一个N型立柱为一对立柱,任一对立柱内有奇数个所述表面MOS结构。
可选的,所述外延层位于N+型衬底上,所述外延层为N型外延层;所述表面MOS结构包括:位于所述P型立柱顶端的第一P+阱区、位于所述第一P+阱区顶端的第一N阱区、位于所述N型立柱顶端的P阱区、位于所述P阱内的第二P+阱区、位于所述第二P+阱区顶端的第二N阱区、栅氧化层和栅极;其中,所述栅氧化层连接所述第一N阱区表面和所述第二N阱区表面;所述晶体管的金属源极连接所述第一P+阱区表面、所述第二P+阱区表面、所述第一N阱区表面和所述第二N阱区表面;所述晶体管的漏极为所述N+型衬底。
可选的,所述多个表面MOS结构中,部分表面MOS结构的栅氧化层位于所述P型立柱和所述N型立柱的交界处。
可选的,所述外延层为N型外延层;所述界面区域具体为:所述栅氧化层与所述外延层的N型区交界的区域。
本申请实施例中提供的一个或多个技术方案,至少具有如下技术效果或优点:
本申请实施例提供的超结MOS晶体管,改变SJ-MOSFET的表面MOS结构的数量和/或分布,以使表面MOS结构的敏感区域均与所述P型立柱和所述N型立柱的中轴线错位,即使得外延层中横向电场最弱的区域与表面MOS结构易发生SEB和/或SEGR的敏感区形成错位,以实现单粒子辐射加固的目的,进而提高器件在空间应用时的可靠性。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为背景技术中SJ-MOSFET的剖面图;
图2为对背景技术中SJ-MOSFET外延层内横向电场分布示意图;
图3为本申请实施例中SJ-MOSFET的剖面图一;
图4为图3所示SJ-MOSFET外延层内横向电场分布示意图;
图5为本申请实施例中SJ-MOSFET的剖面图二。
具体实施方式
本申请实施例通过提供一种超结MOS晶体管,解决了现有技术中的
SJ-MOSFET应用在空间领域时,存在易出现SEB和SEGR,导致失效的技术问题。实现了单粒子辐射加固的,进而提高器件在空间应用时的可靠性的技术效果。
为解决上述技术问题,本申请实施例提供技术方案的总体思路如下:
本申请提供一种超结MOS晶体管,所述晶体管包括:
外延层,所述外延层中交替设有多根P型立柱和多根N型立柱,其中,每相邻两根P型立柱之间的区域为一根N型立柱;
多个表面MOS结构,所述表面MOS结构包括:P阱区、N阱区、栅氧化层和栅极;
其中,每个所述表面MOS结构的敏感区域均与所述P型立柱的中轴线错位;每个所述表面MOS结构的敏感区域均与所述N型立柱的中轴线错位;其中,所述敏感区域包括:所述栅氧化层与所述外延层交界的界面区域。
本申请实施例提供的超结MOS晶体管,改变SJ-MOSFET的表面MOS结构的数量和/或分布,以使表面MOS结构的敏感区域均与所述P型立柱和所述N型立柱的中轴线错位,即使得外延层中横向电场最弱的区域与表面MOS结构易发生SEB和/或SEGR的敏感区形成错位,以实现单粒子辐射加固的目的,进而提高器件在空间应用时的可靠性。
为了更好的理解上述技术方案,下面将结合具体的实施方式对上述技术方案进行详细说明,应当理解本发明实施例以及实施例中的具体特征是对本申请技术方案的详细的说明,而不是对本申请技术方案的限定,在不冲突的情况下,本申请实施例以及实施例中的技术特征可以相互组合。
在本实施例中,提供了一种超结MOS晶体管,请参考图3,如图3所示,所述晶体管包括:
外延层,所述外延层中交替设有多根P型立柱1和多根N型立柱2,其中,每相邻两根P型立柱1之间的区域为一根N型立柱2;
多个表面MOS结构,所述表面MOS结构包括:P阱区3、N阱区4、栅氧化层5和栅极6;
其中,每个所述表面MOS结构的敏感区域均与所述P型立柱1的中轴线错位;每个所述表面MOS结构的敏感区域均与所述N型立柱2的中轴线错位;其中,所述敏感区域包括:所述栅氧化层5与所述外延层交界的界面区域。
在具体实施过程中,所述外延层可以是N型外延层,也可以是P型外延层,在本实施例中不作限制。
下面,分别介绍所述超结MOS晶体管辐射加固的原理和所述超结MOS晶体管的结构。
首先,介绍所述超结MOS晶体管辐射加固的原理。
考虑到SJ-MOSFET器件自身存在一个内建横向电场,可以用于疏导粒子产生的电子或空穴电流远离器件敏感区域。具体如图2所示,为现有SJ-MOSFET的电场分布图,可以看出漂移区内PN结处,即P型立柱和N型立柱交界处,水平电场最强,越靠近N柱中心,水平电场越弱,N型立柱中心处水平电场为0。当电子空穴对产生在PN结附近时,空穴电流会沿着横向电场迅速的流入P型立柱,随后从P型立柱中心区域向表面流动,直至流出源极,这个过程不会引起单粒子效应的发生。而当电子空穴对产生在N型立柱中线附近时,空穴受到的横向电场大大减弱,空穴电流将直接从N型立柱中心区域流至栅介质层下方,使器件发生单粒子效应。
同理,P型立柱的中心处水平电场也为0,电场强度最弱。
因此,SJ-MOSFET抑制器件发生单粒子效应的主要矛盾为,横向电场最弱的区域反而对应表面的敏感区,使其疏导作用降低,很难起到单粒子加固的目的。故本申请将器件表面暴露在N型区的栅氧区域以及表面P阱的边界等器件的敏感区域与横向电场最弱的N型立柱中线及P型立柱中线错位,使得敏感区域不易聚集电子或空穴电流,能实现单粒子辐射加固的目的,进而提高器件在空间应用时的可靠性。
在本申请实施例中,所述敏感区域可以包括:所述栅氧化层5与所述外延层交界的界面区域和所述P阱区的边界与所述外延层的表面交界的区域。
当所述外延层为N型外延层时,所述栅氧化层5与所述外延层交界的界面区域具体可以为:所述栅氧化层5与所述外延层的N型区交界的区域。当然,也可以设置所述栅极6覆盖的Si/SiO2界面均为所述敏感区域。
举例来讲,所述敏感区域可以为图3中菱形分布的区域。
接下来,介绍所述超结MOS晶体管的结构。
下面主要以N型外延层为例来介绍所述超结MOS晶体管的结构,P型外延层的实现方案与之类似,不再累述。
本申请提供的SJ-MOSFET的核心在于P型立柱与N型立柱的排列(交替)方式与表面MOS结构的排列方式不同,从而形成电场错位,以增强内建电场的疏导作用。而SJ-MOSFET具体的结构可以有多种实现方案,只需满足每个所述表面MOS结构的敏感区域均与所述P型立柱1和所述N型立柱2的中轴线错位,下面提供三种实例,当然,本发明方案的结构不限于以下三种:
第一种,表面MOS结构均设置在P型立柱1和N型立柱2的交界处。
即如图3所示,每个所述表面MOS结构301的栅氧化层5均位于所述P型立柱1和所述N型立柱2的交界处;其中,以一个P型立柱和一个N型立柱为一对立柱,任一对立柱内有奇数个所述表面MOS结构。
具体来讲,如图3所示,所述外延层位于N+型衬底上,所述外延层为N型外延层;
所述表面MOS结构包括:位于所述P型立柱1顶端的第一P+阱区、位于所述第一P+阱区顶端的第一N阱区、位于所述N型立柱2顶端的P阱区、位于所述P阱内的第二P+阱区、位于所述第二P+阱区顶端的第二N阱区、栅氧化层5、栅极6、金属源极302和漏极303;
其中,所述栅氧化层5连接所述第一N阱区表面和所述第二N阱区表面;所述金属源极302连接所述第一P+阱区表面、所述第二P+阱区表面、所述第一N阱区表面和所述第二N阱区表面;所述漏极303为所述N+型衬底。
结合图4可见,通过设置间隔的表面MOS结构P阱与P型立柱对准,使电场形成了错位。而未对应P型立柱的表面P阱内采用了深P+源极接触,调整了表面处电场结构,使得N型立柱中间水平电场最弱区域与敏感区域错位,使得黑点所标注敏感区域的电子和空穴在电场作用下疏导,从而实现最佳的单粒子加固作用。
第二种,部分表面MOS结构设置在N型立柱2的区域。
即所述多个表面MOS结构中,部分表面MOS结构的栅氧化层位于所述P型立柱和所述N型立柱的交界处。
如图5所示,除了有与图3类似的设置在P型立柱和N型立柱交界处的表面MOS结构501外,还在N型立柱的表面设置有仅位于N型立柱2区域的2个表面MOS结构502,并通过控制表面MOS结构的数量,实现与N型立柱2的中轴线错位。
当然,在具体实施过程中,还可以增加N型立柱2区域的表面MOS结构数量,只需要保证与N型立柱2的中轴线错位,在此不作限制。
当然,基于同一原理,也可以在P型立柱1区域内设置多个表面MOS结构,具体设置方案与在N型立柱2区域内设置表面MOS结构的方案类似,在此不再累述。
第三种,二维排布。
在具体实施过程中,还可以采用二维排布,以图3为例,即不仅图3所述剖面排列设置有表面MOS结构,沿正对图3方向上也可以排列设置表面MOS结构,只需保证表面MOS结构的敏感区域与P型立柱1和N型立柱2的中轴线错位,在本实施例中不作限制。
需要说明的是,由于对于超结MOS晶体管,主要工艺难点在于体内P型立柱与N型立柱的形成,而增大表面MOS结构密度及调整其结构并不显著增大该器件的制造工艺难度。因此,本申请提供的超结MOS晶体管的电场导流技术的应用更为简单,工艺成本也低。
具体来讲,改变SJ-MOSFET的表面MOS结构的数量和/或分布,以使表面MOS结构的敏感区域均与所述P型立柱和所述N型立柱的中轴线错位,通过调整超结结构体内电场分布,减少了指向表面敏感区域的电场数量,能有效增加器件的可靠性。
上述本申请实施例中的技术方案,至少具有如下的技术效果或优点:
本申请实施例提供的超结MOS晶体管,改变SJ-MOSFET的表面MOS结构的数量和/或分布,以使表面MOS结构的敏感区域均与所述P型立柱和所述N型立柱的中轴线错位,即使得外延层中横向电场最弱的区域与表面MOS结构易发生SEB和/或SEGR的敏感区形成错位,以实现单粒子辐射加固的目的,进而提高器件在空间应用时的可靠性。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (5)
1.一种超结MOS晶体管,其特征在于,所述晶体管包括:
外延层,所述外延层中交替设有多根P型立柱和多根N型立柱,其中,每相邻两根P型立柱之间的区域为一根N型立柱;
多个表面MOS结构,所述表面MOS结构包括:P阱区、N阱区、栅氧化层和栅极;
其中,每个所述表面MOS结构的敏感区域均与所述P型立柱的中轴线错位;每个所述表面MOS结构的敏感区域均与所述N型立柱的中轴线错位;其中,所述敏感区域包括:所述栅氧化层与所述外延层交界的界面区域;
其中,所述外延层位于N+型衬底上,所述外延层为N型外延层;
位于所述P型立柱和所述N型立柱的交界处的所述表面MOS结构包括:位于所述P型立柱顶端的第一P+阱区、位于所述第一P+阱区顶端的第一N阱区、位于所述N型立柱顶端的P阱区、位于所述P阱内的第二P+阱区、位于所述第二P+阱区顶端的第二N阱区、栅氧化层和栅极;
其中,所述栅氧化层连接所述第一N阱区表面和所述第二N阱区表面;所述晶体管的金属源极连接所述第一P+阱区表面、所述第二P+阱区表面、所述第一N阱区表面和所述第二N阱区表面;所述晶体管的漏极为所述N+型衬底。
2.如权利要求1所述的晶体管,其特征在于,所述敏感区域还包括:
所述P阱区的边界与所述外延层的表面交界的区域。
3.如权利要求1所述的晶体管,其特征在于:
每个所述表面MOS结构的栅氧化层均位于所述P型立柱和所述N型立柱的交界处;其中,以一个P型立柱和一个N型立柱为一对立柱,任一对立柱内有奇数个所述表面MOS结构。
4.如权利要求1所述的晶体管,其特征在于:
所述多个表面MOS结构中,部分表面MOS结构的栅氧化层位于所述P型立柱和所述N型立柱的交界处。
5.如权利要求1-4任一所述的晶体管,其特征在于:
所述外延层为N型外延层;
所述界面区域具体为:所述栅氧化层与所述外延层的N型区交界的区域。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610542698.9A CN106206734B (zh) | 2016-07-11 | 2016-07-11 | 一种超结mos晶体管 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610542698.9A CN106206734B (zh) | 2016-07-11 | 2016-07-11 | 一种超结mos晶体管 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106206734A CN106206734A (zh) | 2016-12-07 |
CN106206734B true CN106206734B (zh) | 2019-10-29 |
Family
ID=57477533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610542698.9A Active CN106206734B (zh) | 2016-07-11 | 2016-07-11 | 一种超结mos晶体管 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106206734B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109256428B (zh) * | 2018-09-29 | 2021-07-09 | 东南大学 | 一种鳍式超结功率半导体晶体管及其制备方法 |
CN111929559B (zh) * | 2020-07-02 | 2023-05-23 | 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) | 大气中子导致的功率器件的失效率评估方法及装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102227000A (zh) * | 2011-06-23 | 2011-10-26 | 西安电子科技大学 | 基于超级结的碳化硅mosfet器件及制备方法 |
CN102623349A (zh) * | 2006-01-31 | 2012-08-01 | 株式会社电装 | 具有超结结构的半导体器件及其制造方法 |
CN102832248A (zh) * | 2012-09-10 | 2012-12-19 | 西安电子科技大学 | 基于半超结的碳化硅mosfet及制作方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7928470B2 (en) * | 2005-11-25 | 2011-04-19 | Denso Corporation | Semiconductor device having super junction MOS transistor and method for manufacturing the same |
-
2016
- 2016-07-11 CN CN201610542698.9A patent/CN106206734B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102623349A (zh) * | 2006-01-31 | 2012-08-01 | 株式会社电装 | 具有超结结构的半导体器件及其制造方法 |
CN102227000A (zh) * | 2011-06-23 | 2011-10-26 | 西安电子科技大学 | 基于超级结的碳化硅mosfet器件及制备方法 |
CN102832248A (zh) * | 2012-09-10 | 2012-12-19 | 西安电子科技大学 | 基于半超结的碳化硅mosfet及制作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN106206734A (zh) | 2016-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8125023B2 (en) | Vertical type power semiconductor device having a super junction structure | |
US9362393B2 (en) | Vertical semiconductor device including element active portion and voltage withstanding structure portion, and method of manufacturing the vertical semiconductor device | |
US9048250B2 (en) | Method of manufacturing a super-junction semiconductor device | |
CN105185829B (zh) | 功率晶体管及其制备方法 | |
US10020388B2 (en) | Insulated gate bipolar transistor including charge injection regions | |
CN110190125A (zh) | 碳化硅半导体器件 | |
KR20140097350A (ko) | 초접합 mosfet 디바이스를 위한 에지 종단 | |
JP2009105110A (ja) | 半導体素子 | |
CN106463503A (zh) | 半导体装置 | |
CN107302025B (zh) | 一种具有抗单粒子效应的vdmos器件 | |
KR102068842B1 (ko) | 반도체 전력소자 | |
CN208028068U (zh) | 半导体器件 | |
US10090408B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
CN106206734B (zh) | 一种超结mos晶体管 | |
WO2018040973A1 (zh) | 集成有耗尽型结型场效应晶体管的器件及其制造方法 | |
US20170263698A1 (en) | Power metal-oxide-semiconductor device | |
CN107039512A (zh) | 抗闩锁晶体管 | |
Kawashima et al. | Narrow-pitch n-channel superjunction UMOSFET for 40–60 V automotive application | |
CN105185830B (zh) | 功率晶体管及其结终端结构 | |
CN109801957A (zh) | 一种超结器件结构、器件及制备方法 | |
KR101780436B1 (ko) | 다이나믹 특성 개선을 위한 트렌치 메탈 구조를 갖는 슈퍼 정션 mosfet | |
CN109755315A (zh) | 超结器件及其制造方法 | |
CN104037208B (zh) | 一种双模式绝缘栅晶体管 | |
CN103840001B (zh) | 具有额外漏极od增加的高压漏极延伸mosfet | |
CN108428732A (zh) | 超结器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220817 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
TR01 | Transfer of patent right |