CN103814442A - 用于具有单金属层基底的半导体封装中的高速信号完整性的结构 - Google Patents

用于具有单金属层基底的半导体封装中的高速信号完整性的结构 Download PDF

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CN103814442A
CN103814442A CN201280044982.3A CN201280044982A CN103814442A CN 103814442 A CN103814442 A CN 103814442A CN 201280044982 A CN201280044982 A CN 201280044982A CN 103814442 A CN103814442 A CN 103814442A
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pad
pair
chip
contact pad
parallel
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CN103814442B (zh
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G·E·霍华德
M·D·罗米格
M-S·A·米勒罗恩
S·慕克吉
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Texas Instruments Inc
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Abstract

在基底（103）上的具有键合焊盘（110）的半导体芯片（101），该基底具有多行多列规则间距的金属接触焊盘（131）。一个区包括第一对（131a，131b）和平行的第二对（131c，131d）金属焊盘，以及用于地电位的单个接触焊盘（131e）；通过平行且等长的迹线（131a，132b等）连接到相应的各对相邻接触焊盘的交错的多对缝合焊盘（133）。平行且等长的键合引线（120a，120b等）将键合焊盘对连接到缝合焊盘对，从而形成多对平行且等长的差分导线。处于平行且对称位置的两个差分对形成用于传导高频信号的发射器/接收器单元。

Description

用于具有单金属层基底的半导体封装中的高速信号完整性的结构
技术领域
本发明总体涉及半导体器件和工艺，更具体涉及用于具有单金属层基底和引线键合的半导体封装中的高速信号完整性的结构的配置和制造方法。
背景技术
半导体器件通常包括包封该器件的封装内的集成电路（IC）芯片以及与该芯片集成的基底。为了使现代半导体器件按照预期工作，要求传播通过器件的任何一对差分信号在信号波的相对幅值和相对相位角方面在预定限度内匹配。
对于关于差分信号的集成电路（IC）芯片的设计，基本模块（buildingblock）可以采用通过相互交错（interdigitate）部件的关键版图而已经被匹配的电路部件，例如晶体管和电阻器。
对于将信号从IC芯片引导到例如印制电路板（PCB）的基底或载体的设计，设计者通常面对类似的要求－通常存在将成对的差分信号的路径失配保持在限度内的约束。作为示例，对于在聚合物基底（如本领域中常见的）中传播的10GHz信号，波长仅仅是大约1.5厘米。对于差分信号对，信号路径总长度中仅0.75毫米的失配就会在相位角中产生5%的误差。该失配不仅涉及信号路径的长度（其包括基底上的金属迹线的长度和将IC芯片连接到基底的键合引线的长度），而且还涉及迹线和键合引线的接近度和平行度；平行度和接近度通常具有10%的失配预算。对失配做出贡献的这些参数的总和通常被称为失配预算。
封装系统的失配预算包括金属迹线的长度、厚度和宽度的失配、迹线与键合引线的接近度和平行度的失配以及沿着信号路径的穿通孔与过孔的直径和电镀金属厚度的失配的总和。
在如今的技术中，对这些约束的解决方案是使用具有多个金属层的基底。多个金属层为将差分信号对从IC芯片的键合焊盘借助引线路由到由基底的顶层金属形成的缝合焊盘提供了灵活性；这个顶部金属层也形成了迹线，这些迹线将信号引导到金属填充的过孔内孔（via hole），这继而引导到顶层下方的金属层。之后，可以由下面的金属层形成额外的迹线，这最终可以将信号路由到接触焊盘，作为基底的输出端子。通常，锡球或金属柱被粘附到接触焊盘并且用作至外部电路（例如印制电路板）的连接器。
发明内容
对于高频半导体器件，申请人认识到，前沿市场的趋势是不断推进更高频率以及更低成本的持续压力。基于这些趋势，申请人看到，金属多个层之间的金属填充的过孔的存在严重增加了高速信号封装的失配预算的负担。这些原因可以是通孔固有的瑕疵：过孔内孔的额外钻孔、过孔内孔壁的电镀以及关联的制造步骤必然增加了信号路径的尺寸失配的概率；由过孔产生的电气阻抗中的不可避免的中断将添加信号之间的相位角失配；最后但并非不重要的是，具有过孔的多层基底通常是非常昂贵的。
为了解决过孔失配问题，申请人选择具有单个金属层的基底，这完全避免了对过孔内孔的需要。金属层被图形化在尺寸是针对焊接凸点设计的接触焊盘阵列中以及用于引线键合的缝合焊盘阵列中。借助焊盘阵列，焊盘区被选择为发射器/接收器单元的基础。
申请人进一步认识到，对于发射器/接收器单元的高频操作，差分对需要在该对内紧密耦合，但是差分对需要彼此紧挨着放置。这种放置在实现差分对之间的可接受的小串扰时造成严重困难。申请人通过在两对之间中设置接地迹线和焊线解决了最小化两个紧密间隔的差分线对之间的串扰的问题。
对于引线键合的器件，差分对的紧密填充定位要求紧密间隔的缝合焊盘（在基底上的着陆焊盘，以接受来自集成电路芯片的焊线）。为了在发射器/接收器单位单元中给缝合焊盘腾出可用空间，申请人去掉（depopulate）了每个2×3阵列的一个接触焊盘，由此为紧密接近放置的两个差分对的缝合焊盘释放空间，并且使附加的至少一个缝合焊盘可用于被放置在该对之间作为屏蔽的处于电气地电位的引线。在去掉的区域中留下足够空间以便在相应的缝合焊盘和接触焊盘之间以针对长度和平行度所需的匹配方式放置连接迹线。注意的是，以平行且等长的拱形键合将缝合焊盘连接到芯片表面上的相应的键合焊盘的引线。得到的差分导线在长度和平行度方面在狭窄窗口内匹配。
此外，差分对通过地迹线或电源迹线屏蔽了噪声。借助发射器/接收器单元的这些布置，可以使进入10GHz范围的高速产品具有极好的信号完整性。
附图说明
图1根据示例实施例示出用于传导高频信号的发射器/接收器单元的透视图。
图2是具有焊接凸点的单个接触焊盘的剖面图，该焊接凸点被附连用于接触外部电路板。
图3示出在一个说明性布置中的包括接触焊盘和缝合焊盘的基底区的顶视图。
图4是基底区的缝合焊盘的顶视图，这些焊盘包括将缝合焊盘连接到芯片键合焊盘的键合引线。
图5是四路双工高速差分收发器的实施例的顶视图。
具体实施方式
图1根据本发明的实施例示出用于在半导体封装中以完整性传导高频信号的发射器/接收器单元，其总体被标为100。半导体芯片101通过粘合附连层102（层厚度大约20μm）被附连到基底103。在图1的示例中，芯片可以具有大约280μm的厚度；在其他实施例中，该厚度可以更大或更小。
位于边缘附近，芯片101具有适合粘附金属焊线的多个金属键合焊盘110。在图1的示例中，多个引线120中的单个引线可以具有大约20μm到30μm之间的直径，这生成大约30μm到50μm的无空气球以及大约30μm到60μm的扁平球。虽然图1中的键合焊盘110被描绘为以大约60μm的中心距阵列布置在线性且整齐的行中，但是其他实施例可以具有交错的键合焊盘阵列、更大或更小的间距、不同区域的键合焊盘以及除正方形之外的轮廓，或任何其他布置。在图1中，键合体（其可以是球形键合体、针脚（stitch）键合体或楔形键合体）被示为球形键合体，其中在球体上方具有大约100μm高度的线颈。
在图1的示例中，引线的长度121大约是1000μm。应该强调的是，图1中所示的所有引线120的长度在＜5%变化窗口内一致。在其他实施例中，引线长度可以更大或更小，但是引线在＜5%变化窗口内具有相同的长度。
如图1所示，基底103包括由绝缘材料制成的载体130和面向芯片101的图形化金属层。可以由多种低成本材料提供绝缘载体材料；作为示例，绝缘材料可以是50μm厚的聚酰亚胺胶带，或更厚的玻璃纤维增强塑料板。作为示例，金属层可以是铜；优选厚度可以在大约10μm到50μm的范围内。在图5中大致示出了示例实施例的金属层的图形，并且在图1中更详细地进行显示。该图形包括：多行多列规则间距的焊盘阵列131，焊盘的尺寸适合被选择用于附连金属凸点（例如焊接球）的接触焊盘；进一步地，多行多列交错的焊盘阵列133，焊盘的尺寸适合金属连接器（例如键合引线）的缝合焊盘（stitch pad）；以及总体被分别标为132和135的迹线网络。每个接触焊盘131可以被成形为圆形或正方形，或具有圆角的正方形；示例接触焊盘131的直径可以是375μm。在接触焊盘131的位置中，绝缘载体示出直径小于接触焊盘直径的过孔内孔134。
图2示出通过填充绝缘载体130中的过孔内孔134将焊接凸点201附连到接触焊盘131的示例。接触焊盘金属必须重叠用于焊接凸点的冲孔。接触焊盘的轮廓可以是圆形、正方形、具有圆角的正方形、六边形或任何其他合适的形状。在接触焊盘131具有375μm的宽度的优选示例中，可以通过穿过基底134打一个直径大约为300μm的孔来制造过孔内孔134。焊接凸点201的尺寸被选择为在回流后生成至板203上的金属焊盘202的可靠连接。作为示例，金属焊盘202可以由铜制成并且具有可焊接的表面（例如最外面具有薄金层的镍层）；回流后的焊接凸点201的尺寸可以吸收热机械应力而没有金属疲劳和裂化。
参考图1，由该图示出的示例发射器/接收器单元是三维的：键合引线120跨越芯片101和具有二维金属层图形的基底103的表面之间的高度差。需要指出的是，短术语“单元（cell）”在本文中被用于指代出于尺寸效率目的而需要并排放置两对差分导线的电气单位（unit）；差分对之间的信号的耦合需要≤1%的电压（在5GHz处－40dB）。因此，差分信号表现出各对之间和各对内的低串扰、良好的耦合以及长度匹配，从而以良好的完整性传导高频信号。一对差分导线包含引线、迹线、焊盘和凸点，它们一起将电气高频信号从一个端点传导到另一个端点。当考虑通过差分对的横截面时，它具有基本上是零的总电流。一个单元的两个差分对所需的二维单位的焊盘和迹线在本文中被称为“区（zone）”。在图1中讨论了区的示例（事实是，图1中所描绘的示例区可以仅仅是图5中所讨论的围绕附连芯片的较大图形化基底区域的一部分）。
在图1中所表示的区包括第一对接触焊盘131a和131b以及平行的第二对接触焊盘131c和131d。借助焊接凸点通过支撑金属焊盘的载体130中的过孔内孔附连到每个接触焊盘，各对接触焊盘为该单元的差分对提供输入/输出端子。在第一对和第二对之间的空间中，放置单个接触焊盘131e。接触焊盘131e连接到地电位，从而在邻近的各对接触焊盘之间并且因此在该对差分导线之间提供电气屏蔽。
在图1的示例中，第一对接触焊盘131a和131b以及第二对接触焊盘131c和131d与单个接触焊盘131e一起形成具有500μm的规则中心距136的2×3接触焊盘阵列。另一方面，如图所示，没有放置单个接触焊盘131e的“搭档”，以便提供尺寸被设计为缝合焊盘并且适合粘附键合引线120的焊盘阵列133所需的空间。
可以在图3和图4中看到缝合焊盘阵列133的规则性。图3相对于芯片键合焊盘以顶视图的方式显示了图1的区；图4突出了缝合焊盘和从芯片键合焊盘到基底缝合焊盘的引线键合连接。缝合焊盘的轮廓和面积被选择为使得该焊盘为在引线键合方法（引线直径约为20μm到30μm）例如通过毛细管应用针脚键合或楔形键合提供空间。作为示例，缝合焊盘可以具有长方形形状，其中边长为100μm和150μm。如图3所示，缝合焊盘阵列配合在第一对和第二对接触焊盘之间的空间中（如上所述）；该空间等同于如图中所示的去掉接触焊盘空间。在该示例中，该区包括围绕原本的接触焊盘被取消的一个位置的五个相邻的接触焊盘。这五个接触焊盘形成U形，其中U的开口面向基底的边缘130a，背向键合焊盘。在其他实施例中，键合焊盘可以被布置为镜像图像，U形开口面向芯片的边缘101a。缝合焊盘被图形化为两行不相等的数量；在图3所示的示例中，较长行具有四个缝合焊盘，较短行具有两个缝合焊盘，它们相对于较长行被布置在交错位置。第一对缝合焊盘在图中被标为133a和133b。类似的交错位置适用于缝合焊盘133c和133d。
平行行的相邻缝合焊盘交错布置，因为交错允许附连的键合引线在相应的键合焊盘和缝合焊盘之间平行且紧密接近地跨越，例如具有仅60μm的间距。在图1和图4中，用于缝合焊盘133a和133b的该对键合引线分别被标为120a和120b；用类似的方式，用于缝合焊盘133c和133d的该对键合引线分别被标为120c和120d。在其他实施例中，该间距可以更大，例如150μm。缝合焊盘133a和133b相对于彼此的交错位置允许该差分对的相应的键合引线120a和120b相对于彼此保持在5°的平行度内。类似的相关性也适用于缝合焊盘133c和133d以及它们相应的键合引线。
缝合焊盘和接触焊盘需要通过导电迹线连接；优选地，这些迹线通过从绝缘载体130表面上的同一金属层131刻蚀来制造。迹线的宽度取决于与层厚度的纵横比；作为示例，迹线可以具有大约20μm的宽度。图3示出连接相应的缝合焊盘和相邻接触焊盘的各对迹线。作为示例，连接缝合焊盘133a与相邻接触焊盘131a的迹线132a和连接缝合焊盘133b与相邻接触键131b的迹线132b形成基本平行铺设并且具有相等长度的一对迹线。与该对迹线132a和132b对称的是一对迹线132c和132d，其以基本平行且等长的方式分别连接到一对接触焊盘131c和131d。
如图3所示，交错的缝合焊盘阵列具有在焊盘对133a和133b以及焊盘对133c和133d之间处于对称中心位置的缝合焊盘133e和133f。在一些实施例中，缝合焊盘133e和133f可以被组合成面积比其他缝合焊盘大的单个焊盘。缝合焊盘133e和133f连接到接触焊盘131e（其处于地电位）。将缝合焊盘113e和133f连接到芯片边缘处的相应键合焊盘的一个或两个键合引线120e是与其他键合引线平行且等距的。因此，缝合焊盘133e和133f和键合引线120e的地电位有助于为差分对120a－133a－132a－131a和120b－133b－132b－131b以及差分对120c－133c－132c－131c和120d－133d－132d－131d的导线之间的低串扰提供有效屏蔽。所提到的差分对包含两个基本平行且等长的导体部分，它们能够以高完整性将高频信号从封装端子（焊接凸点）传导到芯片端子，反之亦然。如所述的，当考虑通过差分对的横截面时，它具有基本为零的总电流。
如所提到的，高完整性信号传输的目的可以被实现，无论接触焊盘阵列的U形开口面向芯片边缘（如图3中所示）还是背向芯片边缘。
参考图1，被标为135的迹线将缝合焊盘引导到基底的边缘。这些迹线用于以下目的：将图形化金属层连接到电镀棒，以便将芯片暂时钩住到电镀槽，从而以低成本将附加金属淀积到迹线上。
为了保护键合引线和芯片表面，芯片必须被包封，优选用模塑料包封。在优选示例中，在键合引线拱形的最高峰上的模塑料的厚度可以在300μm和400μm之间。
在图1、图2、图3和图4中所描述的示例实施例说明，在不使用常规多金属层基底和关联的金属填充过孔内孔的情况下，可以实现将差分信号的完整性保持在5%的失配预算内并且在10%的差分阻抗预算内的要求。使用单个金属层基底，图形化金属层包括可以容纳交错形式的键合缝合焊盘的区。从相邻缝合焊盘到相应的接触焊盘的迹线以基本平行的方式行进。对于与该区关联的三维单元，布置一对差分接触焊盘，使得用于该差分对的键合引线和迹线之和具有相比拟的长度。
得到的单元能够很好地保持在确保半导体封装信号完整性的5%的失配预算和10%的接近度和平行度预算内。对于差分阻抗，所要求的阻抗匹配大约是100Ω。设计要求强制每个信号携带地基准。对于差分对中的每个迹线，优选的到地的阻抗大约是50Ω；每个差分对包括以该地为基准时的正走向电压和负走向电压。对于正走向信号和负走向信号两者，这些电压到这个基准地的阻抗优选是大约50Ω。
高速信号器件的频率范围优选是大约5GHz到10GHz；在10GHz处，波长在空气中是30mm而在模塑料中是大约15mm。在10GHz处，阻抗匹配优选在15%内，更优选在10%内。器件的优选电压范围大约是800mV到1000mV，其中假设负载为100Ω，则每个差分对的电流大约10mA。对于1000mV的输入差分信号，差分对之间的串扰优选被保持低于10mV（或在5GHz处－40dB）。对于上面讨论的示例实施例，已经测得串扰为大约3mV。
在平行且对称位置处具有两对差分导线的发射器/接收器单元的概念可以被扩展到系统，其中芯片被组装在基底上，若干这种单元环绕该芯片。在优选布置中，四个发射器/接收器单元以交叉布置环绕芯片。
另一个示例实施例在图5中被示为四路双工高速差分收发器。需要指出的是，出于清楚，图5描绘了简化的X射线图；它仅示出了选定的焊盘、迹线和键合引线。图5示出了正方形（或长方形）半导体芯片501的顶视图，其中键合焊盘510靠近芯片边缘；该视图以X射线方式穿透了包封化合物。芯片被组装在基底503上，基底503具有面向该芯片的金属层。该层包括尺寸被设计为接触焊盘的多行多列规则间距的焊盘531阵列图形。在该阵列内，在图5中通过虚线轮廓540a、540b、540c和540d描画了四个发射器/接收器单元；根据本发明设计这些单元，从而以完整性传导高频信号。
这些单元被对称地设置在芯片的四个侧边处。每个单元包括第一对（531a，531b）接触焊盘以及平行的第二对（531c，531d）接触焊盘，并且在第一对和第二对之间的空间中还包括用于地电位的单个接触焊盘（531e）和尺寸被设计为缝合焊盘的交错的各对焊盘（133）。每个缝合焊盘对通过平行且等长的迹线（132a和132b，132c和132d）连接到相应的相邻接触焊盘对。
跨越平行且等长的拱形的键合引线（120a和120b，120c和120d）用于将一对键合焊盘连接到相应的一对缝合焊盘。键合焊盘、引线、缝合焊盘、迹线和接触焊盘的总和形成导线，并且一对平行且等长的导线形成从键合焊盘到接触焊盘的差分对。对于差分对，导线的长度在5%内一致并且键合引线在5%的平行度内。在这个背景下，键合引线的方向可以与相应的芯片侧边形成直角，或者键合引线的方向可以与相应的芯片侧边形成稍微偏离直角一个角度。处于平行且对称位置的两对差分导线形成发射器/接收器单元，以便以完整性传导高频信号。
所描述的原理不仅适用于集成电路，还适用于用于高速电信号的其他器件。
这些原理也适用于基底是使用如下其他叠层、材料或方法制成的器件，这些叠层、材料或方法使用在此描述的技术大致实现IC芯片和PBC之间的互连。例如，这些原理适用于通过电镀、印刷或刻蚀来施加图形化导电层的器件，或者绝缘层由固化的环氧树脂材料（例如模塑料）组成的器件，或者通过绝缘层的互连由用铜、焊料或其他导电材料填充的极小过孔组成的器件。
这些原理也适用于由模塑料和由其他防护封装（例如金属容器）包封的器件。
本领域技术人员将理解，可以对所描述的实施例进行修改，并且在本发明的范围内，许多其他实施例是可能的。

Claims (11)

1.一种半导体器件，其包括：
在芯片边缘附近具有键合焊盘的半导体芯片，所述芯片被组装在基底上；
具有面向所述芯片的金属层的所述基底，该层被图形化在包括尺寸被设计为接触焊盘的多行多列规则间距的焊盘的阵列中；
在所述阵列内的区，该区包括第一对接触焊盘和平行的第二对接触焊盘，并且在所述第一对和所述第二对之间的空间中包括用于地电位的单个接触焊盘和尺寸被设计为缝合焊盘的交错的多对焊盘，每个缝合焊盘对通过平行且等长的迹线连接到相应的相邻接触焊盘对；
键合引线，其跨越平行且等长的拱形，用于将一对键合焊盘连接到相应的一对缝合焊盘，由此形成从键合焊盘到接触焊盘的一对平行且等长的差分导线；以及
处于平行且对称位置的两对差分导线，这两个差分对形成发射器/接收器单元。
2.根据权利要求1所述的器件，进一步包括附连到远离所述芯片的接触焊盘表面的焊接凸点。
3.根据权利要求2所述的器件，其中形成差分对中的一个导线的导体的总和与形成该对中的另一个导线的导体的总和在5%内一致。
4.根据权利要求3所述的器件，其中形成差分对的两个导线的键合引线在它们的整个长度上彼此间隔开100μm内。
5.根据权利要求4所述的器件，其中形成差分对的两个导线的键合引线相对于彼此在5°平行度内。
6.根据权利要求5所述的器件，其中两个差分对之间的信号的耦合≤1%的电压，对应于在5GHz处－40dB。
7.根据权利要求1所述的器件，其中所述基底具有面向所述外部接触焊盘的金属层。
8.根据权利要求1所述的器件，其中所述基底具有通过电镀或刻蚀所述导电层生成的图形。
9.根据权利要求1所述的器件，其中在所述基底上的绝缘层选自于包括聚酰胺、玻璃纤维增强塑料或环氧树脂模塑料的群组。
10.根据权利要求1所述的器件，其中远离所述芯片的接触焊盘表面是可焊接的并且选自于包括NiPdAu、铜-OSP或者锡或基于锡的合金的群组。
11.一种半导体器件，其包括：
在芯片边缘附近具有键合焊盘的半导体芯片，所述芯片被组装在基底上；
具有面向所述芯片的金属层的所述基底，该层被图形化在包括尺寸被设计为接触焊盘的多行多列规则间距的焊盘的阵列中；
在所述阵列内的四个区，每个区包括第一对接触焊盘以及平行的第二对接触焊盘，并且在所述第一对和所述第二对之间的空间中包括用于地电位的单个接触焊盘和尺寸被设计为缝合焊盘的交错的多对焊盘，每个缝合焊盘对通过平行且等长的迹线连接到相应的相邻接触焊盘对，这些区对称地位于芯片周边周围，在每个芯片侧边处具有一个区；
在每个芯片侧边处跨越平行且等长的拱形的键合引线，用于将一对键合焊盘连接到相应的一对缝合焊盘，由此形成从键合焊盘到接触焊盘的一对平行且等长的差分导线；以及
处于平行且对称位置的两对差分导线，这两个差分对形成发射器/接收器单元，用于以完整性传导高频信号，四个单元对称地位于芯片周边周围，在每个芯片侧边处具有一个单元。
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