CN101842893A - 针对高电流和低电感的半导体装配和封装 - Google Patents

针对高电流和低电感的半导体装配和封装 Download PDF

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CN101842893A
CN101842893A CN200680038043A CN200680038043A CN101842893A CN 101842893 A CN101842893 A CN 101842893A CN 200680038043 A CN200680038043 A CN 200680038043A CN 200680038043 A CN200680038043 A CN 200680038043A CN 101842893 A CN101842893 A CN 101842893A
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lead
chip
wire
edge
parallel
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B·P·兰格
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种器件，该器件包括半导体芯片(110)，半导体芯片(110)具有侧边(111)和靠近所述侧边的多个金属焊盘(120，121)；这些焊盘被对齐以形成平行于所述侧边的列(130，131)。所述器件进一步包括具有引线的引线框(100)，这些引线的一端指向所述芯片边缘并通过一缝隙(150)与其间隔开；所述芯片被附着到所述引线框上。被选择引线的末端通过平行于所述芯片边缘的金属横条(160)连接起来。大致平行的焊丝(170)横跨所述缝隙，以将每个芯片焊盘连接到所述横条上，或者连接到未选择的引线末端。在优选的引线布局中，被选择引线和未选择引线交替出现。

Description

针对高电流和低电感的半导体装配和封装
技术领域
本发明通常涉及半导体器件和工艺领域，更具体地涉及高性能丝焊半导体器件，这些器件可以在成本低于倒装焊芯片器件的情况下提供高功率、低噪声和高速度。
背景技术
在集成电路(IC)技术中存在组件的更加集成化和组件特征尺寸缩小的趋势。更高水平的集成化包括对更大数量的信号线和电源线的需求，而更小的特征尺寸使得越来越难以保持没有相互干扰的洁净信号。此外，随着信号频率增大，需要特别注意信号的传输和屏蔽。
这些趋势和需求不仅支配组合IC的半导体芯片，还支配容纳和保护IC芯片的封装。实际上，板和电子产品的其它部分已经作为系统被包含于这些考虑中。
在硅集成电路(IC)器件的加工工艺流程中倒装焊芯片装配的数量增长受到几个事实的推动。首先，当与传统丝焊互联技术相关的寄生电感被降低时，一般可以改善半导体器件的电学性能。其次，倒装焊芯片装配通常在芯片和封装之间提供比丝焊更高的互联密度。第三，在很多设计中，倒装焊芯片装配比丝焊消耗更少的硅“实体(realestate)”，并因此节约硅面积并降低器件成本。第四，当利用并行的群焊/排式键合(gang-bonding)技术而不是连续的单个键合步骤时，通常可以降低制造成本。传统加工工艺利用锡球或焊锡凸块，并以其回流技术作为球焊的标准方法。
虽然倒装芯片装配器件在技术上看起来有优势，但倒装芯片装配的器件比丝焊器件更昂贵。成本/性能敏感的产品比不上较低性能的器件。产品经理要求倒装芯片装配的产品的更高性能，但他们也要求丝焊器件更低的成本。其中丝焊器件的技术缺陷是焊丝的较高电阻和较高电感。
发明内容
申请人认识到需要发展一种技术方法，该技术方法结合丝焊装配的低成本优势和优越的技术特性优势，比如适用于高功率的最小电感和噪声-高速的先决条件-以及降低的电阻。装配高引线数的器件的低成本方法应该提供优良的电学性能，特别是速度和功率、机械稳定性以及高产品可靠性。加工方法应该有足够的灵活度以便应用于包括衬底在内的不同半导体产品系列以及大范围的设计和工艺变体。
本发明的一个实施例是一种包含半导体芯片的器件，该半导体芯片具有侧边缘和靠近该边缘的多个金属焊盘；这些焊盘被对齐以形成平行于该边缘的列。所述器件还包括具有引线的引线框，这些引线的一端指向芯片边缘并通过一缝隙与其间隔开；所述芯片被附着在引线框上。被选择引线的末端通过平行于芯片边缘的金属横条连接起来。大致平行的焊丝横跨所述缝隙，以将每个芯片焊盘连接到横条上，或者连接到未选择的引线末端。
在一个优选引线布局中，被选择引线和未选择引线交替出现。
在另一个优选引线布局中，相邻的未选择引线被多个选择引线框起来。
本发明的另一个实施例是一种包含半导体芯片的器件，该半导体芯片具有侧边缘和靠近该边缘的多个金属焊盘；这些焊盘被对齐以形成平行于所述边缘的列。该器件还包括具有引线的引线框，这些引线的一端指向芯片边缘并通过一缝隙与其间隔开，所述芯片被附着在引线框上。第一组多个被选择引线的末端通过平行于芯片边缘的第一金属横条连接起来。第二组多个被选择引线的末端通过平行于芯片边缘的第二金属横条连接起来。大致平行的焊丝横跨所述缝隙，以将每个芯片焊盘连接到第一横条上，或者连接到第二横条上，或者连接到未选择引线末端上。
本发明的各个实施例提供通过多于一个连接线来传输电流的可能，因此提供对高容量电流的传输。此外，各对连线在其整个长度方向上大致平行对齐；因此，相应连线之间的有效电感(及因此产生的噪声)被减小。电流的示例包括电源到地的电流和信号到地的电流。可以通过从芯片边缘处的芯片焊盘键合到引线框的横条上而提供最短可能的丝焊来实现对电感的额外降低。此外，在布局中可以使用多重丝焊来利用电源线和地线的耦合。
本发明的技术优势是其简易性和低成本，从而它可以被很容易地应用于任何集成电路。
本发明的另一个技术优势是其通用性，对于高速集成电路特别适用。
本发明的另一个技术优势是其对引线框设计的广泛应用；实际上，本发明也可以应用于无引脚封装和BGA(球栅阵列)可兼容衬底。
附图说明
图1A描述依照本发明的一个实施例的部分引线框的俯视示意图。
图1B描述与图1A相同的部分引线框的俯视示意图，所述部分引线框通过焊丝连接到芯片的接触焊盘上。
图2A图示说明依照本发明的另一个实施例的部分引线框的俯视示意图。
图2B图示说明与图2A相同的部分引线框的俯视示意图，所述部分引线框通过焊丝连接到芯片的接触焊盘上。
图3A示出依照本发明的另一个实施例的部分引线框的俯视示意图。
图3B示出与图3A相同的部分引线框的俯视示意图，所述部分引线框通过焊丝被连接到芯片的接触焊盘上。
图4是在QFN压模封装实施例中图示说明暴露金属部分的部分引线框和已装配芯片的横截面示意图。
具体实施方式
最近的半导体器件应用，特别是电源应用，要求通过半导体芯片来实现高开关电流特性。此外，电噪声水平需要保持尽可能小，并要求低电感。另外，需要保持小的封装尺寸，因为在大多数器件应用中可用空间非常宝贵。因此通常在半导体技术中需要保持尽可能低的器件和加工成本。
图1A和1B图示说明实现这些设计需求的本发明的一个实施例。图1A是引线框的部分引线的俯视图，一般标示为100，而图1B是与芯片的各部分焊盘相连接的同一引线框部分的俯视图；芯片部分被标示为110。该芯片具有侧边缘111和靠近边缘111的多个金属焊盘120，121，...，12n。这些焊盘被对齐以形成平行于边缘111的列130和131。对焊盘的金属进行选择，从而该金属或该金属的至少上表面可以进行可靠的键合，特别是通过金丝；这种焊盘金属的示例是铝或金。
半导体芯片的原材料常常是硅或锗硅，特别是对于集成电路。但是，本发明也适用于由镓砷、其它III-V或II-VI化合物或制造中使用的任何其它半导体材料制成的芯片，或适用于绝缘衬底材料，这些材料涉及丝焊连接到导电引线。图1B中所示的芯片110的电路部分只示意性地图示说明芯片110的电源电路的线180和181。
现在参考图4，可以看出芯片110通过使用粘结材料411(一般是环氧胶或聚酰亚胺)附着在引线框的芯片焊盘410上。
图1A和1B图示说明引线框的部分100。部分100具有引线140，141，...，14n。这些引线的一端140a，141a，...，14na指向芯片边缘111；它们通过缝隙150与边缘111间隔开(见图1B)。在很多器件示例中，引线中心到中心的间距190优选在0.3mm至0.8mm之间。
在引线框部分100中，被选择引线140，142，...，14n的末端140a，142a，...，14na通过平行于芯片边缘111的金属横条160连接起来。换句话说，在图1A和1B的示例中，当对引线计数时，所有为偶数的引线通过金属横条160连接起来。
对于包括部分100和芯片焊盘410的整体引线框，其优选材料为铜或铜合金。典型引线框厚度范围为约120μm至250μm；但是，一些器件可能需要更薄或更厚的材料(对引线的某些部分，特别是在QFN封装中，厚度可以蚀刻到约75μm至100μm以便限制外部焊接的暴露；这一特性将结合图4进行讨论)。为了制造的简单和成本-效益，在通常实践中由数片材料来生产引线框并压印或蚀刻希望的形状。此外，为了支持引线框与模塑料之间的粘附力，为了改善外部引线的可焊接性，或为了增强其它特性或细丝点焊粘连(wire stitch attach)之类的工艺，可以对部分铜电镀另一金属层，如镍、钯、锡或银等。
图1B图示说明大致平行的焊丝170，这些焊丝横跨缝隙150，以将每个芯片焊盘(例如120和121)连接到横条160上，或者连接到未选择的引线末端141a上。为了达到未选择的引线末端而不短路，焊丝必须跨越横条。在图1B的实施例中，相邻焊丝对170大致相互平行；图2B和3B示出的实施例中有更多组的焊丝大致相互平行。焊丝的长度决定于芯片尺寸和引线框与芯片的接近程度。对于图4中例示的方形扁平无引脚(QFN)器件，图1B、2B和3B的图解中示出优选焊丝长度为约1000μm至1500μm。
图1B中焊丝对170的平行性的优选应用是电源电路，其中一组焊丝，如附着于焊盘列130的焊丝，用于传输“入电流”，而另一组焊丝，如附着于焊盘列131的焊丝，用于传输“出电流”。例子包括电源到地的电流和信号到地的电流。图1B的实施例提供两种优势：多重焊丝提供高电流能力，而平行性提供相应焊丝之间的低有效电感(并因此产生低噪声)。
图2A和2B图示说明本发明的另一个实施例。引线框部分200的引线被编组，从而一组相邻的未选择引线240，241，...，14n被多个被选择引线250，251，...，25n框起来。在图2B中，未选择引线的末端240a，...，24na指向芯片边缘211，而被选择引线末端250a，...，25na通过金属横条260连接起来。
引线框部分200中所示的引线布局能够得到器件装配中焊丝的特别有效的平行性。图2B描述具有金属焊盘的标示为210的芯片部分。该芯片具有侧边缘211；多个焊盘220，221，...，22n靠近边缘211。这些焊盘被对齐以形成平行于边缘211的列230和231。边缘211通过缝隙270与引线横条260间隔开。
图2B图示说明大致平行的焊丝280，这些焊丝横跨缝隙270，以将每个芯片焊盘(例如220和221)连接到横条260上，或者连接到未选择的引线末端240a上。为了达到未选择的引线末端而不短路，焊丝必须跨越横条。多重焊丝提供高电流能力，而焊丝的平行性提供低有效电感并因此产生低噪声。
图3A和3B图示说明本发明的另一个实施例，其中图3A描述引线框部分300，而图3B描述芯片部分310与芯片侧边缘311和引线框300的装配。在该引线框中，第一组多个被选择引线340，...，34n的末端340a，...，34na通过第一金属横条360连接起来。如图3B所示，横条360平行于芯片边缘311。另外在该引线框中，第二组多个被选择引线350，...，35n的末端350a，...，35na通过第二金属横条361连接起来。如图3B所示，横条361平行于芯片边缘311。在横条361和芯片边缘311之间有一缝隙370。
大致平行的焊丝380横跨缝隙370，以将每个芯片焊盘连接到第一横条360上，或者连接到第二横条361上。在具有剩余未选择引线末端的器件中，相互平行并平行于上述各组引线的焊丝横跨缝隙370来连接各个芯片焊盘到未选择引线末端。
本发明适用于引线封装的引线框以及无引脚封装的引线框。在图4的横截面中示意性地图示说明方形扁平无引脚器件的示例。芯片110通过粘结材料411附着在引线框的芯片焊盘410上。芯片110具有位于芯片边缘111附近的金属焊盘120和121。该引线框具有更多的引线420，这些引线的一端421指向芯片边缘111；引线末端421通过缝隙150与芯片边缘111间隔开。焊丝170横跨缝隙150来分别连接芯片焊盘120和121到引线420的其中一个上。
引线420的初始厚度被标示为430。但是，对于引线长度的部分440(大约为长度的一半)，厚度430优选通过蚀刻被减少。减少的厚度被标示为431。例如，对于初始厚度在约150μm至200μm之间的情况，减少的厚度优选在约75μm至100μm之间。厚度减少的引线长度部分可以进一步展现减少了的宽度，如图1A-3B的引线框示例中所示意性说明的。
在将器件密封到保护塑料450中后，例如利用模塑料，厚度减少的引线长度部分440用作塑料的锚。额外的引线表面增强粘附力并有助于防止封装分层。
另一方面，具有初始厚度430的剩余引线长度部分441提供电连接到外部部分上，同时也通过压力接点或通过焊接用作除芯片焊盘410之外的附着表面。对于后一种技术，引线长度部分441接收(receive)一可润湿且可焊接的表面(例如，金或钯的薄层)。
除了引线框，本发明还可适用于具有导线和接触焊盘的很多绝缘衬底。可以依照本发明的教导类比上面的引线框描述来设计这些导线和接触焊盘，以生成用于连接焊丝的适当附着点，使得焊丝大致相互平行而且可用大量焊丝来传输高电流。
虽然本发明已通过参考示意性实施例来进行描述，但并不希望从限制的角度来解读本说明书。在参考本说明书的基础上，这些示意性实施例的各种修改和组合以及本发明的其它实施例对本领域技术人员是明显的。

Claims (8)

1.一种器件，其包含：
一半导体芯片，所述半导体芯片具有侧边缘和靠近所述侧边缘的多个金属焊盘，所述焊盘被对齐以形成平行于所述边缘的列；
一引线框，所述引线框具有引线，所述引线的一端指向所述芯片边缘并通过一缝隙与其间隔开，所述芯片被附着在所述引线框上；
被选择引线的末端，所述末端通过平行于所述芯片边缘的金属横条连接起来；以及
大致平行的焊丝，所述焊丝横跨所述缝隙，以将每个芯片焊盘连接到所述横条上，或者连接到未选择的引线末端。
2.根据权利要求1所述的器件，其中所述被选择引线与未选择引线交替出现。
3.根据权利要求2所述的器件，其中从所述芯片焊盘到所述未选择引线末端的所述焊丝跨越所述横条。
4.根据权利要求1所述的器件，其中相邻的未选择引线被多个被选择引线框起来。
5.一种器件，其包含：
一半导体芯片，所述半导体芯片具有侧边缘和靠近所述边缘的多个金属焊盘，所述焊盘被对齐以形成平行于所述边缘的列；
一引线框，所述引线框具有引线，所述引线的一端指向所述芯片边缘并通过一缝隙与其间隔开，所述芯片被附着在所述引线框上；
第一组多个被选择引线的末端，所述末端通过平行于所述芯片边缘的第一金属横条连接起来；
第二组多个被选择引线的末端，所述末端通过平行于所述芯片边缘的第二金属横条连接起来；以及
大致平行的焊丝，所述焊丝横跨所述缝隙，以将每个芯片焊盘连接到所述第一横条上，或者连接到所述第二横条上。
6.根据权利要求5所述的器件，其进一步包括未选择的引线末端。
7.根据权利要求6所述的器件，其中大致平行的焊丝横跨所述缝隙，以将芯片焊盘连接到未选择的引线末端。
8.一种器件，其包含：
一半导体芯片，所述半导体芯片具有侧边缘和靠近所述边缘的多个金属焊盘，所述焊盘被对齐以形成平行于所述边缘的列；
一绝缘衬底，所述绝缘衬底具有导线，所述导线的一端指向所述芯片边缘并通过一缝隙与其间隔开，所述芯片被附着在所述衬底上；
被选择线的末端，所述末端通过平行于所述芯片边缘的金属横线连接起来；以及
大致平行的焊丝，所述焊丝横跨所述缝隙，以将每个芯片焊盘连接到所述横线上，或者连接到未选择的导线末端。
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