WO2009081356A2 - Non-substrate type package with embedded power line - Google Patents

Non-substrate type package with embedded power line Download PDF

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Publication number
WO2009081356A2
WO2009081356A2 PCT/IB2008/055440 IB2008055440W WO2009081356A2 WO 2009081356 A2 WO2009081356 A2 WO 2009081356A2 IB 2008055440 W IB2008055440 W IB 2008055440W WO 2009081356 A2 WO2009081356 A2 WO 2009081356A2
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WO
WIPO (PCT)
Prior art keywords
power supply
band
contact pins
contact
semiconductor die
Prior art date
Application number
PCT/IB2008/055440
Other languages
French (fr)
Other versions
WO2009081356A3 (en
Inventor
Xavier Paris
Laurie Dupont-Janssen
Original Assignee
Nxp B.V.
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009081356A2 publication Critical patent/WO2009081356A2/en
Publication of WO2009081356A3 publication Critical patent/WO2009081356A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • Power supply connecting wires are connected at a first end to power supply contacts of the semiconductor die and at a second end to a respective location of the at least a power supply band.
  • Connecting wires are connected at a first end to contacts other than power supply contacts of the semiconductor die and at a second end to a respective contact pin.
  • An encapsulation accommodates the semiconductor die, the connecting wires and, a portion of each contact pin, and the at least a power supply band therein.
  • two or more power supply bands HOD and HOE are provided on each side - oriented substantially parallel to each other and connected at each end to different contact pins 108, for example, the power supply band 11OD is connected to the first contact pin 108.1 and the last contact pin 108.N, while the power supply band HOE is connected to the second contact pin 108.2 and the second last contact pin 108.N-1.
  • provision of two parallel power supply bands HOD and HOE connected to different contact pins 108 enables provision of two different types of power supplies - for example having a different voltage - or in situations where there is a risk of interference when power is supplied from a same source.
  • Fig. 110 implemented in a QFP type package where, compared to the embodiments shown in Figs 2a to 2d, the number of contact pins used for connecting power supply bands 11OG is reduced.
  • FIG. 3 a four power supply bands HOG are disposed on each of the four sides and are connected on a first side - with a first end connected to the first contact pin 108.1 - and on a second consecutive side - with a second end connected to the first contact pin 108.1.
  • the second end of a power supply band HOG and the first end of a consecutive power supply band 11OG are connected to a same contact pin 108.1 on a same side.
  • power supply bands HOK are connected at a first end to a contact pin located in proximity of the center of the first side and at a second end to a contact pin located in proximity of the center of a second consecutive side.
  • Each power supply band HOK comprises a first portion oriented substantially parallel to a first side and a second portion oriented substantially parallel to a second consecutive side.
  • the second end of a power supply band 11OK and the first end of a consecutive power supply band 11OK are connected to a same contact pin on a same side.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a non-substrate type IC packaging with embedded power line. The packaging comprises a base having a die attach section upon which a semiconductor die is accommodated. A plurality of contact pins are disposed on the base along at least a side of the die attach section. At least a power supply band is disposed on the base between the contact pins and the die attach section. Each of the at least a power supply band is connected to at least a contact pin and is shaped such that provision of a substrate for holding the same in place is obviated. Power supply connecting wires are connected at a first end to power supply contacts of the semiconductor die and at a second end to a respective location of the at least a power supply band. Connecting wires are connected at a first end to contacts other than power supply contacts of the semiconductor die and at a second end to a respective contact pin. An encapsulation accommodates the semiconductor die, the connecting wires and, a portion of each contact pin, and the at least a power supply band therein.

Description

NON-SUBSTRATE TYPE PACKAGE WITH EMBEDDED POWER LINE
This invention relates generally to the field of Integrated Circuit (IC) packaging and more particularly to a non-substrate type packaging with embedded power line.
With increasing complexity, higher operating frequency, and increasing employment of high-speed external interfaces, the power consumption of present day ICs also increases. The direct consequence is an increase in contact pads needed to provide power to the IC, i.e. the number of contact pads to which a semiconductor die has to be connected to and a corresponding number of package pins which then have to be connected on the outside of the IC is substantially increased.
For example, in large Systems On Chip (SoCs) - usually comprising high speed interfaces such as DDRAM - the total number of contact pads - power and functional - is such that a substrate type package having one or more power rings embedded therein is needed. The power rings are connected to only a small number of package pins, while as many power contact pads as needed are connected to the power rings.
However, substrate type packages such as, for example, Ball Grid Arrays (BGAs) several disadvantages. The substrate type packages are cost intensive to manufacture and require a complex soldering process for connecting to an application board compared to non-substrate type packages such as, for example, Quad Flat Packages (QFPs). Furthermore, once the substrate type package is soldered to the application board, it is very difficult to inspect for soldering defects requiring special X-ray machines or special microscopes for inspection. Another disadvantage is that bending due to a difference in the coefficient of thermal expansion between the substrate type package and the application board; flexing; or vibration are potential causes for the solder joints to fracture. Therefore, substrate type packages are usually avoided in, for example, aerospace and military applications.
It would be highly desirable to overcome these drawbacks and to provide a non-substrate type IC packaging with embedded power line.
In accordance with the present invention there is provided a non-substrate type IC packaging with embedded power line. The packaging comprises a base having a die attach section upon which a semiconductor die is accommodated. A plurality of contact pins are disposed on the base along at least a side of the die attach section. At least a power supply band is disposed on the base between the contact pins and the die attach section. Each of the at least a power supply band is connected to at least a contact pin and is shaped such that provision of a substrate for holding the same in place is obviated. Power supply connecting wires are connected at a first end to power supply contacts of the semiconductor die and at a second end to a respective location of the at least a power supply band. Connecting wires are connected at a first end to contacts other than power supply contacts of the semiconductor die and at a second end to a respective contact pin. An encapsulation accommodates the semiconductor die, the connecting wires and, a portion of each contact pin, and the at least a power supply band therein.
In accordance with the present invention there is further provided a storage medium having stored therein executable commands for execution on a processor. The executable commands for when executed result in an integrated circuit package design. The packaging comprises a base having a die attach section upon which a semiconductor die is accommodated. A plurality of contact pins are disposed on the base along at least a side of the die attach section. At least a power supply band is disposed on the base between the contact pins and the die attach section. Each of the at least a power supply band is connected to at least a contact pin and is shaped such that provision of a substrate for holding the same in place is obviated. Power supply connecting wires are connected at a first end to power supply contacts of the semiconductor die and at a second end to a respective location of the at least a power supply band. Connecting wires are connected at a first end to contacts other than power supply contacts of the semiconductor die and at a second end to a respective contact pin. An encapsulation accommodates the semiconductor die, the connecting wires and, a portion of each contact pin, and the at least a power supply band therein.
Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which: Fig. 1 is a simplified block diagram illustrating a cross-sectional view of a non-substrate type IC packaging with embedded power line according to the invention; and,
Figs. 2a to 2d, Figs. 3a to 3f, and Figs. 4a to 4c are a simplified block diagrams illustrating top views of different embodiments of the power supply bands according to the invention. The following description is presented to enable a person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments disclosed, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
While the invention will be described for implementation in QFPs and Small- Outline Packages (SOPs), it will become apparent to those skilled in the art that the invention is not limited thereto but is also applicable for implementation in various other non-substrate type IC packages.
Referring to Fig. 1 , a non-substrate type IC packaging with embedded power line 100 according to the invention is shown in a cross-sectional view. The packaging 100 comprises a base 102 having a die attach section 104 upon which a semiconductor die 106 - for example, a SoC - is accommodated. A plurality of contact pins 108 are disposed on the base 102 along at least a side of the die attach section 104, for example, the semiconductor die forms a rectangle and the contact pins 108 are disposed along all four sides - in QFPs - or along two opposite sides - in SOPs. At least a power supply band 110 is disposed on the base 102 between the contact pins 108 and the die attach section 104. Power supply connecting wires 112 are connected at a first end to power supply contacts 114 of the semiconductor die 106 and at a second end to a respective location of the at least a power supply band 110.
Connecting wires 116 are connected at a first end to contacts 118 other than power supply contacts of the semiconductor die 106 and at a second end to a respective contact pin 108. An encapsulation 120 accommodates the semiconductor die 106, the connecting wires 112 and 116, a portion of each contact pin 108, and the at least a power supply band 110 therein.
Referring to Figs. 2a to 2d, 3a to 3f, and 4a to 4c, top views of different embodiments of the power supply bands 110 and, optionally, bands for supplying other than power according to the invention are illustrated. According to the invention, the power supply bands 110 are connected to at least a contact pin 108 and are shaped such that provision of a substrate for holding the same in place is obviated. For example, by connecting each of the power supply bands 110 to two contact pins 108, it is possible to provide various shapes of the power supply bands 110 that are securely hold in place by the two connections to the respective contact pins 108. As will become evident to those skilled in the art, the different shapes described hereinbelow are examples only and the invention is not limited thereto. A person of skill in the art will readily arrive at different shapes for implementation with QFPs and SOPs as well as different shapes for other non-substrate type IC packages. Furthermore, while described only as power supply bands for simplicity, it is also possible to use such bands for provision of other than power such as, for example, a ground connection or a signal that needs to be provided to a plurality of contact pins of the semiconductor die 106. Figs. 2a to 2d illustrate four different embodiments of the power supply bands
110 implemented in a QFP type package. Referring to Fig. 2a, the power supply bands 11OA are disposed on each of the four sides and are connected on each side to two contact pins 108 - with a first end connected to the first contact pin 108.1 and a second opposite end connected to the last contact pin 108. N on each side. On each side the power supply bands HOA are disposed between the respective row of contact pins 108 and the respective side of the die attach section 104, and are oriented substantially parallel to thereto. Of course, it is also possible to connect the power supply bands to other contact pins, however, at the expense of the length of the power supply band 11OA.
Alternatively, two or more power supply bands HOB and HOC are provided on each side - oriented substantially parallel to each other and connected at each end to a same contact pin, as illustrated in Fig. 2b. For example, provision of two parallel power supply bands 11OB and 11OC is beneficial in situations where provision of only one power supply band necessitates bonding of two or more power supply connecting wires 112 in too close proximity to each other on the power supply band causing interference during the bonding process.
Referring to Fig. 2c, two or more power supply bands HOD and HOE are provided on each side - oriented substantially parallel to each other and connected at each end to different contact pins 108, for example, the power supply band 11OD is connected to the first contact pin 108.1 and the last contact pin 108.N, while the power supply band HOE is connected to the second contact pin 108.2 and the second last contact pin 108.N-1. For example, provision of two parallel power supply bands HOD and HOE connected to different contact pins 108 enables provision of two different types of power supplies - for example having a different voltage - or in situations where there is a risk of interference when power is supplied from a same source. Alternatively, one or more of the bands 110D, 11OE is used to supply other than power, for example, a ground connection or a signal that needs to be provided to a plurality of contact pins of the semiconductor die 106. Of course, it is possible to incorporate the embodiment illustrated in Fig. 2b into the embodiment illustrated in Fig. 2c. Referring to Fig. 2d, another embodiment of the power supply band 110 is shown. Here, a first portion of power supply band 11OF is connected to contact pin 108.x and a second opposite portion of the power supply band 11OF is connected to contact pin 108. x+y with the first and the second portion extending from the respective connecting location. Provision of the power supply band 11OF enables provision of a power supply band having a greater length than the distance between the two contact pins connected thereto, for example, when the first and last contact pin are used as functional contact pins. Of course, it is possible to incorporate the embodiment illustrated in Fig. 2d into the embodiments illustrated in Fig. 2b and 2c. Figs. 3a to 3f illustrate six different embodiments of the power supply bands
110 implemented in a QFP type package where, compared to the embodiments shown in Figs 2a to 2d, the number of contact pins used for connecting power supply bands 11OG is reduced. Referring to Fig. 3 a, four power supply bands HOG are disposed on each of the four sides and are connected on a first side - with a first end connected to the first contact pin 108.1 - and on a second consecutive side - with a second end connected to the first contact pin 108.1. The second end of a power supply band HOG and the first end of a consecutive power supply band 11OG are connected to a same contact pin 108.1 on a same side. On each side the power supply bands HOG are disposed between the respective row of contact pins 108 and the respective side of the die attach section 104, and are oriented substantially parallel to thereto. It is possible to incorporate parallel power supply bands connected to the same contact pins, as illustrated in Fig. 2b, in a similar fashion. It is further possible to provide one or more other power supply bands 11OH connected to two contact pins on a same side and oriented substantially parallel to the power supply bands 11OG, as illustrated in Fig. 3b. Alternatively, one or more of the bands 11OH is used to supply other than power, for example, a ground connection or a signal that needs to be provided to a plurality of contact pins of the semiconductor die 106.
Referring to Fig. 3 c, two power supply bands 1101 are connected with a first end to the first contact pin 108.1 on a first side and with a second end to the first contact pin 108.1 on a second opposite side. Each power supply band 1101 comprises a first portion oriented substantially parallel to a first side and a second portion oriented substantially parallel to a second consecutive side. The second end of a power supply band 1101 and the first end of a consecutive power supply band 1101 are connected to a same contact pin 108.1 on a same side. On each side the respective portions of the power supply bands 1101 are disposed between the respective row of contact pins 108 and the respective side of the die attach section 104, and are oriented substantially parallel to thereto. Here, the number of contact pins 108 for connecting the power supply bands 1101 is further reduced - to two contact pins. It is possible to incorporate parallel power supply bands connected to the same contact pins, as illustrated in Fig. 2b, in a similar fashion. It is further possible to provide one or more other power supply bands HOJ connected to a contact pin on a first side and a second contact pin on a consecutive second side with a first portion oriented substantially parallel to the first portion of the power supply bands 1101 and with a second portion oriented substantially parallel to the second portion of the power supply bands 1101, as illustrated in Fig. 3d. Alternatively, one or more of the bands 110J is used to supply other than power, for example, a ground connection or a signal that needs to be provided to a plurality of contact pins of the semiconductor die 106.
Referring to Fig. 3e, a variant of the embodiment illustrated in Fig. 3 a is shown. Here, power supply bands HOK are connected at a first end to a contact pin located in proximity of the center of the first side and at a second end to a contact pin located in proximity of the center of a second consecutive side. Each power supply band HOK comprises a first portion oriented substantially parallel to a first side and a second portion oriented substantially parallel to a second consecutive side. The second end of a power supply band 11OK and the first end of a consecutive power supply band 11OK are connected to a same contact pin on a same side. On each side the respective portions of the power supply bands 11OK are disposed between the respective row of contact pins 108 and the respective side of the die attach section 104, and are oriented substantially parallel to thereto. Of course, it is also possible to connect the ends of the power supply bands to contact pins placed at any location between the center and the first and last contact pin on each side. It is further possible to incorporate parallel power supply bands connected to the same contact pins, as illustrated in Fig. 2b, in a similar fashion, as well as to provide one or more other power supply bands connected to other contact pins on a first side and a second contact pin on a consecutive second side with a first portion oriented substantially parallel to the first portion of the power supply band 11OK and a second portion oriented substantially parallel to the second portion of the power supply band 110K.
Referring to Fig. 3f, a variant of the embodiment illustrated in Fig. 3c is shown. Here, power supply bands 11OL are connected at a first end to a contact pin located in proximity of the center of the first side and at a second end to a contact pin located in proximity of the center of a second opposite side. Each power supply band 11OL comprises a first portion oriented substantially parallel to a first side, a second portion oriented substantially parallel to a second consecutive side, and a third portion oriented substantially parallel to the opposite side. The second end of a power supply band HOL and the first end of a consecutive power supply band HOL are connected to a same contact pin on a same side.
On each side the respective portions of the power supply bands 11OL are disposed between the respective row of contact pins 108 and the respective side of the die attach section 104, and are oriented substantially parallel to thereto. Of course, it is also possible to connect the ends of the power supply bands to contact pins placed at any location between the center and the first and last contact pin on each side. It is further possible to incorporate parallel power supply bands connected to the same contact pins, as illustrated in Fig. 2b, in a similar fashion, as well as to provide one or more other power supply bands connected to other contact pins on a first side and a second contact pin on the opposite side with a first portion oriented substantially parallel to the first portion of the power supply band 11OL, a second portion oriented substantially parallel to the second portion of the power supply band 11OL, and a third portion oriented substantially parallel to the third portion of the power supply band 11OL.
Figs. 4a to 4c illustrate three different embodiments of the power supply bands 110 implemented in a SOP type package. Fig. 4a illustrates a similar embodiment to the one shown in Fig. 2a, however with only two power supply bands 110 disposed on two opposite sides. Figs. 4b and 4c illustrate similar embodiments to the ones shown in Figs. 3c and 3f, respectively, providing power supply along four sides while being connected to two contact pins on two opposite sides of the SOP. Of course, it is possible to incorporate various variations as described above into the embodiments illustrated in Figs. 4a to 4c. The non-substrate type IC packaging with embedded power line 100 according to the invention is manufactured using standard manufacturing processes. For example, the contact pins 108 and the power supply bands 110 are disposed on the base 102 as a single piece and affixed to the base using for example, an adhesive, followed by an etching process for producing the plurality of contact pins 108 and power supply bands 110. Alternatively, the power supply bands 110 are disposed on the base 102 after provision of the contact pins 108 and bonded to the respective contact pins 108 using, for example, a soldering process.
The power supply bands 110 are, for example, made of a metal such as aluminum, copper, silver, or gold. The power supply connecting wires 112 are connected to the power supply bands using, for example, standard soldering processes. The base 102 comprising the contact pins 108 and the power supply bands 110 are, for example, pre- manufactured - according to a standard type or custom specifications -and provided to an IC manufacturer which then attaches the semiconductor die, provides the wire connections and the encapsulation using standard manufacturing processes.
Knowing system requirements of the semiconductor die and contact pins, it is possible to design the various embodiments of the non-substrate type IC packaging with embedded power line according to the invention on a computer by executing commands based on the above description stored on a storage medium, for example, such that a length of the power supply connecting wires 112 is minimized. Furthermore, using the flexibility provided by the power supply band it is possible to design semiconductor circuits having numerous power supply contacts in order to reduce voltage drop as well as impedance.
Numerous other embodiments of the invention will be apparent to persons skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

What is claimed is:
1. A device comprising: a base having a die attach section for accommodating a semiconductor die thereupon, the base being other than a substrate; a plurality of contact pins disposed on the base along at least a side of the die attach section, at least a portion of the plurality of contact pins for being connected at a first end portion to respective contacts of the semiconductor die; and, at least a power supply band connected at a first portion to a contact pin of the plurality of contact pins and at a second portion to another contact pin of the plurality of contact pins, the at least a power supply band being disposed on the base between the plurality of contact pins and the at least a side of the die attach section oriented substantially parallel thereto, the at least a power supply band for being connected to a plurality of power supply contacts of the semiconductor die.
2. A device as defined in claim 1 wherein the at least a power supply bands are connected to contact pins disposed on a same side.
3. A device as defined in claim 2 wherein the at least a power supply bands are connected to a first and a last contact pin disposed on the side.
4. A device as defined in claim 2 wherein at least two power supply bands are connected to same contact pins.
5. A device as defined in claim 2 wherein at least two power supply bands are connected to different contact pins and wherein the at least two power supply bands are for providing at least two different types of power.
6. A device as defined in claim 2 comprising at least a band for provision of other than power connected at a first portion to at least a contact pin of the plurality of contact pins and at a second portion to at least another contact pin of the plurality of contact pins, the at least a band being oriented substantially parallel to the at least a power supply band.
7. A device as defined in claim 6 wherein the at least a band for provision of other than power is for providing a connection to ground.
8. A device as defined in claim 2 wherein the die attach section is of rectangular shape and wherein the at least a power supply band are disposed on two opposite sides.
9. A device as defined in claim 1 wherein the at least a power supply band are connected at the first portion to contact pins disposed on a first side and at the second portion to contact pins disposed on a second other side.
10. A device as defined in claim 9 wherein the die attach section is of rectangular shape and wherein the at least a power supply band are disposed on each side with the second other side being a consecutive side.
11. A device as defined in claim 9 wherein the at least a power supply band are connected to a first contact pin of each side.
12. A device as defined in claim 9 wherein at least two power supply bands are connected to same contact pins.
13. A device as defined in claim 9 wherein at least two power supply bands are connected to different contact pins and wherein the at least two power supply bands are for providing at least two different types of power.
14. A device as defined in claim 9 comprising at least a band for provision of other than power connected at a first portion to at least a contact pin of the plurality of contact pins and at a second portion to at least another contact pin of the plurality of contact pins, the at least a band being oriented substantially parallel to the at least a power supply band.
15. A device as defined in claim 14 wherein the at least a band for provision of other than power is for providing a connection to ground.
16. A device as defined in claim 1 wherein the at least a power supply band and respective contact pins form a single piece.
17. A device as defined in claim 1 comprising: a semiconductor die accommodated on the die attach section; a plurality of connecting wires, each connecting wire connected at a first end to a contact other than a power supply contact of the semiconductor die and at a second end to a respective contact pin; a plurality of power supply connecting wires, each power supply connecting wire connected at a first end to a power supply contact of the semiconductor die and at a second end to a respective location of the at least a power supply band; and, an encapsulation accommodating the semiconductor die, the connecting wires, a portion of each contact pin, and the at least a power supply band therein.
18. A device as defined in claim 17 wherein the power supply connecting wires are connected to respective locations of the at least a power supply band such that a distance between the power supply contact of the semiconductor die and the respective location is minimized.
19. A device as defined in claim 17 wherein the semiconductor die is of rectangular shape and wherein the contact pins are disposed on two opposite sides.
20. A device as defined in claim 17 wherein the semiconductor die is of rectangular shape and wherein the contact pins are disposed on each side.
21. A device as defined in claim 17 wherein the semiconductor die is a system on a chip.
22. A storage medium having stored therein executable commands for execution on a processor, the executable commands for when executed resulting in an integrated circuit package design comprising: a base having a die attach section for accommodating a semiconductor die thereupon, the base being other than a substrate; a plurality of contact pins disposed on the base along at least a side of the die attach section, at least a portion of the plurality of contact pins for being connected at a first end portion to respective contacts of the semiconductor die; and, at least a power supply band connected at a first portion to a contact pin of the plurality of contact pins and at a second portion to another contact pin of the plurality of contact pins, the at least a power supply band being disposed on the base between the plurality of contact pins and the at least a side of the die attach section oriented substantially parallel thereto, the at least a power supply band for being connected to a plurality of power supply contacts of the semiconductor die.
23. A storage medium having stored therein executable commands for execution on a processor as defined in claim 22, the executable commands for when executed resulting in an integrated circuit package design comprising: a semiconductor die accommodated on the die attach section; a plurality of connecting wires, each connecting wire connected at a first end to a contact other than a power supply contact of the semiconductor die and at a second end to a respective contact pin; a plurality of power supply connecting wires, each power supply connecting wire connected at a first end to a power supply contact of the semiconductor die and at a second end to a respective location of the at least a power supply band; and, an encapsulation accommodating the semiconductor die, the connecting wires, a portion of each contact pin, and the at least a power supply band therein.
24. A storage medium having stored therein executable commands for execution on a processor as defined in claim 23, the executable commands for when executed resulting in an integrated circuit package design wherein the power supply connecting wires are connected to respective locations of the at least a power supply band such that a distance between the power supply contact of the semiconductor die and the respective location is minimized.
PCT/IB2008/055440 2007-12-19 2008-12-19 Non-substrate type package with embedded power line WO2009081356A2 (en)

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Application Number Priority Date Filing Date Title
EP07291577 2007-12-19
EP07291577.0 2007-12-19

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US5763296A (en) * 1991-11-21 1998-06-09 Sgs-Thomson Microelectronics S.R.L. Method for fabricating an electronic device structure with studs locating lead frame on backing plate
US5457340A (en) * 1992-12-07 1995-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
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