CN103811311B - 用以改善线宽稳定性的SiON表面处理方法 - Google Patents

用以改善线宽稳定性的SiON表面处理方法 Download PDF

Info

Publication number
CN103811311B
CN103811311B CN201210458254.9A CN201210458254A CN103811311B CN 103811311 B CN103811311 B CN 103811311B CN 201210458254 A CN201210458254 A CN 201210458254A CN 103811311 B CN103811311 B CN 103811311B
Authority
CN
China
Prior art keywords
sion
thin film
stability
live width
improve
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210458254.9A
Other languages
English (en)
Other versions
CN103811311A (zh
Inventor
虞颖
刘改花
郭振华
王雷
刘鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201210458254.9A priority Critical patent/CN103811311B/zh
Publication of CN103811311A publication Critical patent/CN103811311A/zh
Application granted granted Critical
Publication of CN103811311B publication Critical patent/CN103811311B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明公开了一种用以改善线宽稳定性的SiON表面处理方法，该方法在SiON薄膜沉积后，进行光刻工艺前，用水汽、氧气和氮气的混合气体的等离子体对SiON薄膜进行前处理。通过对SiON抗反射层的表面进行特殊的前处理，有效地改善了0.13μm制程的光刻过程及重新光刻过程中线宽的稳定性。

Description

用以改善线宽稳定性的SiON表面处理方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种用以改善线宽稳定性的SiON表面处理方法。
背景技术
在半导体制造工艺中，稳定的ADI/AEI CD（光刻/干刻后关键尺寸）对于半导体产品的良率及可靠性的提升具有非常重要的作用。但是，随着CD(Critical Dimension，关键尺寸)的越来越小，光刻后关键尺寸的稳定性很容易受到前层薄膜或者rework process（返工工艺）等因素的影响而变差。尤其是在0.13μm制程中，第一金属层的光刻后关键尺寸需要控制在0.135μm左右，此时，光刻后关键尺寸的稳定性更容易变差。
为了提高CD的稳定性，可以在工艺中增加SiON（氮氧化硅）抗反射层，即在晶圆表面的金属薄膜的上面再沉积一层SiON薄膜，然后再进行光刻工艺，如图1所示。但是，即使增加了SiON抗反射层，CD的稳定性仍不够好。如表1和图2所示，在经过了一次Photo rework（光刻返工工艺）之后，CD（一般用Hitachi CD-SEM CD量测机台量测）变小了5nm左右，这对于0.13μm制程来讲是绝对不允许的，因此，需要找出一种方法来提高CD的稳定性。
表1 Photo返工工艺对CD稳定性的影响
发明内容
本发明要解决的技术问题是提供一种用以改善线宽稳定性的SiON表面处理方法，它可以提高线宽的稳定性。
为解决上述技术问题，本发明的用以改善线宽稳定性的SiON表面处理方法，是在SiON薄膜沉积后，进行光刻工艺前，用水汽、氧气和氮气的混合气体的等离子体对SiON薄膜进行前处理。
本发明通过对SiON抗反射层的表面进行特殊的前处理，有效地提高了0.13μm制程的光刻过程及重新光刻过程中线宽的稳定性。
附图说明
图1是常规的光刻工艺流程示意图。
图2是光刻返工工艺对线宽稳定性的影响图，图中数据采用表1的数据。
图3是本发明实施例增加了SiON前处理步骤的光刻工艺流程示意图。
图4是用不同配比的混合气体对晶圆表面SiON薄膜进行前处理得到的CD稳定性结果。
图5是光刻返工工艺对线宽稳定性的影响图，图中数据采用表3的数据。
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合图示的实施方式，详述如下：
本实施例在SiON薄膜沉积后，进行光刻工艺之前，对SiON薄膜进行了特殊的前处理，具体方法如下（参见图3）：
首先，用常规工艺完成SiON抗反射层的沉积，得到表面是SiON薄膜的晶圆，如图3（a）所示。晶圆表面从上往下依次为：SiON薄膜，金属（铝）薄膜。
然后，将上述制备的晶圆置入反应腔中，通入H2O（水汽）、O2（氧气）和N2（氮气）三种气体的混合气体，用微波电源产生等离子体（条件：射频功率为0～1500瓦，腔体压力为1～3托），等离子体与晶圆表面的SiON薄膜发生反应，如图3（b）所示。
上述混合气体中，H2O的流量为500～1000sccm，O2的流量为1000～5000sccm，N2的流量为100～300sccm。
对SiON薄膜的上述前处理完成后，进行正常的光刻工艺，如图3（c）所示。
用不同配比的气体（见表2）的等离子体，对晶圆表面的SiON薄膜进行前处理，并对反应后的晶圆进行外观形貌和关键尺寸大小确认，得到如表2和图4所示的结果。可以看出，在使用本实施例的方法对SiON抗反射层进行前处理后，晶圆的光刻后关键尺寸的稳定性明显变好，其中，以晶圆4（W4）的关键尺寸的稳定性为最好。
表2 不同配比的气体对SiON薄膜在不同实验条件下的结果
采用表2中晶圆4的气体配比条件对多片晶圆表面的SiON薄膜进行前处理，然后进行Photo rework实验，得到如表3和图5所示的结果。从表3的数据可以看出，第一次光刻和两次rework间的关键尺寸的差异都在2nm以内，显示了很好的关键尺寸稳定性。
表3 Photo返工工艺对关键尺寸稳定性的影响

Claims (1)

1.用以改善线宽稳定性的SiON表面处理方法，其特征在于，在SiON薄膜沉积后，进行光刻工艺前，用水汽、氧气和氮气的混合气体的等离子体对SiON薄膜进行前处理，等离子体用微波电源产生，条件为：射频功率0～1500瓦，腔体压力1～3托，水汽的流量为500～1000sccm，氧气的流量为1000～5000sccm，氮气的流量为100～300sccm，混合气体分两步通入，第一步通水汽30秒，第二步通氧气和氮气的混合气体60秒。
CN201210458254.9A 2012-11-15 2012-11-15 用以改善线宽稳定性的SiON表面处理方法 Active CN103811311B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210458254.9A CN103811311B (zh) 2012-11-15 2012-11-15 用以改善线宽稳定性的SiON表面处理方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210458254.9A CN103811311B (zh) 2012-11-15 2012-11-15 用以改善线宽稳定性的SiON表面处理方法

Publications (2)

Publication Number Publication Date
CN103811311A CN103811311A (zh) 2014-05-21
CN103811311B true CN103811311B (zh) 2016-10-26

Family

ID=50707928

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210458254.9A Active CN103811311B (zh) 2012-11-15 2012-11-15 用以改善线宽稳定性的SiON表面处理方法

Country Status (1)

Country Link
CN (1) CN103811311B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174816B1 (en) * 1998-09-03 2001-01-16 Micron Technology, Inc. Treatment for film surface to reduce photo footing
CN1388582A (zh) * 2001-05-25 2003-01-01 株式会社东芝 半导体器件
US6573189B1 (en) * 2001-11-07 2003-06-03 Taiwan Semiconductor Manufacturing Company Manufacture method of metal bottom ARC
JP2006278836A (ja) * 2005-03-30 2006-10-12 Tokyo Electron Ltd エッチング方法、エッチング装置、コンピュータプログラム及びコンピュータ記憶媒体
CN1867695A (zh) * 2003-11-06 2006-11-22 东京毅力科创株式会社 改善沉积的介电膜上的显影后光刻胶外形的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174816B1 (en) * 1998-09-03 2001-01-16 Micron Technology, Inc. Treatment for film surface to reduce photo footing
CN1388582A (zh) * 2001-05-25 2003-01-01 株式会社东芝 半导体器件
US6573189B1 (en) * 2001-11-07 2003-06-03 Taiwan Semiconductor Manufacturing Company Manufacture method of metal bottom ARC
CN1867695A (zh) * 2003-11-06 2006-11-22 东京毅力科创株式会社 改善沉积的介电膜上的显影后光刻胶外形的方法
JP2006278836A (ja) * 2005-03-30 2006-10-12 Tokyo Electron Ltd エッチング方法、エッチング装置、コンピュータプログラム及びコンピュータ記憶媒体

Also Published As

Publication number Publication date
CN103811311A (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
CN105190840B (zh) 用于多图案化应用的光调谐硬掩模
US8465903B2 (en) Radiation patternable CVD film
JP6139505B2 (ja) 枚葉式基板処理のためのエッチングシステム及び方法
CN105097664B (zh) 一种用于集成电路的结构和制造集成电路的方法
US20160329221A1 (en) Isotropic atomic layer etch for silicon oxides using no activation
JP5419167B2 (ja) 半導体装置の製造方法および半導体装置
TW201828339A (zh) 於半導體裝置製造中高品質氧化矽之低溫形成
TWI479563B (zh) 基板處理方法
KR101194192B1 (ko) 어모퍼스 카본 나이트라이드막의 형성 방법, 어모퍼스 카본 나이트라이드막, 다층 레지스트막, 반도체 장치의 제조 방법 및 제어 프로그램이 기억된 기억 매체
JP6081442B2 (ja) マスク層のエッチング速度と選択性の増大
JP2010161162A (ja) 微細パターンの形成方法
KR102082803B1 (ko) 실리콘 다이옥사이드 기판의 식각 방법 및 식각 장치
US9133352B2 (en) Surface treatment agent and surface treatment method
JP2006013190A (ja) 半導体装置の製造方法
CN103137469A (zh) 一种非感光性聚酰亚胺钝化层的制作方法
US20110118494A1 (en) Surface treatment agent and surface treatment method
JP4950188B2 (ja) 層間絶縁膜のドライエッチング方法
JP2014107520A (ja) プラズマエッチング方法
CN103811311B (zh) 用以改善线宽稳定性的SiON表面处理方法
JP2008130604A (ja) 半導体装置の製造方法
CN104253081A (zh) 半导体器件的形成方法
US20100068892A1 (en) Substrate processing method
Kim et al. Investigation of oxide layer removal mechanism using reactive gases
TW201707139A (zh) 半導體裝置之製造方法
US20140370709A1 (en) Methods for reducing line width roughness and/or critical dimension nonuniformity in a patterned photoresist layer

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant