CN103715107B - 封装堆栈结构的制法 - Google Patents

封装堆栈结构的制法 Download PDF

Info

Publication number
CN103715107B
CN103715107B CN201210401126.0A CN201210401126A CN103715107B CN 103715107 B CN103715107 B CN 103715107B CN 201210401126 A CN201210401126 A CN 201210401126A CN 103715107 B CN103715107 B CN 103715107B
Authority
CN
China
Prior art keywords
semiconductor
preparation
semiconductor package
stack architecture
packing colloid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210401126.0A
Other languages
English (en)
Other versions
CN103715107A (zh
Inventor
郑秉凯
蔡文山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN103715107A publication Critical patent/CN103715107A/zh
Application granted granted Critical
Publication of CN103715107B publication Critical patent/CN103715107B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种封装堆栈结构的制法，其提供一形成有封装胶体的半导体封装件及一具有半导体组件的基板，再将该半导体封装件与该基板进行对接，使该封装胶体压合于该基板上而包覆该半导体组件，借以降低压力与温度的影响，使该基板与该封装胶体的整体结构不易发生翘曲，而可容易制作超过两层的封装堆栈结构。

Description

封装堆栈结构的制法
技术领域
本发明有关一种封装堆栈结构的制法，尤指一种能节省制作成本的封装堆栈结构的制法。
背景技术
随着半导体封装技术的演进，半导体装置（Semiconductor device）已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装件以形成封装堆栈结构，借以达到系统的整合。
图1A至图1C为现有封装堆栈结构1的制法的剖面示意图。
如图1A所示，以激光方式形成多个开孔100于一下方半导体封装件1a的封装胶体13上，令该下方半导体封装件1a的第一电性接触垫101外露出该开孔100。其中，该下方半导体封装件1a具有半导体芯片11。
如图1B所示，形成多个焊料凸块14a于该开孔100中的第一电性接触垫101上，且还形成多个焊料凸块14b于一上方半导体封装件1b的第二电性接触垫102上。其中，该上方半导体封装件1b具有半导体芯片（图略）。
如图1C所示，将该上方半导体封装件1b的焊料凸块14b对应结合该下方半导体封装件1a的焊料凸块14a以回焊形成焊接点14，使该上方半导体封装件1b堆栈于该下方半导体封装件1a上，且该上方半导体封装件1b电性连接该下方半导体封装件1a。
然而，现有封装堆栈结构1的制法中，激光开孔的工艺精度有限，致使该开孔100的位置容易偏差而不易对位于该第一电性接触垫101上，且容易影响该开孔100的深度而使该焊接点14产生变异，例如，该开孔100太深将使该焊料凸块14a,14b无法连接、该开孔100太浅将使该焊接点14因接合压力而受损或接触邻近的焊接点14（当回焊该焊料凸块14a,14b时，若该开孔100太浅，其孔中的焊料会融化溢出粘合邻近开孔100中的焊料，造成该些焊接点14之间发生桥接）。
此外，现有封装堆栈结构1的制法中，需先制作完成所需的封装件，再进行激光开孔工艺，之后再堆栈接合各封装件，所以不仅其工艺步骤繁杂及成本高，且容易有产量不佳的问题。
另外，该下方半导体封装件1a或上方半导体封装件1b于模压工艺（即形成该封装胶体13）时，该下方半导体封装件1a或上方半导体封装件1b容易因温度与压力而发生翘曲，致使堆栈愈多层的封装件，各该封装件之间愈无法对接，所以现有封装堆栈结构1的堆栈层数较难超过两层，致使其难以制作超过两层的多层的堆栈结构。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种不足，本发明的主要目的在于提供一种封装堆栈结构的制法，使该基板与该封装胶体的整体结构不易发生翘曲，而可容易制作超过两层的封装堆栈结构。
本发明的封装堆栈结构的制法，包括：提供一基板，该基板表面上设有至少一半导体组件；以及将一半导体封装件以导电组件结合于该基板上，以令该半导体组件位于该基板与该半导体封装件之间，且形成封装胶体于该基板与该半导体封装件之间以包覆该半导体组件，并使该半导体封装件接触该封装胶体。
前述的制法中，该基板具有多个第一电性接触垫，且该半导体封装件具有多个第二电性接触垫，而该第一电性接触垫电性连接该第二电性接触垫，例如，该第一电性接触垫与第二电性接触垫之间借由该导电组件电性连接。此外，该导电组件包含焊锡材料及铜材。另外，该第一电性接触垫具有凹部。
前述的制法中，该半导体组件为堆栈芯片组或单一芯片。
前述的制法中，该半导体组件以打线方式或覆晶方式电性结合于该基板。
前述的制法中，形成该封装胶体的工艺包括：形成该封装胶体于该半导体封装件上；以及当该半导体封装件结合于该基板上时，该封装胶体包覆该半导体组件。于其中一方式，该封装胶体还形成于该基板上，而该半导体封装件上具有电子组件，且该封装胶体还包覆该电子组件。
前述的制法中，形成该封装胶体的工艺包括：结合该半导体封装件于该基板上；以及将该封装胶体填入该基板与该半导体封装件之间，以包覆该半导体组件。
前述的制法中，该导电组件为导电凸块、导电柱或导电球。
另外，前述的制法中，还包括于该封装胶体包覆该半导体组件后，形成另一半导体封装件于该半导体封装件上。
由上可知，本发明的封装堆栈结构的制法，借由具有半导体组件的基板不进行模压工艺，而当该半导体封装件与该基板对接后，再使封装胶体包覆该半导体组件，所以相比于现有膜压工艺，本发明的制法因减少温度与压力的影响，而使该基板不易发生翘曲，因而可借此方式不断进行堆栈工艺，使得制作超过两层的封装堆栈结构变得容易。
此外，本发明于对接前不需进行钻孔工艺，所以相比于现有制法，本发明的制法利于对位及电性接合，因而本发明的封装堆栈结构的产量较佳。
因此，本发明不仅克服现有技术的缺点，且工艺步骤简化、工艺时间缩短及成本更低。
附图说明
图1A至图1C为现有封装堆栈结构的制法的剖视示意图；
图2A至图2C为本发明封装堆栈结构的制法的第一实施例的剖视示意图；其中，图2C’及图2C”分别为图2C的其它实施例；
图3A至图3B为本发明封装堆栈结构的制法的第二实施例的剖视示意图；其中，图3B’为图3B的另一实施例；
图4A至图4C为本发明封装堆栈结构的制法的第三实施例的剖视示意图；以及
图5A至图5B为本发明封装堆栈结构的制法的第四实施例的剖视示意图。
主要组件符号说明
1,2,2’,2”,3,3’,4,5 封装堆栈结构
1a,2a 下方半导体封装件
1b,5a 上方半导体封装件
100 开孔
101,200,200’ 第一电性接触垫
102,220 第二电性接触垫
11 半导体芯片
13,33 封装胶体
14 焊接点
14a,14b 焊料凸块
20 基板
20a 上表面
20b,22b,58b 下表面
200a 凹部
201 焊球
21,31,51 半导体组件
21a 顶侧
210 导电凸块
22 第一半导体封装件
221,302 挡块
222 封装材
23,43 第一封装胶体
24,24’,34,54 导电组件
24a,34a 铜凸块
24b,34b 焊锡材料
35 电子组件
36 第二封装胶体
57 第三封装胶体
58 第二半导体封装件。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、“第三”、“顶”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的封装堆栈结构2的制法的第一实施例的剖面示意图。
如图2A所示，一基板20的上表面20a上设有一半导体组件21及多个第一电性接触垫200。
于本实施例中，该半导体组件21为单一芯片，且借由多个导电凸块210以覆晶方式电性连接该基板20。于其它实施例中，该半导体组件21也可以打线方式（图略）电性连接该基板20。
此外，该些第一电性接触垫200位于该基板20的上表面20a四周，以围绕该半导体组件21。
再者，该基板20为具有内层线路的封装基板，且其下表面20b用以植设焊球201以供接置如电路板的电子装置（图略）。然而，用以承载芯片的基板种类繁多，并无特别限制，特此述明。
如图2B所示，提供一具有至少一半导体芯片（图略）的第一半导体封装件22，且以点胶或涂布方式形成第一封装胶体23于该第一半导体封装件22的下表面22b上。
于本实施例中，该第一半导体封装件22的下表面22b上具有多个第二电性接触垫220，且该些第二电性接触垫220位于该第一半导体封装件22的下表面22b四周，以对应该些第一电性接触垫200，并形成多个导电组件24于该些第二电性接触垫220上。于其它实施例中，还可形成多个导电组件24于该些第一电性接触垫200上。
此外，该些导电组件24可为焊料凸块、金属柱等，并无特别限制。
再者，该第一半导体封装件22的下表面22b上还形成有至少一挡块（dam）221，以限制形成该第一封装胶体23的范围，而防止该第一封装胶体23流至线路表面或该第二电性接触垫220表面。
另外，为了防止胶量不足，可依需求将挡块221的位置向该第一半导体封装件22的边缘偏移，使挡块221内的第一封装胶体23的胶量可增加；或者，可在完成图2C的工艺后，于侧边以点胶方式补强胶量。
另外，该第一半导体封装件22具有封装材222以包覆该第一半导体封装件22的半导体芯片。然，有关半导体封装件的种类繁多，并不限于上述，特此述明。
如图2C所示，将该些导电组件24对应结合于该些第一电性接触垫200上，使该第一半导体封装件22结合于该基板20上，并使该第一半导体封装件22接触该第一封装胶体23，以令该半导体组件21位于该基板20与该第一半导体封装件22之间，且该第一封装胶体23压合于该基板20与该第一半导体封装件22之间，以包覆该半导体组件21与该些导电组件24。之后再固化该第一封装胶体23。
于本实施例中，该第一封装胶体23形成于该半导体组件21的顶侧21a上，使该半导体组件21的顶侧21a未接触该第一半导体封装件22，而于其它实施例中，该第一封装胶体23也可不形成于该半导体组件21的顶侧21a上，也就是使该半导体组件21的顶侧21a接触该第一半导体封装件22。
此外，该第一电性接触垫200与第二电性接触垫220之间借由该些导电组件24电性连接，使该第一半导体封装件22电性连接该基板20。
再者，该基板20、该半导体组件21与该第一封装胶体23可视为一下方半导体封装件2a。
另外，如图2C’所示，该第一电性接触垫200’可具有凹部200a，以增加该导电组件24的接触面积，而提升该第一电性接触垫200’与该导电组件24的结合力，所以可增强该封装堆栈结构2’的可靠度。
制作该凹部200a的方式可使用Lithography技术，如先形成光阻或干膜（DryFilm）于该金属垫上，再经图案化曝光、显影成形，再电镀塡入金属、移除光阻而得到该凹部200a。
或者，如图2C”所示的封装堆栈结构2”的制法，该第一电性接触垫200或第二电性接触垫220上可先形成铜凸块24a，再形成焊锡材料24b于该铜凸块24a上，以令该铜凸块24a与该焊锡材料24b作为导电组件24’，其中，该铜凸块24a的含量占该导电组件24’至多为85重量份。
经回焊该焊锡材料24b，使该焊锡材料24b包覆该铜凸块24a，以增加该焊锡材料24b与铜材（即该第一电性接触垫200、第二电性接触垫220与铜凸块24a）的接触面积，而提升该第一电性接触垫200或第二电性接触垫220与该导电组件24’的结合力，所以可增强该导电组件24’的可靠度及电性。
图3A至图3B为本发明的封装堆栈结构3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于半导体组件31的种类及新增电子组件35与第二封装胶体36，其它工艺大致相同，所以不再赘述相同处。
如图3A所示，该第一半导体封装件22的下表面22b上还具有一电子组件35，且形成第二封装胶体36于该基板20的上表面20a上。
于本实施例中，该半导体组件31与该电子组件35为堆栈芯片组。然而，有关电子组件的种类繁多，并不限于上述，特此述明。
此外，该基板20的上表面20a上还设有至少一挡块（dam）302，以限制形成该第二封装胶体36的范围，而防止胶体流至线路表面或第一电性接触垫200表面。所述的挡块221,302为胶材，可与该封装胶体的材质相同，且该挡块221,302为半固化形态的胶，当封装胶体包覆组件后，该挡块221,302会融入该第一封装胶体23（或该封装胶体33）中而成为一体，再固化该第一封装胶体23（或该封装胶体33）。
再者，该第一封装胶体23的位置对应该半导体组件31，而该第二封装胶体36的位置对应该电子组件35。另外，该第一与第二封装胶体23,36的材质相同。
如图3B所示，借由导电组件24将该第一半导体封装件22结合于该基板20上，以令该半导体组件31与该电子组件35均位于该基板20与该第一半导体封装件22之间，且该第一封装胶体23与第二封装胶体36结合为一封装胶体33，以包覆该半导体组件31、该电子组件35与该些导电组件24。
于本实施例中，该封装胶体33形成于该电子组件35与该基板20之间，而于其它实施例中，该电子组件35接触该基板20。
另外，如图3B’所示的封装堆栈结构3’的制法，该导电组件34可由铜凸块34a与该焊锡材料34b构成。经回焊该焊锡材料24b，该铜凸块34a仍结合该第二电性接触垫220，而该焊锡材料24b结合该第一电性接触垫200而未包覆该铜凸块24a。
图4A至图4C为本发明的封装堆栈结构4的制法的第三实施例的剖面示意图。本实施例与第一实施例的差异在于形成该第一封装胶体43的工艺，其它工艺大致相同，所以不再赘述相同处。
如图4A所示，借由该些导电组件24将该第一半导体封装件22结合于该基板20上。
如图4B及图4C所示，借由填充方式，将该第一封装胶体43填入该基板20与该第一半导体封装件22之间，以包覆该半导体组件21与该些导电组件24。
本发明的制法可先点胶形成第一封装胶体23，再进行压合固化；或者，先进行对接，再填充固化第一封装胶体43。相比于现有膜压工艺，本发明的点胶固化方式或填充方式，因固化温度与压力极低，所以该下方半导体封装件2a不易发生翘曲，因而可借此方式不断进行堆栈工艺，使得制作超过两层的封装堆栈结构5变得容易，如下之第四实施例所述。
此外，本发明的制法中，于对接前不需进行钻孔工艺，所以该些导电组件24不需形成于孔中，因而该些导电组件24不受开孔的影响，也就是可设计面积较大的第一电性接触垫200或第二电性接触垫220，以容许较大的偏移误差。因此，相比于现有制法，本发明的制法利于该些导电组件24对位及电性接合，因而本发明的封装堆栈结构2,2’,3,4的产量较佳。
图5A至图5B为本发明的封装堆栈结构5的制法的第四实施例的剖面示意图。本实施例为第一或第三实施例的后续工艺，也就是继续形成其它半导体封装件于该封装堆栈结构2,4上，以形成另一封装堆栈结构5。
如图5A所示，依第一实施例的工艺，结合多个半导体组件51于该封装堆栈结构2的第一半导体封装件22的上表面22a上，且形成第三封装胶体57于一第二半导体封装件58的下表面58b上。
于本实施例中，该第一与第三封装胶体23,57的材质相同，且该些半导体组件51以覆晶方式电性连接该第一半导体封装件22。
此外，该第二半导体封装件58的构成与该第一半导体封装件22的构成相似，所以不再赘述。
如图5B所示，借由多个导电组件54，将第二半导体封装件58结合于该第一半导体封装件22上，以令该些半导体组件51位于该第一与第二半导体封装件22,58之间，且该第三封装胶体57包覆该些半导体组件51，使该第二半导体封装件58接触该第三封装胶体57。
于本实施例中，该半导体组件51与该第三封装胶体57可视为一上方半导体封装件5a。
此外，于其它实施例中，也可依第三实施例的工艺进行再堆栈工艺；或者，将该第二半导体封装件58直接电性接置于该封装堆栈结构2上，而不形成该半导体组件51与该第三封装胶体57。
再者，本发明的封装堆栈结构5的制法，可利用第一或第三实施例的工艺交替搭配使用，并无限制仅能单一堆栈方式重复使用。因此，借由固化温度与压力极低的工艺优势，当所需的堆栈层数超过两层时，该封装堆栈结构5仍不会产生翘曲，也就是更能突显本发明的优点。
另外，第二实施例也可进行上述的后续工艺。
综上所述，本发明的封装堆栈结构的制法，不仅克服现有技术的缺点，且工艺步骤简化、工艺时间缩短及成本更低。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种封装堆栈结构的制法，其包括：
提供一其上设有至少一半导体组件的基板，且该基板具有多个第一电性接触垫；
提供一下表面形成有封装胶体的半导体封装件，该半导体封装件下表面具有多个第二电性接触垫及至少一挡块，其中该挡块限制形成该封装胶体的范围，该挡块的材质为半固化形态的胶；以及
将该半导体封装件以导电组件结合于该基板上，以令该半导体组件位于该基板与该半导体封装件之间，且该封装胶体位于该基板与该半导体封装件之间以包覆该半导体组件，并使该半导体封装件接触该封装胶体，且该挡块会融入该封装胶体中而成为一体。
2.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该第一电性接触垫电性连接该第二电性接触垫。
3.根据权利要求1或2所述的封装堆栈结构的制法，其特征在于，该第一电性接触垫与第二电性接触垫之间借由该导电组件电性连接。
4.根据权利要求3所述的封装堆栈结构的制法，其特征在于，该导电组件包含焊锡材料及铜材。
5.根据权利要求2所述的封装堆栈结构的制法，其特征在于，该第一电性接触垫具有凹部。
6.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该半导体组件为堆栈芯片组或单一芯片。
7.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该半导体组件以打线方式或覆晶方式电性结合于该基板。
8.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该封装胶体还形成于该基板上。
9.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该半导体封装件上具有电子组件，且该封装胶体还包覆该电子组件。
10.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该导电组件为导电凸块、导电柱或导电球。
11.根据权利要求1所述的封装堆栈结构的制法，其特征在于，该制法还包括于该封装胶体包覆该半导体组件后，形成另一半导体封装件于该半导体封装件上。
CN201210401126.0A 2012-10-09 2012-10-19 封装堆栈结构的制法 Active CN103715107B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101137228 2012-10-09
TW101137228A TW201415602A (zh) 2012-10-09 2012-10-09 封裝堆疊結構之製法

Publications (2)

Publication Number Publication Date
CN103715107A CN103715107A (zh) 2014-04-09
CN103715107B true CN103715107B (zh) 2017-04-19

Family

ID=50407979

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210401126.0A Active CN103715107B (zh) 2012-10-09 2012-10-19 封装堆栈结构的制法

Country Status (3)

Country Link
US (1) US20140099755A1 (zh)
CN (1) CN103715107B (zh)
TW (1) TW201415602A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478498B2 (en) 2013-08-05 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Through package via (TPV)
CN105328969B (zh) * 2014-08-11 2018-01-09 上海和辉光电有限公司 一种封装基板制造方法及封装基板
US9406629B2 (en) * 2014-10-15 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499630A (zh) * 2002-11-04 2004-05-26 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN101071779A (zh) * 2006-05-08 2007-11-14 矽品精密工业股份有限公司 半导体封装件堆栈结构及其制法
KR20080086178A (ko) * 2007-03-22 2008-09-25 (주)아이셀론 스택 패키지 제조 방법
CN102222653A (zh) * 2010-04-15 2011-10-19 财团法人工业技术研究院 微凸块结构
CN102637678A (zh) * 2011-02-15 2012-08-15 欣兴电子股份有限公司 封装堆栈装置及其制法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590292B1 (en) * 2001-06-01 2003-07-08 Lsi Logic Corporation Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill
US8404518B2 (en) * 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8460968B2 (en) * 2010-09-17 2013-06-11 Stats Chippac Ltd. Integrated circuit packaging system with post and method of manufacture thereof
US8546932B1 (en) * 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499630A (zh) * 2002-11-04 2004-05-26 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN101071779A (zh) * 2006-05-08 2007-11-14 矽品精密工业股份有限公司 半导体封装件堆栈结构及其制法
KR20080086178A (ko) * 2007-03-22 2008-09-25 (주)아이셀론 스택 패키지 제조 방법
CN102222653A (zh) * 2010-04-15 2011-10-19 财团法人工业技术研究院 微凸块结构
CN102637678A (zh) * 2011-02-15 2012-08-15 欣兴电子股份有限公司 封装堆栈装置及其制法

Also Published As

Publication number Publication date
US20140099755A1 (en) 2014-04-10
TW201415602A (zh) 2014-04-16
CN103715107A (zh) 2014-04-09

Similar Documents

Publication Publication Date Title
CN104576557B (zh) 包括插入件开口的半导体封装件装置
KR101711499B1 (ko) 반도체 패키지 및 그 제조 방법
CN102760715A (zh) 嵌埋电子组件的封装结构及其制法
CN107785344A (zh) 电子封装件及其制法
KR20130082298A (ko) 패키지 온 패키지 장치의 제조 방법 및 이에 의해 제조된 장치
CN105304584B (zh) 中介基板及其制造方法
CN105428341A (zh) 半导体装置以及半导体装置的制造方法
CN108962840A (zh) 电子封装件及其制法
CN105489565B (zh) 嵌埋元件的封装结构及其制法
CN104037142B (zh) 封装对准结构及其形成方法
CN103715107B (zh) 封装堆栈结构的制法
CN111293092A (zh) 一种集成多种塑封技术的超微小化sip封装产品及封装工艺
CN104078372A (zh) 半导体装置的制造方法
CN105304583B (zh) 封装结构的制法
CN106449560A (zh) 芯片封装结构
CN103050466B (zh) 半导体封装件及其制法
KR102235489B1 (ko) 인쇄 회로 기판 및 이를 이용한 반도체 패키지
CN101853835A (zh) 倒装芯片封装及其制造方法
CN104124212B (zh) 半导体封装件及其制法
CN103137581B (zh) 具有导电凸块的半导体装置、封装结构及制法
CN101447471B (zh) 用于半导体封装的基板及使用该基板的半导体封装
CN104779175A (zh) 半导体封装件及其制法
CN104681499B (zh) 封装堆栈结构及其制法
CN104183555B (zh) 半导体封装件及其制法
KR20130073714A (ko) 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant