CN103681813B - 一种背沟槽结构绝缘栅双极晶体管及其制备方法 - Google Patents
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Abstract
本发明公开了一种背沟槽结构绝缘栅双极晶体管,传统绝缘栅双极晶体管的背P+发射区完全覆盖器件背面,本发明的绝缘栅双极晶体管通过沟槽将器件背面部分或全部区域设置为多晶P+发射区,以此调节背P+发射区向N型基区注入空穴的效率,提高器件高频特性的应用范围。本发明还提供了一种背沟槽结构绝缘栅双极晶体管的制备方法。
Description
技术领域
本发明涉及到一种背沟槽结构绝缘栅双极晶体管,本发明还涉及一种背沟槽结构绝缘栅双极晶体管的制备方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,简称IGBT)是一种集金属氧化物半导体场效应管(MOSFET)的栅电极电压控制特性和双极晶体管(BJT)的低导通电阻特性于一身的半导体功率器件,具有电压控制、输入阻抗大、驱动功率小、导通电阻小、开关损耗低及工作频率高等特性,是比较理想的半导体功率开关器件,有着广阔的发展和应用前景。
一般说来,从IGBT的正面结构区分,可以把IGBT分为平面型和沟槽栅型两种结构;从IGBT击穿特性区分,可以分为穿通型和非穿通型两种结构,穿通型在器件背面P+表面具有N+缓冲层,其通态压降比非穿通型要小,同时穿通型器件也增加了器件的制造难度。
发明内容
本发明提供一种背沟槽绝缘栅双极晶体管及其制备方法。
一种背沟槽结构绝缘栅双极晶体管,其特征在于:包括:N型基区,由N+缓冲层和N-基区叠加组成;P型基区、N+源区、栅氧化层和栅极介质,位于N型基区上方;背沟槽多晶P+发射区,为多个沟槽结构,位于N型基区下方,P型多晶半导体材料临靠沟槽内壁,同时背沟槽内填充电极金属。
一种背沟槽绝缘栅双极晶体管的制备方法,其特征在于:包括如下步骤:对N型片进行双面N型杂质扩散;通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层:在上表面形成P型基区、N+源区、栅氧化层和栅极介质;在下表面通过掩膜刻蚀形成沟槽,淀积形成P型多晶半导体材料。
传统绝缘栅双极晶体管的背P+发射区完全覆盖器件背面,本发明的绝缘栅双极晶体管通过沟槽将器件背面部分或全部区域设置为多晶P+发射区,以此调节背P+发射区向N型基区注入空穴的效率,提高器件高频特性的应用范围。
附图说明
图1为本发明的一种背沟槽结构绝缘栅双极晶体管剖面示意图;
图2为本发明的第二种背沟槽结构绝缘栅双极晶体管剖面示意图;
图3为本发明的第三种背沟槽结构绝缘栅双极晶体管剖面示意图;
图4为本发明的第四种背沟槽结构绝缘栅双极晶体管剖面示意图;
图5为本发明的第五种背沟槽结构绝缘栅双极晶体管剖面示意图;
图6为本发明的第六种背沟槽结构绝缘栅双极晶体管剖面示意图。
其中,1、背沟槽多晶P+发射区;2、N+缓冲层;3、N-基区;4、P型基区;5、N+源区;6、栅氧化层;7、栅极介质;10、背面氧化层。
具体实施方式
实施例1
图1为本发明的一种背沟槽结构绝缘栅双极晶体管的剖面图,下面结合图1详细说明本发明的半导体装置。
一种绝缘栅双极晶体管,包括:N+缓冲层2,为N传导类型的半导体硅材料,磷原子掺杂浓度为5E13cm-3~5E16cm-3,厚度为30um;背沟槽多晶P+发射区1,为P传导类型多晶半导体硅材料,分布背面沟槽内壁和N+缓冲层2表面,沟槽宽度和间距为5um,沟槽深度为50um,硼原子表面掺杂浓度为5E17cm-3;N-基区3,位于N+缓冲层2之上,为N传导类型的半导体硅材料,厚度为200um,磷原子掺杂浓度为5E13cm-3;P型基区4,位于N-基区3之上,为硼原子重掺杂的半导体硅材料,厚度为5um;N+源区5,位于P型基区4之上,为磷原子重掺杂的半导体硅材料,厚度为2um;栅氧化层6,为硅材料的氧化物,位于器件表面;栅极介质7,位于栅氧化层6表面,为重掺杂的多晶半导体硅材料。
本实施例的工艺制造流程如下:
第一步,对N型硅片进行双面磷杂质扩散;
第二步,通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层,形成N+缓冲层2和N-基区3:
第三步,在上表面形成P型基区4、N+源区5、栅氧化层6和栅极介质7;
第四步,在下表面光刻腐蚀形成胶掩膜,刻蚀形成沟槽,淀积P型多晶半导体材料,如图1所示。
然后在此基础上,淀积金属铝,然后光刻腐蚀进行反刻铝,为器件引出N+源区电极和栅电极,通过背面金属化工艺为器件引出背沟槽多晶P+发射区电极。同时图1实施例中表面栅氧化层6和栅极介质7也可以为沟槽结构,如图2所示。
实施例2
图3为本发明的第三种背沟槽结构绝缘栅双极晶体管的剖面图,下面结合图3详细说明本发明的半导体装置。
一种绝缘栅双极晶体管,包括:N+缓冲层2,为N传导类型的半导体硅材料,磷原子掺杂浓度为5E13cm-3~5E16cm-3,厚度为30um;背沟槽多晶P+发射区1,为P传导类型多晶半导体硅材料,分布背面沟槽内壁和N+缓冲层2表面,沟槽宽度和间距为5um,沟槽深度为50um,硼原子表面掺杂浓度为5E17cm-3;N-基区3,位于N+缓冲层2之上,为N传导类型的半导体硅材料,厚度为200um,磷原子掺杂浓度为5E13cm-3;P型基区4,位于N-基区3之上,为硼原子重掺杂的半导体硅材料,厚度为5um;N+源区5,位于P型基区4之上,为磷原子重掺杂的半导体硅材料,厚度为2um;栅氧化层6,为硅材料的氧化物,位于器件表面;栅极介质7,位于栅氧化层6表面,为重掺杂的多晶半导体硅材料;背面氧化层10,位于N+缓冲层2表面。
本实施例的工艺制造流程如下:
第一步,对N型硅片进行双面磷杂质扩散;
第二步,通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层,形成N+缓冲层2和N-基区3:
第三步,在上表面形成P型基区4、N+源区5、栅氧化层6和栅极介质7;
第四步,在下表面光刻腐蚀形成氧化层掩膜,刻蚀形成沟槽,淀积P型多晶半导体材料,如图3所示。
然后在此基础上,淀积金属铝,然后光刻腐蚀进行反刻铝,为器件引出N+源区电极和栅电极,通过背面金属化工艺为器件引出背沟槽多晶P+发射区电极。同时图3实施例中表面栅氧化层6和栅极介质7也可以为沟槽结构,如图4所示。
实施例3
图5为本发明的第五种背沟槽结构绝缘栅双极晶体管的剖面图,下面结合图5详细说明本发明的半导体装置。
一种绝缘栅双极晶体管,包括:N+缓冲层2,为N传导类型的半导体硅材料,磷原子掺杂浓度为5E13cm-3~5E16cm-3,厚度为30um;背沟槽多晶P+发射区1,为P传导类型多晶半导体硅材料,分布沟槽内壁,沟槽宽度和间距为5um,沟槽深度为5um,硼原子表面掺杂浓度为5E17cm-3;N-基区3,位于N+缓冲层2之上,为N传导类型的半导体硅材料,厚度为200um,磷原子掺杂浓度为5E13cm-3;P型基区4,位于N-基区3之上,为硼原子重掺杂的半导体硅材料,厚度为5um;N+源区5,位于P型基区4之上,为磷原子重掺杂的半导体硅材料,厚度为2um;栅氧化层6,为硅材料的氧化物,位于器件表面;栅极介质7,位于栅氧化层6表面,为重掺杂的多晶半导体硅材料。
本实施例的工艺制造流程如下:
第一步,对N型硅片进行双面磷杂质扩散;
第二步,通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层,形成N+缓冲层2和N-基区3:
第三步,在上表面形成P型基区4、N+源区5、栅氧化层6和栅极介质7;
第四步,在下表面光刻腐蚀形成胶掩膜,刻蚀形成沟槽,淀积P型多晶半导体材料,进行背面减薄,如图5所示。
然后在此基础上,淀积金属铝,然后光刻腐蚀进行反刻铝,为器件引出N+源区电极和栅电极,通过背面金属化工艺为器件引出背沟槽多晶P+发射区电极。同时图5实施例中表面栅氧化层6和栅极介质7也可以为沟槽结构,如图6所示。
通过上述实例阐述了本发明,同时也可以采用其它实例实现本发明,本发明不局限于上述具体实例,因此本发明由所附权利要求范围限定。
Claims (2)
1.一种背沟槽结构绝缘栅双极晶体管的制备方法,其特征在于:依次包括如下步骤:
1)对N型片进行双面N型杂质扩散;
2)通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层:
3)在N型片上表面形成P型基区、N+源区、栅氧化层和栅极介质;
4)在N型片下表面通过掩膜刻蚀形成背沟槽,在背沟槽内壁表面淀积形成P型多晶半导体材料。
2.一种如权利要求1制备方法所述的背沟槽结构绝缘栅双极晶体管,其特征在于:包括:
N型基区,由N+缓冲层和N-基区叠加组成,N-基区位于N+缓冲层上方;
P型基区、N+源区、栅氧化层和栅极介质,位于N型基区上方;
背沟槽多晶P+发射区,为多个背沟槽结构,背沟槽位于N型基区N+缓冲层内下方,整个P+发射区由P型多晶半导体材料构成,P型多晶半导体材料临靠背沟槽内壁,同时背沟槽内填充电极金属。
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JP2008140828A (ja) * | 2006-11-30 | 2008-06-19 | Rohm Co Ltd | 半導体装置およびその製造方法 |
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