CN103681810B - 一种绝缘栅双极晶体管 - Google Patents

一种绝缘栅双极晶体管 Download PDF

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CN103681810B
CN103681810B CN201210320208.2A CN201210320208A CN103681810B CN 103681810 B CN103681810 B CN 103681810B CN 201210320208 A CN201210320208 A CN 201210320208A CN 103681810 B CN103681810 B CN 103681810B
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bipolar transistor
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CN103681810A (zh
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朱江
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Qingdao Huike Microelectronics Co.,Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

本发明公开了一种绝缘栅双极晶体管，本发明的绝缘栅双极晶体管在N型基区表面设置有P型基区、N+源区、栅氧化层和栅极介质，在N型基区下表面设置了多晶P型半导体材料作为器件的背P+发射区；本发明的绝缘栅双极晶体管降低了器件的导通电阻，提高了器件的高频应用能力。本发明还提供了一种绝缘栅双极晶体管的制备方法。

Description

一种绝缘栅双极晶体管
技术领域
本发明涉及到一种绝缘栅双极晶体管，本发明还涉及一种绝缘栅双极晶体管的制备方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,简称IGBT)是一种集金属氧化物半导体场效应管(MOSFET)的栅电极电压控制特性和双极晶体管(BJT)的低导通电阻特性于一身的半导体功率器件，具有电压控制、输入阻抗大、驱动功率小、导通电阻小、开关损耗低及工作频率高等特性，是比较理想的半导体功率开关器件，有着广阔的发展和应用前景。
一般说来，从IGBT的正面结构区分，可以把IGBT分为平面型和沟槽栅型两种结构；从IGBT击穿特性区分，可以分为穿通型和非穿通型两种结构，穿通型在器件背面P+表面具有N+缓冲层，其通态压降比非穿通型要小，同时穿通型器件也增加了器件的制造难度。
发明内容
本发明提供一种绝缘栅双极晶体管及其制备方法。
一种绝缘栅双极晶体管，其特征在于：包括：N型基区，由N+缓冲层和N-基区叠加组成；P型基区、N+源区、栅氧化层和栅极介质，位于N型基区上方；背P+发射区，为多晶P型半导体材料，位于N型基区的N+缓冲层下方。
一种绝缘栅双极晶体管的制备方法，其特征在于：包括如下步骤：对N型片进行双面N型杂质扩散；通过减薄抛光去除上表面N型杂质扩散层和部分去除下表面N型杂质扩散层：在上表面形成P型基区、N+源区、栅氧化层和栅极介质；在下表面淀积多晶P型半导体材料，形成背P+发射区。
传统绝缘栅双极晶体管的背P+发射区通过注入退火形成，本发明的绝缘栅双极晶体管将多晶P型半导体材料设置为器件的背P+发射区，降低了器件的导通电阻，提高了器件高频应用的范围。
附图说明
图1为本发明的一种绝缘栅双极晶体管的剖面示意图；
图2为本发明的第二种绝缘栅双极晶体管的剖面示意图。
其中，1、背P+发射区；2、N+缓冲层；3、N-基区；4、P型基区；5、N+源区；6、栅氧化层；7、栅极介质。
具体实施方式
实施例1
图1为本发明的一种绝缘栅双极晶体管的剖面图，下面结合图1详细说明本发明的半导体装置。
一种绝缘栅双极晶体管，包括：背P+发射区1，为P传导类型多晶半导体硅材料，厚度为0.2um，硼原子表面掺杂浓度为5E17cm-3；N+缓冲层2，位于背P+发射区1之上，为N传导类型的半导体硅材料，磷原子掺杂浓度为5E13cm-3～1E16cm-3，厚度为30um；N-基区3，位于N+缓冲层2之上，为N传导类型的半导体硅材料，厚度为200um，磷原子掺杂浓度为5E13cm-3；P型基区4，位于N-基区3之上，为硼原子重掺杂的半导体硅材料，厚度为5um；N+源区5，位于P型基区4之上，为磷原子重掺杂的半导体硅材料，厚度为2um；栅氧化层6，为硅材料的氧化物，位于器件表面；栅极介质7，位于栅氧化层6表面，为重掺杂的多晶半导体硅材料。
本实施例的工艺制造流程如下：
第一步，对N型硅片进行双面磷杂质扩散；
第二步，通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层，形成N+缓冲层2和N-基区3：
第三步，在上表面形成P型基区4、N+源区5、栅氧化层6和栅极介质7；
第四步，在下表面淀积形成P型多晶半导体材料，形成背P+发射区1，如图1所示。
然后在此基础上，淀积金属铝，然后光刻腐蚀进行反刻铝，为器件引出N+源区电极和栅电极，通过背面金属化工艺为器件引出背P+发射区电极。
实施例2
图2为本发明的第二种绝缘栅双极晶体管的剖面图，下面结合图2详细说明本发明的半导体装置。
一种绝缘栅双极晶体管，包括：背P+发射区1，为P传导类型多晶半导体硅材料，厚度为0.2um，硼原子表面掺杂浓度为5E17cm-3；N+缓冲层2，位于背P+发射区1之上，为N传导类型的半导体硅材料，磷原子掺杂浓度为5E13cm-3～1E16cm-3，厚度为30um；N-基区3，位于N+缓冲层2之上，为N传导类型的半导体硅材料，厚度为200um，磷原子掺杂浓度为5E13cm-3；P型基区4，位于N-基区3之上，为硼原子重掺杂的半导体硅材料，厚度为5um；N+源区5，位于P型基区4之上，为磷原子重掺杂的半导体硅材料，厚度为2um；栅氧化层6，为硅材料的氧化物，位于器件沟槽内；栅极介质7，位于沟槽内栅氧化层6表面，为重掺杂的多晶半导体硅材料。
本实施例的工艺制造流程如下：
第一步，对N型硅片进行双面磷杂质扩散；
第二步，通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层，形成N+缓冲层2和N-基区3：
第三步，在上表面形成P型基区4、N+源区5、沟槽结构栅氧化层6和沟槽结构栅极介质7；
第四步，在下表面淀积形成P型多晶半导体材料，形成背P+发射区1，如图2所示。
然后在此基础上，淀积金属铝，然后光刻腐蚀进行反刻铝，为器件引出N+源区电极和栅电极，通过背面金属化工艺为器件引出背P+发射区电极。
通过上述实例阐述了本发明，同时也可以采用其它实例实现本发明，本发明不局限于上述具体实例，因此本发明由所附权利要求范围限定。

Claims (1)

1.一种绝缘栅双极晶体管，其特征在于：包括：
N型基区，由N+缓冲层和N-基区叠加组成，N-基区位于N+缓冲层上方，为N型半导体材料；
P型基区、N+源区、栅氧化层和栅极介质，位于N型基区上方；
背P+发射区，完全为多晶P型半导体材料构成，位于N+缓冲层的下方，背P+发射区为在上表面形成P型基区、N+源区、栅氧化层和栅极介质后，在N+缓冲层下表面形成多晶P型半导体材料，背P+发射区背部设置金属，形成背P+发射区电极。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0746040A1 (en) * 1995-05-31 1996-12-04 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Improved IGBT device
US6221721B1 (en) * 1996-02-12 2001-04-24 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing an insulated trench gate semiconductor device
CN101976683A (zh) * 2010-09-25 2011-02-16 浙江大学 一种绝缘栅双极型晶体管及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07107935B2 (ja) * 1988-02-04 1995-11-15 株式会社東芝 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0746040A1 (en) * 1995-05-31 1996-12-04 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Improved IGBT device
US6221721B1 (en) * 1996-02-12 2001-04-24 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing an insulated trench gate semiconductor device
CN101976683A (zh) * 2010-09-25 2011-02-16 浙江大学 一种绝缘栅双极型晶体管及其制造方法

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