CN103650133B - Qfn封装的晶圆级处理技术 - Google Patents

Qfn封装的晶圆级处理技术 Download PDF

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CN103650133B
CN103650133B CN201280002459.4A CN201280002459A CN103650133B CN 103650133 B CN103650133 B CN 103650133B CN 201280002459 A CN201280002459 A CN 201280002459A CN 103650133 B CN103650133 B CN 103650133B
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column
wafer
photoresist layer
chip
packaging structure
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CN103650133A (zh
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V·卡恩德卡尔
K·坦比杜赖
A·阿什拉夫扎德
A·科尔卡
H·D·阮
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Abstract

本发明描述了例如晶圆级封装半导体器件的半导体封装器件，其具有用于提供电气的相互连接性的柱。在实施方式中，晶圆级封装器件包括集成电路芯片，其具有至少一个形成于集成电路芯片上的柱。柱配置成提供与集成电路芯片电气的相互连接性。晶圆级封装器件还包括配置成支撑该柱的包装结构。

Description

QFN封装的晶圆级处理技术
背景技术
例如四边扁平无引线(QFN)封装技术的扁平无引线封装技术，物理地与电气地将集成电路芯片连接至印刷电路板。扁平无引线封装技术典型地使用引线框架，该引线框架包括安装于其上的集成电路芯片(晶片)。该晶片可以通过线接合技术或倒装芯片技术与引线框架相互电连接。随后在引线框架上形成包装结构，以封装集成电路芯片。
发明内容
描述了用于制造晶圆级封装半导体器件的技术，其具有相似于使用扁平无引线(例如，QFN)封装技术器件的形状因数的形状因数。在一个或多个实施方式中，晶圆级封装器件包括集成电路芯片(例如，晶片)，其具有形成于集成电路芯片上的至少一个柱(例如，铜柱)。柱配置成向集成电路芯片提供相互电连接。配置成支撑该柱的包装结构形成于集成电路芯片的表面上。在一个或多个实施方式中，第二集成电路器件可以被安装至集成电路芯片，从而集成电路器件与集成电路芯片电连通。第二集成电路器件至少部分地由包装结构包装。
提供上述概述，以介绍简化形式的概念的选择，其在下面详细说明中将作进一步的描述。该概述并不旨在确定要求保护的主题的关键特征或基本特征，也并不旨在用作辅助确定要求保护的主题的范围。
附图说明
参照附图描述详细的说明。在说明书与附图的不同实施例中使用相同的附图标记可以表示相似或相同的项目。
图1为示例了根据本公开的示例性实施方式的晶圆级封装器件的透视图。
图2A为沿平面2A-2A的图1中所示的晶圆级封装器件部分的局部截面侧视图。
图2B为沿平面2B-2B的图1中所示的晶圆级封装器件部分的局部截面侧视图，其中，晶圆级封装器件包括集成电路器件。
图3为示例了用于制造例如图1至2A中所示的器件的晶圆级封装器件的示例性实施方式中的过程的流程图。
图4A至4I为示例了根据图3中所示的过程，例如在图1与2A中所示的器件的晶圆级封装器件的制造的局部截面侧视图。
具体实施方式
综述
使用例如QFN封装技术的扁平无引线封装技术的器件通过将集成电路芯片完全装在封装中，而向包含在器件包装中的集成电路芯片(晶片)提供良好的机械保护。然而，扁平无引线(例如，QFN)封装器件生产非常昂贵，并且典型地提供相对低的引脚数量(例如，QFN的引脚典型地沿晶片边缘定位)。
晶圆级封装为包含多种技术的芯片级封装技术，由此，在分割之前集成电路芯片以晶圆级被封装。晶圆级封装扩展晶圆制造过程，以包括器件相互连接与器件保护过程。因此，晶圆级封装通过允许以晶圆级集成晶圆制造、封装、测试、以及烧入过程而使得加工过程流水线化。与扁平无引线(QFN)封装技术相比，晶圆级封装通常更便宜地实现，因为封装以晶圆级发生，而扁平无引线封装以带级(strip level)进行。而且，可比较的晶圆级封装器件的占用空间典型地少于QFN封装器件的占用空间，因为晶圆级封装可以几乎等于集成电路芯片的尺寸。
因此，描述了使用晶圆级封装技术来制造半导体器件的技术，该半导体器件具有相似于使用扁平无引线(QFN)封装技术的那些器件的形状因数。晶圆级封装器件因此可以提供包含在相似于由扁平无引线(QFN)器件提供的器件封装中的集成电路芯片(晶片)的机械保护，同时保持晶圆级封装的固有益处(例如，低成本、小封装尺寸、高引脚数量等)。晶圆级封装器件包括集成电路芯片(例如，晶片)，其具有向器件提供电相互连接的柱。在具体实施中，柱可以是铜柱，其具有形成于柱的暴露端上的焊料层(solder layer)。配置成支撑该柱的包装结构以晶圆级形成于集成电路芯片的表面上。在实施例中，包装结构可以由环氧树脂或相似物质制造。在一个或多个实施方式中，第二集成电路器件可以被安装至集成电路芯片，以使得集成电路器件与集成电路芯片电连通。第二集成电路器件至少局部地由包装结构包装。一旦从晶圆分离，则器件可以安装至印刷电路板，并且柱通过与印刷电路板的焊点相连接的器件的背部提供相互电连接。
示例性实施方式
图1至2B示例了根据本公开的示例性实施方式的半导体封装器件100。在一些实施方式中，半导体封装器件100可以包括晶圆级集成电路封装器件。如图所示，器件100包括集成电路芯片102，该集成电路芯片102由具有一个或多个形成于其中的集成电路106的半导体基板104组成。在各种实施方式中，集成电路106可以包括数字集成电路、模拟集成电路、混合信号集成电路、其组合等。集成电路106可以通过合适的前段工艺过程(FEOL)制造技术来形成。
器件100进一步包括从半导体基板104的表面111延伸的柱108。在实施方式中，柱108为经由合适的加工过程，例如此处描述的双叠层/沉积过程来制造的铜柱。柱108可以具有从大约1比1(1∶1)至大约20比1(20∶1)范围的高宽比(aspect ratio)(柱的宽度与柱的高度的比例)。在特定的示例中，高宽比可以在大约5比1(5∶1)至大约15比1(15∶1)的范围。柱108用于提供集成电路芯片102与印刷电路板之间的相互电连接，印刷电路板配置成接受器件100。如图2A与2B中所示，柱108包括布置于暴露的端部112上的焊料层110(例如，从基板104的远端)，以用作器件100(例如，柱108)与布置于印刷电路板上的相应焊点之间的连接。在实施方式中，焊料层110可以由无铅焊料成分制造，例如锡-银-铜(Sn-Ag-Cu)合金焊料(即，SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等。
在某些实施方式中，器件100可以包括布置于(并且安装至)集成电路芯片102的表面111的第二集成电路器件114(例如，集成电路封装器件)。在实施例中，第二集成电路器件114可以与集成电路芯片102的集成电路106相电连通。例如，如图2B中所示，集成电路器件114包括焊料块116，其允许器件114与器件100相电接触。焊料块116例如可以定位于晶圆级芯片尺寸器件100的再分配结构(例如再分配层(RDL)118)上，以允许器件114与器件100之间的电连接(例如，集成电路106等)。RDL118可以由例如多晶硅、铝、铜等导电材料形成。因此，集成电路器件114通过能够有系统化封装的能力而扩展了器件100的额外功能。在实施方式中，集成电路器件114可以是数字集成电路器件、模拟集成电路器件、混合信号集成电路器件等。如上述的焊料层110，焊料块116可以由例如锡-银-铜(Sn-Ag-Cu)合金焊料(即，SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等的无铅焊料成分制造。然而，预期的是，可以使用锡-铅(PbSn)焊料成分。
器件100还包括布置于集成电路芯片102的表面111上的包装结构120。如图2A与2B所示，包装结构120至少基本上包装柱108。因此，包装结构120提供对柱108的支撑与绝缘(以及当器件100使用集成电路器件114时提供对集成电路器件114的支撑与绝缘)。柱108具有至少基本上延伸至包装结构120的深度的长度。如图1至2B所示，焊料层110延伸超过由包装结构120的表面122限定的平面，以允许焊料层110连接至印刷电路板的相应焊点。在实施方式中，包装结构120可以是沉积在晶圆级芯片尺寸封装器件100的表面111上的聚合物材料，例如环氧树脂等。
制造过程示例
图3示出了示例过程200，其使用晶圆级封装技术来制造具有柱的半导体器件，例如图1与2A中所示的器件100。在示例的过程200中，一个或多个柱最初形成于半导体晶圆上。如此处所述，可以使用双叠层/沉积过程来形成柱。因此，在将晶圆分割为单个电路芯片(晶片)之前第一光刻胶层形成于半导体晶圆上(方框202)。图4A示例了晶圆300的一部分，当通过合适的FEOL制造技术加工时，该部分包括半导体基板302，该半导体基板302包括集成电路芯片304。集成电路芯片304包括一个或多个形成于其中的集成电路306。基板302可以包括形成于基板302的表面310上的再分配结构，例如再分配层(RDL)308。如图所示，介电层312还可以形成于基板302的表面310上。介电层312可以是苯并环丁烯聚合物(BCB)、二氧化硅(SiO2)等。第一叠层步骤包括在晶圆300上(例如，在RDL308与介电层312上)应用第一光刻胶层314。第一光刻胶层314可以是光聚合物与聚酯膜的合成物，其可以通过一个或多个合适的干膜叠层过程形成图案并且蚀刻。
随后第一光刻胶层被形成图案并且蚀刻，以形成第一蚀刻区域(方框204)。图4B示例了第一光刻胶层314，其示出被形成图案并且蚀刻，以形成第一蚀刻区域316。蚀刻区域316至少穿过第一光刻胶层314延伸至RDL层308的焊点。
随后将导电材料沉积于第一蚀刻区域中(方框206)。图4C示例了沉积于晶圆300的蚀刻区域316中的导电材料318。在一个或多个实施方式中，可以使用合适的电镀过程，以在光刻胶层314的蚀刻区域316中沉积导电材料318。导电材料318可以包括铜、铝等导电材料或其他导电材料。
随后将第二光刻胶层应用于剩余的第一光刻胶层(方框208)与导电材料上。图4D示例了沉积于剩余的第一光刻胶层314与导电材料318上的第二光刻胶层320。一旦沉积，则第二光刻胶层被形成图案并且蚀刻，以形成第二蚀刻区域(方框210)。图4E示例了第二光刻胶层320，其中，第二光刻胶层320已经被形成图案并且蚀刻，以形成一个或多个第二蚀刻区域322，该第二蚀刻区域322定位于之前蚀刻的区域(例如，第一蚀刻区域316)。蚀刻区域322延伸第二光刻胶层320的深度，以使得导电材料318至少局部地暴露。
随后将导电材料沉积于第二蚀刻区域中，以完成一个或多个柱的形成(方框212)。图4F示例了沉积于蚀刻区域322中以形成柱324的导电材料318。如图所示，沉积于蚀刻区域322中的导电材料318至少局部地与沉积于蚀刻区域316中的导电材料318相接触。在一个或多个实施方式中，导电材料318(例如铜等)被电镀在蚀刻区域322中，以形成柱324(例如铜柱)。
一旦柱已经被形成，则除去光刻胶层(方框214)。图4C示例了通过合适的剥离过程除去第一与第二光刻胶层314与320(参见图4F)。此外，柱324可以经受合适的籽蚀刻(seedetch)过程。如上所述，集成电路芯片器件(图2B中所示)可以定位于基板302上。集成电路芯片器件能够将系统化封装能力扩展至集成电路芯片304。
一旦形成柱，则包装结构形成于晶圆上，以至少基本上包装柱(方框216)。图4H示例了形成于晶圆300的表面310上的包装结构326，以向集成电路306与柱324提供支撑与绝缘。在实施例中，多个聚合物层(例如环氧树脂等)可以沉积于表面310上，以形成包装结构326。期望的是，环氧树脂材料还可以沉积于晶圆300的背部上(例如，在表面328上)。一旦形成，则包装结构326可以经受磨削过程，以暴露柱324(例如，暴露柱324的远离基板302的端部)。如图所示，包装结构326至少基本上延伸柱324的长度(例如，深度或高度)。如图4H中所示，在实施方式中，第一柱324穿过至少基本上整个包装结构326延伸(例如，至少基本上延伸包装结构326的高度，第一柱324的高度与包装结构326的高度相同)，并且第二柱324仅局部穿过包装结构326延伸。例如，第二柱324可以仅穿过包装结构326的一半延伸(例如，第二柱324的高度为至少大约包装结构326的高度的一半)。然而，应该理解的是，可以根据晶圆级半导体封装器件的要求使用其他柱高度。
随后将焊料层应用于柱(方框218)。例如，焊料层330(例如，焊料光洁处理)可以被形成于(例如，应用于)柱324的暴露端332上(例如，柱324的远离晶圆300的端部)。在实施方式中，晶圆300可以经受合适的浸焊过程，以在暴露的铜柱引线上应用焊料层330。一旦完成浸焊过程，则可以使用合适的过程，以将单个集成电路芯片304分割为单个封装。
结论
尽管针对结构特征和/或过程操作描述了主题内容，但应该理解的是，在所附权利要求中限定的主题内容并不必须限制于上述具体特征或行为。相反，上述具体特征与行为作为实施权利要求的示例形式而被公开。

Claims (17)

1.一种制造半导体器件的过程，包括：
在半导体晶圆上应用第一光刻胶层；
在所述第一光刻胶层上应用第二光刻胶层；
在所述半导体晶圆上形成至少一个柱，所述至少一个柱包括多个柱，该多个柱中的第一柱延伸穿过所述第一光刻胶层和所述第二光刻胶层，并且该多个柱中的第二柱仅延伸穿过所述第一光刻胶层；
在所述半导体晶圆上形成包装结构，所述包装结构至少包装所述至少一个柱；以及
将焊料层应用于所述至少一个柱。
2.根据权利要求1所述的过程，其中，形成至少一个柱进一步包括：
使所述第一光刻胶层形成图案并且至少局部地蚀刻所述第一光刻胶层，以形成第一蚀刻区域；
在所述第一蚀刻区域中沉积导电材料；
使所述第二光刻胶层形成图案并且至少局部地蚀刻所述第二光刻胶层，以形成第二蚀刻区域，所述第二蚀刻区域形成于所述第一蚀刻区域上；
在所述第二蚀刻区域中沉积导电材料，以形成所述至少一个柱；并且
至少除去所述第一光刻胶层和所述第二光刻胶层。
3.根据权利要求1所述的过程，其中，形成包装层进一步包括在所述半导体晶圆上沉积环氧树脂材料，所述包装层至少局部地包装所述至少一个柱。
4.根据权利要求1所述的过程，其中，所述至少一个柱包括铜柱。
5.根据权利要求1所述的过程，其中，所述至少一个柱的高宽比在从1比1（1:1）至20比1（20:1）的范围。
6.根据权利要求1所述的过程，其中，所述至少一个柱的高宽比在从5比1（5:1）至15比1（15:1）的范围。
7.根据权利要求1所述的过程，其中，应用所述焊料层包括将所述焊料层应用于所述至少一个柱的暴露的部分。
8.一种晶圆级封装器件，包括：
具有表面的集成电路芯片；
从所述表面延伸的至少一个柱，所述至少一个柱具有远离所述表面的端部，所述至少一个柱配置成向所述集成电路芯片提供相互电连接；
布置于所述至少一个柱的端部上的焊料层；以及
布置于所述表面上的包装结构，所述包装结构至少局部地包围所述至少一个柱；
其中，所述至少一个柱包括从所述集成电路芯片的表面延伸的多个柱，所述多个柱中的第一柱延伸穿过所述包装结构，并且所述多个柱中的第二柱延伸穿过部分所述包装结构。
9.根据权利要求8所述的晶圆级封装器件，其中，所述至少一个柱包括铜柱。
10.根据权利要求8所述的晶圆级封装器件，其中，所述包装结构包括环氧树脂材料。
11.根据权利要求8所述的晶圆级封装器件，其中，所述至少一个柱的高宽比在从1比1（1:1）至20比1（20:1）的范围。
12.根据权利要求8所述的晶圆级封装器件，其中，所述至少一个柱的高宽比在从5比1（5:1）至15比1（15:1）的范围。
13.一种半导体器件，包括：
具有表面的集成电路芯片；
从所述表面延伸的至少一个柱，所述至少一个柱具有远离所述表面的端部，所述至少一个柱配置成向所述集成电路芯片提供相互电连接；
布置于所述至少一个柱的端部上的焊料层；
布置于所述表面上的集成电路封装器件；以及
布置于所述表面上的包装结构，所述包装结构至少局部地包围所述至少一个柱与所述集成电路封装器件；
其中，所述至少一个柱包括从所述集成电路芯片的表面延伸的多个柱，所述多个柱中的第一柱延伸穿过所述包装结构，并且所述多个柱中的第二柱延伸穿过部分所述包装结构。
14.根据权利要求13所述的半导体器件，其中，所述至少一个柱包括铜柱。
15.根据权利要求13所述的半导体器件，其中，所述包装结构包括环氧树脂材料。
16.根据权利要求13所述的半导体器件，其中，所述至少一个柱的高宽比在从1比1（1:1）至20比1（20:1）的范围。
17.根据权利要求13所述的半导体器件，其中，所述至少一个柱的高宽比在从5比1（5:1）至15比1（15:1）的范围。
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