CN103594418A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103594418A
CN103594418A CN201210334646.4A CN201210334646A CN103594418A CN 103594418 A CN103594418 A CN 103594418A CN 201210334646 A CN201210334646 A CN 201210334646A CN 103594418 A CN103594418 A CN 103594418A
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China
Prior art keywords
layer
hole
conductive
chip
semiconductor package
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CN201210334646.4A
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Inventor
刘鸿汶
许习彰
周信宏
廖信一
张江城
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103594418A publication Critical patent/CN103594418A/zh
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Abstract

一种半导体封装件及其制法，该方法包括将至少一芯片结合于承载件上的粘着层，并于该芯片的非作用面及粘着层上依序形成软质层和支撑层以使该芯片嵌埋于该软质层中，接着移除该承载板与粘着层以使该芯片的作用面外露于该软质层的第一表面，接着于该软质层中形成第一导电通孔，并于该芯片的作用面及软质层的第一表面上形成第一线路重布结构，于该支撑层中形成与该第一导电通孔导通的第二导电通孔，最后于该支撑层的第三表面上形成第二线路重布结构，以通过该第一及第二导电通孔与该第一线路重布结构电性连接。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种晶圆级半导体封装件及其制法。
背景技术
随着半导体技术的演进，半导体产品已开发出不同封装产品型态，而为追求半导体封装件的轻薄微型化，因而发展出一种芯片尺寸封装件(chip scale package,CSP)，其特征在于此种芯片尺寸封装件仅具有与芯片尺寸相等或略大的尺寸。
第5,892,179、6,103,552、6,287,893、6,350,668及6,433,427号美国专利即揭露一种传统的CSP结构，通过直接于芯片上形成增层，且利用重布线(redistribution layer,RDL)技术重配芯片上的焊垫至所欲位置。
然而上述CSP结构的缺点在于重布线技术的施用或布设于芯片上的导电迹线往往受限于芯片的尺寸或其作用面的面积大小，尤其当芯片的积集度提升且芯片尺寸日趋缩小的情况下，芯片甚至无法提供足够表面以安置更多数量的焊球来与外界电性连接。
鉴此，第6,271,469号美国专利揭露一种晶圆级芯片尺寸封装件WLCSP(Wafer Level Chip Scale Package)的制法，通过于芯片上形成增层的封装件，得提供较为充足的表面区域以承载较多的输入/输出端或焊球。
如图1A所示，首先将芯片102以作用面106粘贴于胶膜104上，接着利用如环氧树脂的封装胶体112包覆住该芯片102的非作用面114及侧面116，接着再加热移除该胶膜104，以外露出该芯片的作用面106及电极垫108；然后如图1B所示，利用重布线(RDL)技术，敷设一线路重布结构14于芯片102的作用面106及封装胶体112的表面上，再于线路重布结构14上敷设防焊层136及在预定位置植设焊球138。
于前述工艺中，因包覆芯片102的封装胶体112的表面能提供较芯片102作用面106大的表面区域，故可安置较多焊球138以有效达成与外界的电性连接。
然而，上揭工艺仅通过胶膜104支撑芯片102，容易导致胶膜104及封装胶体112发生翘曲，另外，将芯片102以作用面106粘贴于胶膜104上时，常因胶膜104于工艺中受热而发生伸缩问题，造成粘置于胶膜104上的芯片102位置发生偏移，甚至于封装模压时因胶膜104受热软化而造成芯片102位移，如此导致后续在重布线工艺时，无法连接到芯片102电极垫108上而造成电性不良。此外，利用上述工艺的半导体封装件无具有导电通孔，因而无法电性连接上下侧的线路重布结构，故未能提供其它封装件或电子组件接置。
因此，如何提供一种半导体封装件及制法，以能确保线路层与焊垫间的电性连接品质，并提升产品的可靠度，减少工艺成本，实为一重要课题。
发明内容
鉴于上述现有技术的缺陷，本发明的主要目的在于提供一种半导体封装件及其制法，能另提供其它封装件或电子组件接置。
本发明的半导体封装件的制法，包括以下步骤：提供一表面上形成有粘着层的承载板；将至少一具有相对的作用面及非作用面的芯片以其作用面结合于该粘着层上，其中，该芯片的作用面上具有多个电极垫；于该芯片的非作用面及粘着层上形成软质层，以使该芯片嵌埋于该软质层中，其中，该软质层具有相对的第一和第二表面，该第二表面上设有支撑层，以令该软质层夹置于该支撑层和粘着层之间，该支撑层具有相对于该第二表面的第三表面；移除该承载板与粘着层，以使该芯片的作用面外露于该软质层的第一表面；于该软质层中形成第一导电通孔；于该芯片的作用面及软质层的第一表面上形成第一线路重布结构，以使该第一线路重布结构与该第一导电通孔电性连接；于该支撑层中形成与该第一导电通孔导通的第二导电通孔；以及于该支撑层的第三表面上形成第二线路重布结构，以通过该第一及第二导电通孔与该第一线路重布结构电性连接。
前述的制法中，形成该第一线路重布结构的步骤复包括于该芯片的作用面及软质层的第一表面上形成第一介电层；于该第一介电层表面上形成第一线路层，且于该第一介电层中形成第一导电盲孔以电性连接该第一线路层、电极垫和第一导电通孔；以及于该第一介电层上形成外露部分该第一线路层的第一绝缘保护层。形成该第二线路重布结构的步骤复包括：于该支撑层的第三表面上形成第二介电层；于该第二介电层表面上形成第二线路层，且于该第二介电层中形成第二导电盲孔以电性连接该第二线路层和第二导电通孔；以及于该第二介电层上形成外露部分该第二线路层的第二绝缘保护层。前述的制法中，形成该第一导电通孔的步骤包括于该软质层中形成第一通孔，再于该第一通孔内形成第一导电通孔；形成该第二导电通孔的步骤包括于该支撑层中形成第二通孔，再于该第二通孔内形成第二导电通孔。
经前述制法，本发明的半导体封装件包括：软质层，其具有第一导电通孔及相对的第一表面及第二表面；至少一芯片，其嵌埋于该软质层内，该芯片具有相对的作用面、非作用面及多个形成于该芯片的作用面的电极垫，且该芯片的作用面外露于该软质层的第一表面；支撑层，其设于该软质层的第二表面上并具有第二导电通孔及相对于该第二表面的第三表面，且该第一导电通孔与第二导电通孔导通；第一线路重布结构，其设于该芯片的作用面及软质层的第一表面上并与该第一导电通孔和电极垫电性连接；以及第二线路重布结构，其设于该支撑层的第三表面上，并通过该第一及第二导电通孔与该第一线路重布结构电性连接。
于本发明的半导体封装件中，该支撑层的材料可为硅，则该第二导电通孔为穿透硅通孔。另外，该支撑层的材料可为玻璃，则该第二导电通孔为玻璃导通孔。此外，该软质层的材料可为Ajinomoto Build-upFilm(ABF)、聚酰亚胺或硅氧树脂。
相比于现有技术，本发明的半导体封装件及其制法，借由如硅或玻璃的支撑件来支撑嵌埋有芯片的软质层，以防止封装件翘曲的发生。再者，本发明的半导体封装件通过第一和第二导电通孔电性连接半导体封装件的第一和第二线路重布结构，故能另提供其它封装件或电子组件接置。
附图说明
图1A及图1B为现有晶圆级芯片尺寸封装件的剖面示意图；
图2A至图2J为本发明的半导体封装件的制法剖面示意图；
图3为本发明的半导体封装件的一应用实施例的剖面示意图；以及
图4为本发明的半导体封装件的另一应用实施例的剖面示意图。
主要组件符号说明
104            胶膜
116            侧面
136            防焊层
138            焊球
14             线路重布结构
2              半导体封装件
20             承载件
21             粘着层
102、22        芯片
106、22a       作用面
114、22b       非作用面
108、220       电极垫
112            封装胶体
23             软质层
230            第一通孔
231            第一导电通孔
23a            第一表面
23b            第二表面
24             支撑层
24b、24b’     第三表面
240            第二通孔
241            第二导电通孔
25             第一线路重布结构
250            第一开孔
251            第一介电层
252            第一线路层
253            第一导电盲孔
254            第一绝缘保护层
26             第二线路重布结构
260            第二开孔
261            第二介电层
262            第二线路层
263            第二导电盲孔
264            第二绝缘保护层
27、31、41     导电组件
3              电子组件
4              封装件。
具体实施方式
以下借由特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。本发明也可借由其它不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不背离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本实用新型可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本实用新型所能产生的功效及所能达成的目的下，均应仍落在本实用新型所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一”、“第二”、“第三”及“上”等的用语，也仅为便于叙述的明了，而非用以限定本实用新型可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本实用新型可实施的范畴。
请参阅图2A至图2J，将详细说明本发明的半导体封装件的制法的一实施例的剖面示意图。
请参阅图2A，提供一承载件20，该承载件20上形成有粘着层21；接着，提供具有相对的作用面22a及非作用面22b的芯片22，该芯片22作用面22a上具有多个电极垫220，将该芯片22以其作用面22a结合于该粘着层21上。
请参阅图2B，提供一软质层23，将该软质层23形成于该芯片22的非作用面22b及粘着层21上，以使该芯片22嵌埋于该软质层23中，其中，该软质层具有相对的第一表面23a和第二表面23b。该软质层23的材料可例如但不限于Ajinomoto Build-up Film(ABF)、聚酰亚胺(Polyimide,PI)或硅氧树脂(polymerized siloxanes,silicone)，此外硅氧树脂也称为硅酮（polysiloxanes）等等；接着，提供一支撑层24，该支撑层24具有相对于该第二表面23b的第三表面24b，将该支撑层24形成于该软质层23的第二表面23b上，以使该芯片22夹置于该支撑层24和粘着层21之间，其中，该支撑层24的材料可为玻璃或硅。
请参阅图2C，移除该承载板20与粘着层21，以使该芯片22的作用面22a外露于该软质层23的第一表面23a。
请参阅图2D，于该软质层23中形成第一通孔230。
请参阅图2E，于该第一通孔230中，可通过电镀技术，形成第一导电通孔231。
请参阅图2F，于该芯片22的作用面22a及软质层23的第一表面23a上形成第一线路重布结构25，以使该第一线路重布结构25与该第一导电通孔231电性连接，详言之，形成该第一线路重布结构25的步骤复包括：于该芯片22的作用面22a及软质层23的第一表面23a上形成第一介电层251，其材料例如为低温钝化(low temperaturepassivation)材料；于该第一介电层251表面上形成第一线路层252，且于该第一介电层251中形成第一导电盲孔253以电性连接该第一线路层252、电极垫220和第一导电通孔231；以及于该第一介电层251上形成具外露部分该第一线路层252的第一开孔250的第一绝缘保护层254。
请参阅图2G，薄化该支撑层24，使该支撑层24具有相对于该第二表面23b的第三表面24b’。须说明的是，图2G所示的薄化步骤仅为例示，以下步骤也可实施于未薄化的支撑层24的第三表面24b上。
请参阅图2H，自第三表面24b’侧于该支撑层24中形成与该第一导电通孔231导通的第二导电通孔241。于该支撑层24的材料为硅的实施方式中，该第二导电通孔241为穿透硅通孔(through-silicon via,TSV)；于该支撑层24的材料为玻璃的实施方式中，该第二导电通孔241为玻璃导通孔(through-glass via,TGV)。
请参阅图2I，于该支撑层24的第三表面24b’上形成第二线路重布结构26，以通过该第一导电通孔231和第二导电通孔241与该第一线路重布结构25电性连接，详言之，形成该第二线路重布结构26的步骤复包括：于该支撑层24的第三表面24b’上形成第二介电层261，其材料例如为低温钝化(low temperature passivation)材料；于该第二介电层261表面上形成第二线路层262，且于该第二介电层261中形成第二导电盲孔263以电性连接该第二线路层262和第二导电通孔241；以及于该第二介电层261上形成具有外露部分该第二线路层262的第二开孔260的第二绝缘保护层264。
请参阅图2J，于该第一开孔250中的外露的第一线路层252上形成导电组件27，该导电组件27通过该第一线路层252与该芯片22的电极垫220电性连接。
根据前述的制法，本发明提供一种半导体封装件，如图2I所示，包括：软质层23，其具有第一导电通孔231及相对的第一表面23a及第二表面23b；至少一芯片22，其嵌埋于该软质层23内，该芯片22具有相对的作用面22a、非作用面22b及多个形成于该芯片22的作用面22a的电极垫220，且该芯片22的作用面22a外露于该软质层23的第一表面23a；支撑层24，其设于该软质层23的第二表面23b上并具有第二导电通孔241及相对于该第二表面23b的第三表面24b’(或为未薄化的支撑层24的第三表面24b)，且该第一导电通孔231与第二导电通孔241导通；第一线路重布结构25，其设于该芯片22的作用面22a及软质层23的第一表面23a上并与该第一导电通孔231和电极垫220电性连接；以及第二线路重布结构26，其设于该支撑层24的相对于该软质层23的第三表面24b’上，并通过该第一导电通孔231及第二导电通孔241与该第一线路重布结构25电性连接。
该第一线路重布结构25包括形成于该软质层23的第一表面23a上的第一介电层251、形成于该第一介电层251表面上的第一线路层252、形成于该第一介电层251中且电性连接该第一线路层252、电极垫220和第一导电通孔231的第一导电盲孔253、及形成于该第一介电层251上外露部分该第一线路层252的第一绝缘保护层254。
该第二线路重布结构26包括形成于该支撑层24的第三表面24b’上的第二介电层261、形成于该第二介电层261表面上的第二线路层262、形成于该第二介电层261中且电性连接该第二线路层262和第二导电通孔241的第二导电盲孔263、以及形成于该第二介电层261上外露部分该第二线路层262的第二绝缘保护层264。
须说明的是，所述的支撑层24的材料可为硅或玻璃，可增加封装件的强度，降低封装件翘曲的可能性，此外，以玻璃代替硅更可利用其透光性方便第二线路重布结构的对位。而所述的软质层23的材料为Ajinomoto Build-up Film(ABF)、聚酰亚胺或硅氧树脂。
再者，本发明的半导体封装件也可供其它封装件或电子组件接置，以形成堆栈封装结构。
另请参阅图3至图4，其为本发明的半导体封装件的应用实施例的剖面示意图。
如图3所示，本发明的半导体封装件2上方通过导电组件31而接置电子组件3。
如图4所示，本发明的半导体封装件2上方通过导电组件41而接置另一封装件4。
综上所述，本发明的半导体封装件及其制法，于半导体封装件中以硅或玻璃为材料作为支撑层，该支撑层介于线路重布结构和嵌埋有芯片的软质层之间，借此可增加封装件的结构强度，减少翘曲发生。此外，于半导体封装件中形成导电通孔以电性连接上下侧的线路重布结构，故本发明的半导体封装件能提供其它封装件或电子组件接置。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种半导体封装件的制法，包括以下步骤：
提供一表面上形成有粘着层的承载板；
将至少一具有相对的作用面及非作用面的芯片以其作用面结合于该粘着层上，其中，该芯片的作用面上具有多个电极垫；
于该芯片的非作用面及粘着层上形成软质层，以使该芯片嵌埋于该软质层中，其中，该软质层具有相对的第一和第二表面，该第二表面上设有支撑层，以令该软质层夹置于该支撑层和粘着层之间，该支撑层具有相对于该第二表面的第三表面；
移除该承载板与粘着层，以使该芯片的作用面外露于该软质层的第一表面；
于该软质层中形成第一导电通孔；
于该芯片的作用面及软质层的第一表面上形成第一线路重布结构，并使该第一线路重布结构与该第一导电通孔电性连接；
于该支撑层中形成与该第一导电通孔导通的第二导电通孔；以及
于该支撑层的第三表面上形成第二线路重布结构，以通过该第一及第二导电通孔与该第一线路重布结构电性连接。
2.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该第一线路重布结构的步骤复包括：于该芯片的作用面及软质层的第一表面上形成第一介电层；于该第一介电层表面上形成第一线路层，且于该第一介电层中形成第一导电盲孔以电性连接该第一线路层、电极垫和第一导电通孔；以及于该第一介电层上形成外露部分该第一线路层的第一绝缘保护层。
3.根据权利要求1所述的半导体封装件的制法，其特征在于，于该支撑层中形成该第二导电通孔之前，还包括薄化该支撑层的步骤。
4.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该第二线路重布结构的步骤还包括：于该支撑层的第三表面上形成第二介电层；于该第二介电层表面上形成第二线路层，且于该第二介电层中形成第二导电盲孔以电性连接该第二线路层和第二导电通孔；以及于该第二介电层上形成外露部分该第二线路层的第二绝缘保护层。
5.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该第一导电通孔的步骤包括于该软质层中形成第一通孔，再于该第一通孔内形成第一导电通孔。
6.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该第二导电通孔的步骤包括于该支撑层中形成第二通孔，再于该第二通孔内形成第二导电通孔。
7.一种半导体封装件，其包括：
软质层，其具有第一导电通孔及相对的第一表面及第二表面；
至少一芯片，其嵌埋于该软质层内，该芯片具有相对的作用面与非作用面及多个形成于该芯片的作用面的电极垫，且该芯片的作用面外露于该软质层的第一表面；
支撑层，其设于该软质层的第二表面上并具有第二导电通孔及相对于该第二表面的第三表面，且该第一导电通孔与第二导电通孔导通；
第一线路重布结构，其设于该芯片的作用面及软质层的第一表面上并与该第一导电通孔和电极垫电性连接；以及
第二线路重布结构，其设于该支撑层的第三表面上，并通过该第一及第二导电通孔与该第一线路重布结构电性连接。
8.根据权利要求7所述的半导体封装件，其特征在于，该第一线路重布结构包括形成于该软质层的第一表面上的第一介电层、形成于该第一介电层表面上的第一线路层、形成于该第一介电层中且电性连接该第一线路层、电极垫和第一导电通孔的第一导电盲孔、及形成于该第一介电层上外露部分该第一线路层的第一绝缘保护层。
9.根据权利要求7所述的半导体封装件，其特征在于，该第二线路重布结构包括形成于该支撑层的第三表面上的第二介电层、形成于该第二介电层表面上的第二线路层、形成于该第二介电层中且电性连接该第二线路层和第二导电通孔的第二导电盲孔、以及形成于该第二介电层上外露部分该第二线路层的第二绝缘保护层。
10.根据权利要求7所述的半导体封装件，其特征在于，该支撑层的材料为硅，该第二导电通孔为穿透硅通孔。
11.根据权利要求7所述的半导体封装件，其特征在于，该软质层的材料为Ajinomoto Build-up Film(ABF)、聚酰亚胺或硅氧树脂。
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