CN103579155B - 制造用于热压键合的键合垫的方法以及键合垫 - Google Patents

制造用于热压键合的键合垫的方法以及键合垫 Download PDF

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Publication number
CN103579155B
CN103579155B CN201310327642.8A CN201310327642A CN103579155B CN 103579155 B CN103579155 B CN 103579155B CN 201310327642 A CN201310327642 A CN 201310327642A CN 103579155 B CN103579155 B CN 103579155B
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metal layer
bonding
bond pad
carrier material
layer
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CN103579155A (zh
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C.谢林
D.博罗维斯基
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Robert Bosch GmbH
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Robert Bosch GmbH
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Abstract

本发明涉及一种制造用于热压键合的键合垫（100）的方法（200），其中，所述方法（200）具有提供步骤（202）和沉积步骤（204）。在所述提供步骤（202）中提供一具有半导体结构的载体材料（102），其中，所述载体材料（102）的最外部的边缘层构造成一布线金属层（106），用于电接触所述半导体结构。在所述沉积步骤（204）中将一单层的键合金属层（104）直接在所述布线金属层（106）的表面上进行沉积，用以制造所述键合垫（100）。

Description

制造用于热压键合的键合垫的方法以及键合垫
技术领域
本发明涉及一种制造用于热压键合的键合垫的方法，此外还涉及一种用于将一个载体材料与另一个载体材料进行热压键合的键合垫、一种具有所述键合垫的构件以及一种相应的计算机程序产品。
背景技术
为了能够电接触半导体结构的接触接头，大多采用键合垫，其被敷设到半导体结构的各相关的接触接头上。键合垫大多具有多层的结构。为了成形出所述键合垫，将一下层结构进行结构化，其被施布到待连接的材料上。将一键合金属施布到所述下层结构上。
例如在Tang等人的出版物“Wafer-Ievel Cu-Cu bonding technology”（Microelectronics Reliability52 （2012） 312-320）中公开了一种由钽和铜制成的层结构。在Huffman等人的出版物“Fabrication and characterization of metal-to-metalinterconnect structures for 3-D Integration”（Journal of InstrumentationVolume 4 （2009））中公开了一种由钛和铜制成的层结构。Froemel等人在他们的出版物“Investigations of thermocompression bonding with thin metal layers”（Proceedings of Transducers '11）中公开了由钽和铜、钛和金以及由铝制成的层结构。
发明内容
在该背景下本发明涉及一种制造用于热压键合的键合垫的方法，此外还涉及一种用于将一个载体材料与另一个载体材料进行热压键合的键合垫、一种具有所述键合垫的构件以及一种相应的计算机程序产品。
铝作为键合材料由于作为印制导线标准材料而仅需克服最小的障碍，用以在工业生产中建立晶片键合，但作为金和铜需要较高的工艺温度并且由于铝容易氧化而成为难以掌控的键合系统。金和铜迄今为止以由大多情况下的附着层、扩散阻挡部和例如用于电镀的起始层构成的昂贵的层结构来制成。这些层中的每一个都需要结构化，这导致了复杂的工艺，其中，大量的参数必须相互协调。
本发明基于如下知识，即能够将键合金属直接沉积到芯片的印制导线层上，其中，所述印制导线层在此情况下能够满足作为芯片内部的电连接以及作为键合金属的载体的双重功能。在所述印制导线层中可以集成一扩散阻挡部作为最上部的层。
通过将单层的键合金属直接沉积到芯片的印制导线层上可以节省耗时的工作步骤。键合垫的结构高度可以被减小，从而可以实现相互键合的小芯片之间的更小的间距。
本发明提出了一种用于制造热压键合用的键合垫的方法，其中，所述方法具有下列步骤：
提供一具有半导体结构的载体材料，其中，所述载体材料的最外部的边缘层构造成一布线金属层，用以电接触所述半导体结构；并且
将一单层的键合金属层直接沉积到所述布线金属层的表面上，用以制造所述键合垫。
此外，本发明提供了一种用于将一个载体材料与另一个载体材料进行热压键合的键合垫，其中，所述键合垫具有下列特征：
载体材料，其具有半导体结构，其中，所述载体材料的最外部的边缘层构造成一布线金属层，用以电接触所述半导体结构；以及
单层的键合金属层，其直接布置在所述载体材料的布线金属层的表面上。
此外本发明提出一种具有下列特征的构件：
具有至少一个根据这里介绍的方法所述的第一键合垫的第一载体材料；以及
具有至少一个根据这里介绍的方法所述的第二键合垫的第二载体材料，其中，所述第二键合垫与所述第一键合垫至少部分地重叠，并且所述第二键合垫面对所述第一键合垫，并且与所述第一键合垫经由键合过程进行材料接合地连接。
键合垫可以理解为一种连接元件，其构造用于与另一键合垫在用于热压键合的键合过程期间形成一种材料接合的连接。所述键合过程在此情况下是一热过程，其中，所述键合垫的材料被加热到以键合温度上，以便能够在两个键合垫之间的接触面上实现晶体和/或微晶的增长。所述键合温度在此情况下低于所述材料的液相温度。所述键合垫在所述键合过程期间以一压紧力相互压紧。载体材料可以是芯片或晶片。所述载体材料可以具有半导体材料。半导体结构可以例如是集成的电路或微机械传感器。布线金属层可以是导电的金属的和/或陶瓷的层，由所述布线金属层可以构造出印制导线，用以将例如所述半导体结构相互连接起来。沉积可以理解为将材料组成部分聚积到表面上。在沉积时可以构造出具有预设的层厚度的层。所述层厚度可以均匀地沉积在一个面上，在该面上沉积所述键合金属。
所述第一键合垫和所述第二键合垫可以分别构造成至少一个键合触头，用于将所述第一载体材料与所述第二载体材料电连接。所述第一键合垫和所述第二键合垫也可以替选地或附加地分别构造成键合框，用于密封所述第一载体材料和所述第二载体材料之间的空穴。如果所述两个载体材料在预设的大气中进行连接，则在在所述载体材料之间的键合框内部可以保留住所述大气。例如可以将所述载体材料在真空下连接起来。然后在键合框内部即使在去除之后也可以由真空构成一抽真空的空间。例如可以如此提供一用于压力传感器的参考压力腔室。
所述载体材料可以提供具有由Al基的导电材料制成的布线金属层。替选地或附加地，可以沉积一Cu基或Au基的金属层作为键合金属层。Al基的材料可以理解为一种材料，其至少部分地具有铝（Al）。Cu基的材料可以理解为一种材料，其至少部分地具有铜（Cu）。Au基的材料可以理解为一种材料，其至少部分地具有金（Au）。例如所述布线金属层可以由纯的Al、AISi、AlSiCu、AICu构成，其中，这些材料在上方以及在下方可以被扩散阻挡层例如Ti/TiN或Ta/TaN围住，即所述布线金属层由例如Ti/TiN/AICu/Ti/TiN构成。例如所述键合金属层可以作纯的铜（Cu）或纯的金（Au）沉积。Al基的印制导线可以特别简单地进行加工。Cu和Au具有防腐蚀的特性。例如所述键合金属层可以电镀地或者通过溅射方法来沉积。由此可以产生特别均匀的薄的层厚度。
所述方法可以具有掩模步骤，其中，在所述掩模步骤中将所述布线金属层的表面上的至少一个待敞开的（freizuhaltender）的掩模区域以一掩模层进行遮盖，其中，在沉积步骤中将所述键合金属层在所述布线金属层的表面的未掩模的区域中沉积。所述未掩模的区域可以预设的宽度，例如在0.1μm和1000μm之间的宽度、尤其是在1μm和500μm之间的宽度来空出。所述方法可以特别是具有去除步骤，其中，所述掩模层在所述去除步骤中被去除。掩模可以理解为具有例如光敏涂层的表面，所述光敏涂层在曝光的区域中硬化。在未曝光的区域中可以布置工作区域，在所述工作区域中，所述涂层不硬化并且可以被去除。之后，所述表面在所述工作区域中暴露并且可以继续加工。在沉积步骤中可以选择性地在所述暴露的区域中沉积所述键合金属。通过限定用于沉积的面，可以有目的性地布置和成形所述键合垫。这样可以节省宝贵的贵金属。
至少一个密封区域可以在所述布线金属层的表面上为了沉积所述键合金属层而空出，其中所述密封区域具有环形闭合的轮廓。所述密封区域可以是一种待密封的区域的连续的边界结构。所述密封区域可以在所述区域中围出功能元件的轮廓。通过所述密封区域可以提供一种在两个相邻布置的载体材料之间的封闭的空穴。
所述载体材料可以在所述方法的一种替选的变型中提供有未结构化的布线金属层。在之前的去除掩模层的步骤之后可以在另一掩模步骤中将另一掩模层涂覆到所述键合金属层和所述布线金属层的部分上。在结构化步骤中可以将未掩模的部位上的布线金属层剥除。随后可以将所述另一掩模层在另一个去除步骤中去除。由于连续的布线金属层，所述键合金属层可以特别是电化学地沉积。通过电化学的沉积方法，可以产生所述键合金属的特别光滑和/或均匀的层厚度。所述层厚度可以精确地确定。在结构化时可以例如将所述布线金属层进行蚀刻。
所述载体材料可以提供有一结构化的布线金属层。当所述布线金属层已经结构化地提供时，可以特别是采用湿化学的沉积方法来沉积所述键合金属层。提供湿化学方法可以将所述键合金属层以预设的组分进行沉积。在湿化学方法的情况下无需用于沉积的区域的电接触。
所述布线金属层的表面可以设有一扩散阻挡部。例如可以将TiN、TaN或TiW在整个面上完全嵌入到所述布线金属层的表面中去，用以在键合中以及之后阻止扩散过程。
所述载体材料可以提供有至少一个微电子机械结构，所述微电子机械结构通过所述布线金属层的至少一个部分区域来电接触。微电子机械结构可以具有可动的区域，所述区域可以经由半导体技术的制造步骤来制成。所述微电子机械结构可以布置在所述密封区域内部。所述微电子机械结构可以是传感器、例如压力传感器或加速度传感器的组成部分。
所述方法可以具有对键合金属层进行空气调节的步骤。在所述空气调节时所述键合金属层的暴露的表面针对下一键合过程做准备。空气调节例如可以理解为平滑、清洁或整平层厚度。通过所述空气调节可以改善所述键合过程。由此可以提高所述键合连接的品质。例如通过所述空气调节在所述密封区域的很小的宽度的情况下就能够实现所述密封区域的密闭的密封。由此可以节省键合金属和芯片面积。
所述载体材料可以提供有在预设的厚度，例如在0.01μm和200μm之间的厚度、尤其是在0.1μm和20μm之间的厚度的布线金属层。所述键合金属层可以以预设的厚度，例如在0.001μm和10μm之间的厚度、尤其是在0.01μm和1.0μm之间的厚度来沉积。通过这种预设的层厚度可以限定所述层的内部的微晶大小。在较小的微晶的情况下，一种材料可以相对于平均状态具有改善的材料特性例如提高的抗拉强度和/或更大的硬度。小的微晶可以在键合过程中提供大量晶核，用于超出界面的晶体增长。
有利的还有，具有程序代码的计算机程序产品，所述程序代码可以存储在机器可读的载体如半导体存储器、硬盘存储器或光学存储器上，并且当所述程序产品在一计算机或一设备上实施时，用于实施或操控按照前述的实施方式的方法的步骤。
附图说明
下面参照附图示例性地详细阐释本发明。其中:
图1 示出了根据本发明的一个实施例的键合垫的截面图；
图2 示出了根据本发明的一个实施例的用于制造键合垫的方法的流程图；
图3 示出了根据本发明的一个实施例的提供的载体材料的截面图；
图4 示出了根据本发明的一个实施例的在涂覆了掩模层之后的所述载体材料的截面图；
图5 示出了根据本发明的一个实施例的在沉积所述键合金属的步骤之后的被掩模的载体材料的截面图；
图6 示出了根据本发明的一个实施例的在沉积所述键合金属的步骤之后并且在去除所述掩模层之后的所述载体材料的截面图；
图7 示出了根据本发明的一个实施例的在涂覆了另一个掩模层的步骤之后的所述载体材料的截面图；
图8 示出了根据本发明的一个实施例的在结构化所述布线金属层的步骤之后的所述被掩模的载体材料和键合金属的截面图；
图9 示出了根据本发明的一个实施例的具有涂覆的键合金属和结构化的布线金属层的两个载体材料的截面图；
图10 示出了根据本发明的一个实施例的由两个相互键合的载体材料构成的构件的截面图；
图11 示出了根据本发明的另一个实施例的具有结构化的布线金属层的、提供的另一个载体材料的截面图；
图12 示出了根据本发明的另一个实施例的具有涂覆的掩模层的所述另一个载体材料的截面图；
图13 示出了根据本发明的另一个实施例的具有沉积的键合金属的被掩模的载体材料的截面图；
图14 示出了根据本发明的另一个实施例的具有涂覆的键合金属的两个载体材料的截面图；
图15 示出了根据本发明的一个实施例的由两个相互键合的载体材料构成的构件的截面图；
图16 示出了根据本发明的一个实施例的具有一功能区域和一环围的密封区域的载体材料的示图。
在下面的本发明的优选实施例的描述中，针对在不同的附图中展示的并且相似作用的元件采用相同的或者相似的附图标记，其中，舍弃了所述元件的重复描述。
具体实施方式
图1示出了根据本发明的一个实施例的键合垫100的截面图建和。所述键合垫100构造用于将一个载体材料102与另一个未示出的载体材料通过一热压键合方法连接起来。所述键合垫100具有一单层的键合金属层104，其直接布置在所述载体材料102的布线金属层106的表面上。所述布线金属层106可以例如仅是单层的并且形成所述载体材料102的最外部的边缘层。所述载体材料102例如通过一具有未示出的半导体结构的晶片或芯片形成，所述半导体结构被所述布线金属层106电接触。在图1中示出了所述载体材料102的一个部分。在所示的实施例中，所述布线金属层106大面积地布置在所述载体材料102上。所述布线金属层106实施成基于铝的印制导线材料。所述键合金属层104由金或铜制成并且电化学地或者湿化学地沉积在所述布线金属106上。所述键合金属层104具有在0.01μm和1.0μm之间的厚度。所述键合金属层104具有在1μm和500μm之间的横向宽度。所述布线金属层106具有在0.1μm和20μm之间的厚度。
换句话说，图1示出了针对热压键合方法的层结构。所述热压键合方法作为用于连接两个晶片102的技术是能够以大量不同的层结构来实施的。
在图1中描述的层系统大大减少了用于结构化所述键合连接的费用，由此实现了比迄今为止更经济实惠的、具有更少错误源的高效的制造工艺。所述键合连接同时代表了一种机械稳定的、密闭的以及电的连接，且因此可以通过仅一个键合步骤来满足最多三个功能。
图2示出了根据本发明的一个实施例的用于制造键合垫的方法200的流程图。所述方法200具有至少一个提供的步骤202和沉积的步骤204。在所述提供步骤202中，提供一具有半导体结构的载体材料。所述载体材料的最外部的边缘层构造成布线金属层，用于电接触所述半导体结构。在沉积步骤204中将一单层的键合金属层直接沉积在所述布线金属层的表面上，用以产生所述键合垫。在步骤204中可以将所述键合金属层电化学地或者湿化学地进行电镀。
所述方法200可以在至少两个变型中实施。在第一变型中，在采用电化学电镀的情况下为了将两个衬底连接起来，所述方法200可以具有下面的工艺步骤，所述工艺步骤可以在至少两个待相互连接的衬底上实施。起始状态是具有可能的层下部结构的平整地以布线金属进行覆层的衬底。在涂覆和结构化的步骤中将不传导的掩模层例如由光致抗蚀剂、聚酰亚胺、氮化硅制成的掩模层进行涂覆和结构化。在沉积步骤204中将键合金属层例如借助于电化学的沉积方法进行沉积。在去除步骤中将所述掩模层再次去除。可选地，可以在涂覆步骤中涂覆第二掩模层。在结构化步骤中可以将所述布线金属例如借助于等离子蚀刻进行结构化。可选地，可以在去除步骤中将所述第二掩模层去除。在热压键合的步骤中将至少两个衬底进行连接。所述变型1的步骤在图3至10中展示。
在第二变型中，在采用化学电镀的情况下为了将两个衬底连接起来，所述方法200可以具有下面的工艺步骤，所述工艺步骤可以在至少两个待相互连接的衬底上实施。起始状态是一在衬底上具有可能的层下部结构的、结构化的布线金属层。不传导的掩模层例如由光致抗蚀剂、聚酰亚胺、氮化硅制成的掩模层的可选的、涂覆和结构化步骤。所述键合金属层的例如借助于化学沉积方法的沉积步骤204。可选地去除所述掩模层的步骤。以及所述至少两个衬底的热压键合步骤。所述变型2的步骤在图11至15中展示。
可选地其它的工艺步骤是可行的。可以在键合之前和/或期间实施所述键合金属表面的例如借助于等离子处理（例如氩-背溅射（Ar-Rücksputtern））和/或气体处理（例如利用合成气体（Formiergas））和/或蒸汽处理（例如利用蚁酸）和/或湿化学清洁来进行清洁/空气调节的步骤。可以实施一用于键合后退火（Post-Bond Annealen）的热处理步骤，用以强化所述键合附着力。所述方法200可以具有在键合之前涂覆和结构化其它的层的步骤。
所述的晶片键合连接或者说所述方法可以用于制造具有封装的传感器、例如红外线传感器阵列（Infrarot-Sensorarrays）、加速度传感器、旋转率传感器、压力传感器。
有利地，根据这里介绍的方法取消了用于沉积所述键合金属层的单独的起始层。通过薄的键合层实现了小的微晶大小。小的微晶允许在所述键合垫的界面上的快速的换位（Umlagerung）且因此允许一稳固的键合连接。通过电镀沉积可以实现光滑的表面。通过这里介绍的方法可以产生出经济实惠的、耐腐蚀的键合连接，其实现了在两个衬底之间的定义的间距。
对于所述热压键合有利的是，所述键合表面尽可能平滑并且全都位于一个平面上，因为之后在键合过程中所述键合面的大部分区域开始接触。电化学的沉积方法特别好地适用产生光滑的表面。此外，利用电化学的沉积方法可以对选择的确定的区域进行覆层并且不仅实现几个纳米（nm）厚度的薄的层，而且实现多个微米（μm）厚度的特别厚的层。
在所述热压键合期间，在接触面上通过在所述键合面的两侧的（内部）扩散过程会出现（重）结晶和晶粒的晶粒增长，这导致了键合界面的相互附着。在薄层的情况下的晶粒明显小于在厚层的情况下的晶粒，在键合时的换位可以比在厚层的情况下更快地以及更完全地进行。此外，由于过程兼容性的原因，键合连接是有利的，其可以在较低的温度下进行并且之后仍然能够承受高温。因此，大多随着较低的键合能和熔融温度而出现的具有较低的扩散能的键合金属是特别受到关注的。
图3至10示出了半成品（或者说图10中的制成的键合垫的半成品）的示图，其在实施了与前述的根据本发明的一个实施例的用于制造键合垫100的所述方法200的第一变型的工艺流程的步骤之后得以获得。这些示图展示了在实施了在采用电化学的电镀的情况下的工艺步骤之后获得的产品阶段的穿过所述键合触点中的一个的详细横截面视图，所述键合触点如在图16中所示。
图3示出了用于使用在本发明的一个实施例中的提供的载体材料102的截面图。所述载体材料102在一个状态中示出，在该状态中其被提供用于一根据本发明的一个实施例的用于制造一键合垫的方法。在图3中展示了晶片或芯片的一个部分区域，其通过载体材料102形成。所述载体材料102超出所示的部分区域延伸到一垂直于所述截面图的示图平面的平面中。所述载体材料102具有一由例如晶体硅制成的衬底300。在所述衬底300上布置一层下部结构（Schichtunterbau）302，其可以包含半导体结构（例如微机械传感器）的组成部分。所述层下部结构302也可以具有一附着连接层，以便能够实现与所述载体材料102的由一布线金属制成的最外部的边缘层的牢固的连接。所述布线金属层106或者布线金属平面106是基于铝的并且例如由纯的铝或者AlSi、AlSiCu、AICu或者Ti/TiN/AICu/Ti/TiN构成。其它的Al基的金属或合金或层顺序部也是可行的。
图4示出了根据本发明的一个实施例的具有涂覆的掩模层400的载体材料102的截面图。所述载体材料102相应于图3中的载体材料并且具有衬底300、层下部结构302和布线金属平面106。所述掩模层400在一掩模的工艺步骤中被涂覆到所述布线金属层106上并且随后被结构化。所述掩模层400在该实施例中是电绝缘的。例如将所述掩模层400针对一种光刻方法作为光敏涂层进行涂覆。所述涂层的部分区域随后被曝光。根据所采用的涂层的不同，随后将所述涂层的曝光的或者未曝光的部分区域去除并且产生出未掩模的区域402，所述布线金属106的表面暴露（freiliegt）在该区域中。
图5示出了根据本发明的一个实施例的具有沉积的键合金属104的被掩模的载体材料102的截面图。所述载体材料102对应于在图4中展示的载体材料。在所述未掩模的区域402中，在一沉积步骤中将所述键合金属层104直接沉积到所述布线金属106的表面上。在以掩模层400遮盖的部位处没有沉积键合金属。所述沉积在该实施例中是电化学地实施的。为此将连续的布线金属层106置于一个电势上，并且所产生的电场已经将金离子或铜离子从一电镀池中迁移到所述布线金属106的暴露的表面上，在那里它们作为金属层104被沉积。电镀的持续时间以及其它的工艺参数例如电解液的流速和电流强度确定了所述键合金属层104的层厚度。
图6示出了根据本发明的一个实施例的具有沉积的键合金属104以及去除的掩模层的载体材料102的截面图。所述载体材料102对应于在图5中展示的载体材料。所述掩模层在一去除步骤中被去除。所述布线金属层的表面的被掩模的部分区域600再次暴露。
图7示出了根据本发明的一个实施例的具有涂覆的另一掩模层700的载体材料102的截面图。所述载体材料102对应于在图6中展示的载体材料。所述第二掩模层700在另一个掩模步骤中被涂覆以及结构化，例如在图4中所述。所述键合金属层104以及所述布线金属层106的表面的部分区域通过另一掩模层700遮盖。所述布线金属106的剩余的表面702暴露。
图8示出了根据本发明的一个实施例的掩模的载体材料102和键合金属104的截面图，具有结构化的布线金属层106。所述载体材料102对应于在图7中展示的载体材料。在一结构化步骤中将所述未掩模的区域702中的布线平面106剥除。所述层下部结构302暴露在所述未掩模的区域702中。因此，在所示的部分中，从所述布线平面106中加工出一印制导线800，其将一键合触头802与所述载体材料102的半导体结构进行导电连接。此外，从所述布线平面106中加工出一用于密封区域804的底座。所述键合触头802和所述密封区域804的键合金属层104布置在一个平面中。
换句话说，图8示出了一金属系统。其由一布线平面106（例如AI、AISi、AlSiCu、AICu、 Ti/TiN/AICu/Ti/TiN）和至少一个位于其上的键合金属层104（例如Au、Cu）构成。所述金属系统可通过横截面剖开以及其它的广为流传的物理方法进行证明。这里介绍的金属系统可以用于所有的应用中，在这些应用中应该产生至少两个晶片或芯片102或者一个晶片102和一个芯片102之间的机械稳定的连接和/或密闭性的密封和/或电接触。这可以是例如在制造红外线传感器阵列、加速度传感器、旋转率传感器、压力传感器时的情况。
图9示出了根据本发明的一个实施例的具有涂覆的键合金属104和结构化的布线金属层106的两个载体材料102、900的截面图。第一载体材料102对应于在图7中展示的载体材料。在一去除步骤中去除所述另一掩模层并且所述键合金属层104再次暴露。所述键合触头和所述密封区域以所述键合金属的材料厚度突出于所述布线金属层之外。第二载体材料900与所述第一载体材料102镜像地实施。所述第二载体材料900具有在一公差范围内的与所述第一载体材料102呈镜像的轮廓。所述第二载体材料900的键合金属层104面向所述第一载体材料102的键合金属层104并且与其完全相同地取向。在所述第一载体材料102和所述第二载体材料900之间是一间距。
图10示出了根据本发明的一个实施例的由两个相互键合的载体材料102、900构成的构件1000的截面图。所述载体材料102、900相应于图9中的载体材料。所述载体材料102、900的键合金属层104直接地相互贴靠。在一键合或者说热压键合步骤中，将所述键合金属层相互连接并且晶粒超出所述键合金属层104之间的界面增长。所述两个衬底102、900相互具有一预设的间距。
换句话说，图10示出了由至少两个衬底102、900（例如晶片、芯片）构成的构件1000，所述衬底经由一金属的晶片键合连接部相互连接。所述金属的晶片键合连接部由至少一个键合金属层104（例如Au、Cu）构成，其位于所述布线平面106（例如由AI、AISi、AlSiCu、AICu制成，可选地具有位于其之间的例如由TiN、TaN或TiW制成的扩散阻挡部）上。所述金属的晶片键合连接层104可以在所述衬底102、900中的至少一个上用于布线。所述金属的晶片键合连接层104可以在所述衬底102、900中的至少一个上相对于其它的层突起。所述金属的晶片键合连接部可以产生在至少两个衬底102、900之间的至少一个机械稳定的连接和/或电连接802和/或可选的密闭的、闭合的封闭连接804（“键合框”）。在所述衬底102、900中的至少一个上可以集成一MEMS构件。所述晶片键合金属化部104的表面可以在针对键合所设置的区域802、804上为了所述机械稳定的连接和/或电连接和/或密闭连接而在所述衬底102、900上分别突起并且位于同一个水平线上，例如以如下方式，即它们具有相同的层下部结构和/或所述表面在涂覆所述晶片键合金属化部104之前或之后被平面化。所述金属的晶片键合连接部可以在至少一个方向上具有在1μm和500μm之间的横向的结构宽度。通过所述金属的晶片键合连接部可以调节出在所述至少两个衬底102、900之间的从0.1μm至20μm的定义的间距。所述布线平面106可以具有从0.1μm至20μm的厚度并且所述键合金属层104可以具有从优选0.01μm至1.0μm的厚度。
图11至14示出了半成品（或者说制成的键合垫的半成品）的示图，其在实施了与前述的根据本发明的一个实施例的用于制造键合垫100的所述方法200的变型2的工艺流程的步骤之后获得。这些示图展示了在实施了用于化学电镀的工艺步骤之前和之后的工艺阶段的穿过所述键合触点中的一个的详细横截面视图，如在图16中所示。
图11示出了根据本发明的另一个实施例的具有结构化的布线金属层106的提供的载体材料102的截面图。所述载体材料102相应于图3中的载体材料并且具有衬底300、层下部结构302和布线金属平面106。与图3不同，所述布线金属层106已经被结构化并且作为用于一键合触头802和用于一密封区域804的区域来成形出。
图12示出了根据本发明的另一个实施例的具有涂覆的掩模层400的载体材料102的截面图。所述载体材料102相应于图11中的载体材料。在一掩模步骤中将所述掩模层400进行涂覆并且结构化。所述布线金属层106的印制导线被掩模，其中，所述印制导线将所述键合接触区域802与所述载体材料102的半导体结构连接起来。所述布线金属106在所述键合接触区域802中以及在所述密封区域804中暴露。
图13示出了根据本发明的另一个实施例的具有沉积的键合金属104的被掩模的载体材料102的截面图。所述载体材料102相应于图12中的载体材料。在所述布线平面106上在一沉积步骤中在暴露的区域802和804中沉积所述键合金属104。与图5中的实施例不同，所述键合金属104也在所述布线金属106的侧面上沉积。所述沉积在采用一湿化学工艺的前提下实施。在所述层下部结构302上不沉积键合金属。
图14示出了根据本发明的另一个实施例的具有涂覆的键合金属104的两个载体材料102、900的截面图。所述载体材料102相应于图13中的载体材料。在一去除步骤中将所述掩模层从所述印制导线上去除。所述键合金属层104从所述布线平面106上突起。所述第二载体材料900具有在一公差范围内的与所述第一载体材料102至少部分重叠的轮廓。所述第二载体材料900的键合金属层104面向所述第一载体材料102的键合金属层104。在所述第一载体材料102和所述第二载体材料900之间是一间距。
图15示出了根据本发明的一个实施例的由两个相互键合的载体材料102、900构成的构件1000的截面图。所述载体材料102、900相应于图14中的载体材料。所述载体材料102、900的键合金属层104直接地相互贴靠。在一键合或者说热压键合步骤中，将所述键合金属层相互连接并且晶粒在所述键合金属层104之间的界面上增长。所述两个衬底102、900相互具有一预设的间距。
图16示出了根据本发明的一个实施例的具有一功能区域1600和一环围的密封区域804的载体材料102的示图。所述功能区域1600在该实施例中是一微电子机械系统（MEMS）1600的至少一个组成部分。例如所述MEMS1600的另一个组成部分可以布置在一镜像地实施的另一个载体材料上。所述功能区域1600具有一矩形形状并且具有在相对置的窄面上各六个接头，其经由印制导线800、例如在图8中所示的印制导线与各一个键合触头802连接。环形闭合地环围所述MEMS1600地布置一密封区域804。所述密封区域804具有一与所述功能区域1600和所述键合触头802的间距。所述密封区域804具有倒圆的角。所述密封区域804和所述键合触头802以一单层的键合金属层104进行覆层，所述键合金属层直接在位于其下方的布线金属层上沉积。所述密封区域804和所述键合触头802布置在一个平面中并且从所述MEMS1600的平面上突起。
换句话说，图16展示了在所述构件的一个侧面的典型的构件布设，如在图9和14中所示。所述键合区域802、804具有一键合金属化部104。图3至15的示图展示了沿着穿过所述印制导线800中的一个、所述键合触头802中的一个以及所述密封区域804的截面线的截面。
所描述的并且在附图中所示的实施例仅是示例性地选择的。不同的实施例可以完全地或者关于单个的特征相互组合。一个实施例也可以通过其他实施例的特征来补充。
此外，可以重复根据本发明的方法步骤以及以不同于在所描述的顺序进行实施。
如果一实施例包含在第一特征和第二特征之间的“和/或”关联，则应该理解为，所述实施例根据一种实施方式不仅具有第一特征而且具有第二特征，并且根据另一种实施方式要么仅具有第一特征要么仅具有第二特征。

Claims (13)

1.制造一用于热压键合的键合垫（100）的方法（200），其中，所述方法（200）具有下列步骤：
提供（202）一具有半导体结构的载体材料（102），其中，所述载体材料（102）的最外部的边缘层构造成一布线金属层（106），用于电接触所述半导体结构，其中，所述布线金属层（106）具有一位于所述布线金属层（106）上的扩散阻挡部；并且
将一单层的键合金属层（104）以如下方式直接在所述布线金属层（106）的表面上进行沉积（204）用以制造所述键合垫（100），即，所述扩散阻挡部位于所述键合金属层（104）和所述布线金属层（106）之间。
2.根据权利要求1所述的方法（200），其中，在所述提供步骤（202）中所述载体材料（102）提供有一由Al基的导电材料制成的布线金属层（106），和/或在所述沉积步骤（204）中沉积至少一个Cu基的或Au基的金属层作为键合金属层（104）。
3.根据权利要求1或2所述的方法（200），具有掩模步骤，其中，在所述掩模步骤中将所述表面上的至少一个掩模区域以一掩模层（400）进行遮盖，其中，在所述沉积步骤中将所述键合金属层（104）在所述表面的未掩模的区域（402）中进行沉积。
4.根据权利要求3所述的方法（200），其中，在所述掩模步骤中将所述表面上的至少一个密封区域（804）空出，其中，所述密封区域（804）具有环形闭合的轮廓。
5.根据权利要求3所述的方法（200），其中，在所述提供步骤（202）中所述载体材料（102）提供有一未结构化的布线金属层（106），并且在一事先的去除掩模层（400）的步骤之后在另一掩模步骤中将另一掩模层（700）涂覆到所述键合金属层（104）和所述布线金属层（106）的部分上，并且在一结构化步骤中将未掩模的部位（702）处的布线金属层（106）剥除。
6.根据权利要求1或2所述的方法（200），其中，在所述提供步骤（202）中所述载体材料（102）提供有一结构化的布线金属层（106）。
7.根据权利要求1或2所述的方法（200），其中，在所述提供步骤（202）中所述载体材料（102）提供有至少一个微电子机械结构（1600），所述微电子机械结构通过所述布线金属层（106）的至少一个部分区域（800）进行电接触。
8.根据权利要求1或2所述的方法（200），具有对所述键合金属层（104）进行空气调节的步骤，其中，所述键合金属层（104）的暴露的表面针对下一键合过程做准备。
9.根据权利要求1或2所述的方法（200），其中，在所述提供步骤（202）中所述载体材料（102）提供有在预设的厚度、特别是在0.01μm和200μm之间的厚度中的布线金属层（106），和/或在所述沉积步骤（204）中所述键合金属层（104）以预设的厚度，特别是在0.001μm和10μm之间的厚度进行沉积。
10.键合垫（100），用于将一个载体材料（102）与另一个载体材料（900）进行热压键合，其中，所述键合垫（100）具有下列特征：
载体材料（102），其具有半导体结构，其中，所述载体材料（102）的最外部的边缘层构造成一布线金属层（106），用以电接触所述半导体结构，其中，所述布线金属层（106）具有一位于所述布线金属层（106）上的扩散阻挡部；以及
单层的键合金属层（104），其以如下方式直接布置在所述载体材料（102）的布线金属层（106）的表面上，即，所述扩散阻挡部位于所述键合金属层（104）和所述布线金属层（106）之间。
11.构件（1000），具有下列特征：
具有至少一个第一、根据权利要求10所述的键合垫（100）的第一载体材料（102）；
具有至少一个第二、根据权利要求10所述的键合垫（100）的第二载体材料（900），其中，所述第二键合垫（100）在相对于所述第一键合垫（100）的公差范围内与所述第一键合垫（100）至少部分地重叠，并且所述第二键合垫（100）面对所述第一键合垫（100），并且与所述第一键合垫（100）经由一键合过程进行材料接合地连接。
12.根据权利要求11所述的构件（1000），其中，所述第一键合垫（100）和所述第二键合垫（100）分别构造成至少一个键合触头（802），用于将所述第一载体材料（102）与所述第二载体材料（900）进行电连接，和/或所述第一键合垫（100）和所述第二键合垫（100）分别构造成一键合框（804），用于密封所述第一载体材料（102）与所述第二载体材料（900）之间的空穴和/或所述第一键合垫（100）和所述第二键合垫（100）分别构造成至少一个键合触头（802），用于将所述第一载体材料（102）与所述第二载体材料（900）进行机械连接。
13.具有程序代码的计算机程序产品，所述程序代码存储在机器可读的载体上，当所述计算机程序产品在一设备上实施时，所述程序代码用于操控或转换按照权利要求1至9中任一项所述的方法（200）的步骤。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3006236B1 (fr) * 2013-06-03 2016-07-29 Commissariat Energie Atomique Procede de collage metallique direct
DE102014202808A1 (de) * 2014-02-17 2015-08-20 Robert Bosch Gmbh Verfahren zum eutektischen Bonden zweier Trägereinrichtungen
DE102014211643A1 (de) 2014-06-18 2015-12-24 Robert Bosch Gmbh Trägermodul für ein Halbleiterbauteil, Herstellungsverfahren für ein Trägermodul und Verfahren zum Befestigen eines Halbleiterbauteils an einem Trägermodul
ES2962260T3 (es) 2014-08-08 2024-03-18 Univ Leland Stanford Junior Proteínas de fusión SIRPa alfa-anticuerpo
CN105355613B (zh) * 2015-10-27 2018-08-10 上海华虹宏力半导体制造有限公司 铝锗共晶键合的方法
DE102016112198A1 (de) * 2016-07-04 2018-01-04 Endress+Hauser Gmbh+Co. Kg Druckaufnehmer
US10056310B2 (en) * 2016-09-26 2018-08-21 International Business Machines Corporation Electrolytic seal
US10248486B2 (en) * 2016-09-29 2019-04-02 Intel Corporation Memory monitor
WO2018081448A1 (en) 2016-10-26 2018-05-03 The Board Of Trustees Of The Leland Stanford Junior University Modified immunoglobulin hinge regions to reduce hemagglutination
US11078272B2 (en) 2017-03-09 2021-08-03 The Board Of Trustees Of The Leland Stanford Junior University Treatment of pediatric brain tumors with targeting of CD47 pathway
DE102017007486B3 (de) 2017-08-09 2018-09-20 Azur Space Solar Power Gmbh Empfängerbaustein

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010059118A1 (en) * 2008-11-19 2010-05-27 Silex Microsystems Ab Functional capping

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3514314B2 (ja) * 2001-07-25 2004-03-31 ローム株式会社 半導体装置およびその製造方法
US20040262772A1 (en) * 2003-06-30 2004-12-30 Shriram Ramanathan Methods for bonding wafers using a metal interlayer
US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
JP3886513B2 (ja) * 2004-02-02 2007-02-28 松下電器産業株式会社 フィルム基板およびその製造方法
DE102004005668B4 (de) * 2004-02-05 2021-09-16 Snaptrack, Inc. Elektrisches Bauelement und Herstellungsverfahren
EP1953817B1 (en) * 2005-11-25 2012-10-31 Panasonic Corporation Sensor device and method for manufacturing same
US8241995B2 (en) * 2006-09-18 2012-08-14 International Business Machines Corporation Bonding of substrates including metal-dielectric patterns with metal raised above dielectric
JP2008098336A (ja) * 2006-10-11 2008-04-24 Stanley Electric Co Ltd 半導体発光素子およびその製造方法
KR100833508B1 (ko) * 2006-12-07 2008-05-29 한국전자통신연구원 멤즈 패키지 및 그 방법
JP2008243853A (ja) * 2007-03-23 2008-10-09 Renesas Technology Corp インターポーザ基板、それを利用したｌｓｉチップ及び情報端末装置、インターポーザ基板製造方法、並びにｌｓｉチップ製造方法
EP2011762B1 (en) * 2007-07-02 2015-09-30 Denso Corporation Semiconductor device with a sensor connected to an external element
US7927906B2 (en) * 2008-02-04 2011-04-19 Honeywell International Inc. Method for MEMS threshold sensor packaging
US8390047B2 (en) * 2008-11-14 2013-03-05 Faquir Chand Jain Miniaturized implantable sensor platform having multiple devices and sub-chips
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
DE102009002363B4 (de) * 2009-04-14 2019-03-07 Robert Bosch Gmbh Verfahren zum Befestigen einer ersten Trägereinrichtung an einer zweiten Trägereinrichtung
CN101908517B (zh) * 2009-06-05 2013-06-19 中芯国际集成电路制造(上海)有限公司 键合垫及其制造方法以及键合方法
US8482132B2 (en) * 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
US8159060B2 (en) * 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
TWI502696B (zh) * 2010-02-06 2015-10-01 Ind Tech Res Inst 接合結構及其製造方法
JP5693375B2 (ja) * 2010-05-28 2015-04-01 シチズンホールディングス株式会社 半導体発光素子
US8946877B2 (en) * 2010-09-29 2015-02-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor package including cap
US20130256913A1 (en) * 2012-03-30 2013-10-03 Bryan Black Die stacking with coupled electrical interconnects to align proximity interconnects

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010059118A1 (en) * 2008-11-19 2010-05-27 Silex Microsystems Ab Functional capping

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