CN103548154A - 半导体器件及制造方法 - Google Patents

半导体器件及制造方法 Download PDF

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CN103548154A
CN103548154A CN201280021446.1A CN201280021446A CN103548154A CN 103548154 A CN103548154 A CN 103548154A CN 201280021446 A CN201280021446 A CN 201280021446A CN 103548154 A CN103548154 A CN 103548154A
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T.王
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Abstract

一种制造半导体器件的方法，包括：提供具有半导体层的半导体晶片；在半导体层之上形成第一掩模层；在第一掩模层之上形成第二掩模层；对第二掩模层进行退火以形成岛；采用岛为掩模蚀刻通过第一掩模层和半导体层以形成柱阵列；以及在柱之间且然后在柱的顶部之上生长半导体材料。

Description

半导体器件及制造方法
技术领域
本发明涉及半导体器件以及制造半导体器件的方法。特别是，本发明涉及以高质量晶体结构生产半导体器件。例如，该器件可用于形成发光二极管和固态激光器。
背景技术
当前，有三种主要方法来制造固态照明设备所需的白色发光二极管（LED）：（1）三个LED芯片的封装，其每一个发射不同的波长（分别为红、绿和蓝）；（2）蓝光（460nm）LED和由来自该LED的蓝光泵出的黄色磷光粉的结合；（3）发射UV光的单一芯片，其在LED封装中由三种磷光粉（红、绿和蓝）吸收，并且重新发射为广谱白光。对于第一和第二方法，主要成分是蓝/绿LED，其二者基于InGaN材料系统。对于第三方法，需要具有高性能的紫外线（UV）发射器。
已经建立了用于InGaN基和AlGaN基器件的先进的生长技术，但是通常基于c-面蓝宝石基板。该极性方位因压电效应导致很强的内置电场，并且器件受到电子和空穴波函数之间重叠的减少以及很长的辐射再结合时间，因此量子效率很低。这是所谓的量子限制斯塔克效应（QCSE）。特别是，当发射器朝着绿光谱区域移动时，要求更高的InN组分，并且内部电场通常变得极高。这对于实现具有高性能的InGaN基发射器（特别是绿光发射器）呈现出主要障碍。对于AlGaN基UV发射器存在相同的问题，但是对于AlGaN比InGaN甚至更坏。
同质外延生长对于III族氮化物基光电器件是理想的。然而，由于提供能力的原因，诸如蓝宝石、SiC、硅等异质基板上的生长仍保持用于III族氮化物生长的主要方法。这样的″大晶格错配异质外延″导致高密度的断层。这将引起III族氮化物光电子的光学性能的显著下降，例如InGaN基近UV/蓝/绿光发射器和AlGaN/GaN基UV发射器。AlGaN/GaN基UV发射器比InGaN基发射器中的断层问题变得更加明显，因为AlGaN/GaN基UV发射器的光学性能比InGaN基发射器对断层更加敏感。
上述的两个问题（QCSE和断层）是进一步改善III族氮化物基光电子光学性能的两个基本障碍。
最有希望抵消QCSE负面影响的一个方法是沿着无极或半极方位生长，这已经在理论和实践上得到证实。无极或半极III族氮化物发射器的另一个主要优点是它们可发射偏振光。液晶显示器（LCD）需要偏振照明，并且当前的LCD需要超偏振元素来实现偏振照明。偏振器件的低透射效率导致降低效率，并且发射偏振光的器件是有利的。
最新的在无极或半极平面上生长III族氮化物已经对绿光发射器产生重大突破。然而，也已经暴露出主要的挑战，这些具有高性能的无极或半极III族氮化物发射器只能生长在极其昂贵的GaN基板上，即采用同质外延生长法。不幸地，无极或半极GaN基板非常小且极其昂贵。另外，高度的不均匀性也使它们不适合批量生产。
因此，希望在具有任何尺寸（例如至12英寸）的蓝宝石基板上获得具有高晶体模板(template)的无极或半极GaN，用于进一步生长InGaN基或AlGaN基器件结构。迄今为止，一直采用传统的外延横向生长过度（ELOG）来改善无极或半极GaN在蓝宝石上的结晶质量。ELOG技术基于选择性区域生长。通常，首先通过金属有机气相外延（MOVPE）或分子束外延（MBE）或氢化物气相外延（HVPE）在蓝宝石上生长标准的GaN层，然后该表面非原位涂覆电介质掩模，例如SiO2或Si3N4。然后，采用标准的光刻将掩模图案化成微米级条（不是纳米级）。掩盖的样品然后用作模板，以进一步通过MOVPE或MBE或HVPE生长。再生长在掩模窗口区域中的暴露的GaN上开始，因为GaN不生长在电介质掩模的顶部上。当生长表面达到掩模的高度之上时，GaN再生长在条形掩模之上横向延伸，并且可最终接合以形成光滑的表面。由蓝宝石和GaN之间的大晶格错配引起的从掩模条下开始的晶体结构中的断层被有效阻止。由于标准光刻的限制，掩模条宽度和侧翼宽度不能进一步减小到纳米级。因此，通常，直至过生长层达到大于10-20μm厚时才能获得平坦的表面。另外，难以将这样的方法应用在AlGaN的过生长，因为AlGaN横向生长率通常远小于GaN横向生长率，导致接合非常慢。
因此，传统的ELOG方法非常复杂，并且因此导致非常高的额外成本。
发明内容
本发明提供制造半导体器件的方法。该方法可包括提供具有半导体层的半导体晶片。该方法可包括在半导体层之上形成第一掩模层。该方法可包括在第一掩模层之上形成第二掩模层。该方法可包括退火或者以其他方式应用或改变第二掩模层以形成岛。该方法可包括采用岛作为掩模蚀刻通过第一掩模层和半导体层以形成柱阵列。该方法还包括在柱之间然后在柱的顶部之上生长半导体材料。
该方法可包括在生长半导体材料前去除岛。
由掩模层之一形成的盖子可在半导体材料的生长过程中留在每个柱的顶部上。这可为第一掩模层。
半导体层可支撑在基板上。基板可包括蓝宝石、硅和碳化硅中的至少一个。
生长在柱上的半导体材料可与制作半导体层（并且因此为柱）的材料相同，或者它可为不同的材料。
半导体层可由III族氮化物形成。例如，它可由氮化镓、氮化铟镓或氮化铝镓形成。半导体材料也可为III族氮化物材料，例如氮化镓、氮化铟镓或氮化铝镓。
第一掩模层可由二氧化硅和氮化硅的至少一个形成。
第二掩模层可由金属形成，例如，镍。
该方法还可包括去除支撑基板。这可包括去除柱的一部分，例如，最下部。
本发明还提供一种半导体器件，其包括柱阵列，其每一个包括由半导体材料形成的主要柱，并且每一个包括由其顶部上形成的掩模材料形成的盖子，半导体材料在柱之间以及柱的顶部之上且在盖子之上延伸，以形成连续层。两种半导体材料可为相同的，或者它们可为不同的。柱阵列可包括直径全部小于1000nm的柱，并且优选小于500nm，更优选小于300nm。在某些情况下，在直径上可有不规则性，从而某些柱很大，但是优选至少90%的柱具有如上给出尺寸的直径。柱的高度优选为至少500nm，更优选至少750nm。柱可全部为基本上相同的高度。掩模材料可为金属。
至少某些纳米柱在它们底部周围可具有腔体。
本发明基于所谓的自组织纳米掩模法以及随后的过生长的结合。自组织纳米掩模的制造非常简单，并且不需要额外的光刻。过生长的层与已知的ELOG法相比相对很薄，但是所获得的晶体质量等同于或好于传统的ELOG所获得的晶体质量。因此，可显著降低成本。另外，该方法可沿用于生长包括有极、无极或半极的任何III族氮化物。
附图说明
该方法或器件还可以任何组合方式包括本发明优选实施例的任何一个或多个步骤或特征，现在仅借助于示例并参考附图对其进行描述，其中：
图1a至1h示出了形成根据本发明实施例的器件的步骤；
图2是如图1d所示的纳米杆阵列的图像；以及
图3是示出作为入射x射线束的方位角的函数的x射线摇摆曲线对于根据图1a至1h的方法形成的样品且为无极GaN的标准样品的半高全宽曲线图。
具体实施方式
参见图1a，制造该器件的第一步骤是提供适当的半导体晶片201。晶片201是传统晶片且由基板205制成，其在此情况下包括蓝宝石层，其上是由氮化镓（GaN）形成的半导体层210。可采用其它的材料。例如，基板可为硅或碳化硅。半导体可为其他的适当材料，例如，其他的III族氮化物，如氮化铟镓（InGaN）或氮化铝镓（AlGaN）。
第一掩模层220提供在半导体层210之上，例如采用等离子增强化学气相沉积（PECVD）。第一掩模层220由二氧化硅形成并且以大致200纳米的均匀厚度沉积，尽管有用于该层的适当的选择性材料，例如，氮化硅。
第二掩模层230，包括在此情况下为镍的金属，提供在第一掩模层220之上。这可采用热蒸发或溅射或电子束蒸发。在该步骤中，形成范围为5至50纳米的大致均匀厚度的镍层，然后在600至900摄氏度的温度范围内在流动氮（N2）环境下退火。退火工艺的持续时间为1至10分钟，导致在第一掩模层220之上由镍层形成第二掩模层230，其包括不规则分布的自装配镍岛231。镍岛的每一个覆盖第一掩模层220的上表面各自接近圆形的区域，其直径通常为不小于100纳米且不大于1000纳米。因此，第二掩模层230可用作蚀刻下SiO2层的掩模，其中镍岛231掩盖下SiO2层的多个区域，并且镍岛之间的间隔留下SiO2层的多个暴露区域，以限定下SiO2层将被蚀刻的区域。
参见图lc，采用第二掩模层230的金属岛231作为掩模，第一掩模层220在反应离子蚀刻（RIE）工艺中采用CHF3或SF6通透蚀刻。该步骤提供不规则地分布在GaN层210之上二氧化硅的纳米柱（也称为纳米杆）240，其每一个包括第一掩模层220的各部分221和各镍岛231。每个纳米杆240对应于各自的镍岛，其直径与各自镍岛所覆盖的表面区域的直径大致相同。前述步骤产生的纳米柱240用于掩盖GaN层210的某些区域，且限定GaN层210将被蚀刻的区域（即纳米柱240之间的间隔中的暴露区域）。
参见图1d，在接下来的步骤，以前述步骤中形成的纳米柱240作为掩模对GaN层210进行蚀刻，例如，通过感应耦合等离子体蚀刻。该步骤涉及诸如图1d所示蚀刻通过GaN层210或者部分地蚀刻通过GaN层210。该步骤产生如图1d所示的纳米柱结构，其中纳米柱250从蓝宝石基板205向上延伸，每个纳米柱250包括GaN层210的各部分211、第一掩模层220的部分221和来自第二掩模层230的金属岛231。因此，该步骤的蚀刻产生GaN的暴露表面250a，其包括纳米柱250的侧面。每个纳米柱250的直径从顶部到底部近似不变，与由其各镍岛231覆盖的表面面积近似相同，尽管实际上通常产生一些锥形的纳米柱。
参见图le，然后去除形成第二掩模层230的镍岛231，导致纳米柱260包括GaN层210的各部分211、第一掩模层220的部分221。这可通过采用盐酸（HCl）或者硝酸（HNO3）的湿蚀刻实现。这留下了每个纳米柱，其主要包括GaN柱211及其顶端上的SiO2盖子221。
参见图1f，GaN纳米杆阵列用作模板，用于通过金属有机化学气相沉积（MOCVD）或MBE或HVPE在GaN柱211的侧面250a上沉积GaN270以进行过生长(overgrowth)。在GaN纳米杆（先横向再垂直）的侧壁上开始再生长，其中暴露GaN。这在纳米柱的壁面上形成层271。这些生长从柱向外并彼此相向，直到它们在该层最厚处接触。于是，这进一步防止在接触点272之下空间273中的进一步生长，并且在接触点之上的空间274中继续生长。在某些情况下，这留下了空间273作为每个纳米柱的底部周围的中空间隙或腔体。这些间隙可互连为形成腔体，其为迷宫的形式且在所有的或者基本上所有的纳米柱之间延伸。纳米柱顶部上的SiO2掩模221将防止GaN在它们的顶部上生长。参见图1g，当GaN的生长面达到SiO2纳米掩模221的高度之上时，GaN的再生长在SiO2纳米掩模的顶部之上横向进行，并且最终接合起来以形成在纳米掩模的顶部之上延伸的连续层，具有如图1h所示的光滑表面271。理论上，所有由模板（即，在纳米柱260中）产生的断层被有效阻挡。即使在纳米柱的底部周围没有留下腔体，来自纳米柱之间间隙的底部的生长通常由来自纳米柱的侧面的生长部分地或完全切断，并且延伸到纳米柱的顶部的断层数因此非常低。
一旦已经完成生长，可去除基板205。去除基板通常包括去除纳米柱260的底端。这可因纳米柱底部周围的中空空间273的存在而容易进行。纳米柱260的底部可去除至在接触点272之下的位置，即在中空空间273的顶部之下。这可导致具有低应力水平的非常均匀的结构。
图2示出了所形成的GaN纳米杆的高密度阵列，其每一个的直径为约200nm。重要的是注意GaN纳米杆的侧壁示出了所希望的垂直对准。
图3示出了如上所述生产的样品的X射线衍射结果。可以看到，与r平面蓝宝石上的标准无极GaN样品相比，x射线摇摆曲线的半高全宽对于入射x射线束的所有方位角都大幅减小（方位角的零角度定义为入射束的发射平行于生长GaN层的c方向）。这表明在本发明的该实施例中已经大幅减小断层密度。
再者，非常有效地将上述的方法沿用到在GaN纳米柱结构上过生长AlGaN，而没有接合问题的困扰，因为GaN纳米杆之间的间隙为纳米级，这远比上述传统的ELOG中通常采用的SiO2掩模中的间隙窄。另外，由于在过生长期间在纳米杆之间的间隙中留下的残留空旷，可消除传统的III族氮化物生长中通常发生的GaN上AlGaN的破裂问题。
应理解，本发明的其它实施例可由上述的那些进行变化。该方法可应用于基板、纳米柱结构材料和生长半导体材料的不同组合，但是主要应用于基板和生长的半导体具有足够不同晶格结构使在半导体晶格结构中形成断层成问题的情况下。显然，结构的精确比例可变化，尽管该方法的独特优点是可在小尺度上生产结构。

Claims (17)

1.一种制造半导体器件的方法，包括：
（i）提供具有半导体层的半导体晶片；
（ii）在所述半导体层之上形成第一掩模层；
（iii）在所述第一掩模层之上形成第二掩模层；
（iv）对所述第二掩模层进行退火以形成岛；
（v）采用所述岛作为掩模蚀刻通过所述第一掩模层和所述半导体层以形成柱阵列；
（vi）在所述柱之间、然后在所述柱的顶部上生长半导体材料。
2.根据权利要求1所述的方法，还包括在生长所述半导体材料之前去除所述岛。
3.根据权利要求1或权利要求2所述的方法，其中由所述掩模层之一形成的盖子在所述半导体材料的生长过程中留在所述柱的每一个的顶部上。
4.根据前述权利要求中任何一项所述的方法，其中所述半导体层支撑在基板上。
5.根据权利要求4所述的方法，其中所述基板包括蓝宝石、硅和碳化硅的至少一个。
6.根据前述权利要求中任何一项所述的方法，其中所述半导体层由III族氮化物形成。
7.根据前述权利要求中任何一项所述的方法，其中所述第一掩模层由二氧化硅和氮化硅的至少一个形成。
8.根据前述权利要求中任何一项所述的方法，其中所述第二掩模层由金属形成。
9.根据权利要求8所述的方法，其中所述第二掩模层由镍形成。
10.根据前述权利要求中任何一项所述的方法，其中所述生长步骤在所述柱的底部周围留下间隙。
11.根据权利要求10所述的方法，其中相邻柱上生长的所述半导体材料在与所述基板分隔的位置处接触，从而该间隙留在该位置之下。
12.一种半导体器件，包括由半导体材料形成的柱阵列，其每一个柱包括由其顶部上形成的掩模材料形成的盖子以及在所述柱之间延伸且在所述柱的顶部之上以形成连续层的半导体材料。
13.根据权利要求12所述的半导体器件，根据权利要求1至11所述的任何一种方法形成。
14.根据权利要求12或权利要求13所述的半导体器件，其中至少90%的所述柱的直径小于1000nm。
15.根据权利要求12至14中任何一项所述的半导体器件，其中所述柱的高度至少为500nm。
16.一种制造半导体器件的方法，如本文参考附图所基本描述的。
17.一种半导体器件，如本文参考附图所基本描述的。
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