1278908 九、發明說明： % 【發明所屬之技術領域】 本發明是有關於一種形成奈米級粗化面的製程方法及 其應用。特別地’是指一種形成具有奈米柱（nan〇rocJ)結構 的粗化面的製程方法及其應用。 【先前技術】 一般的發光元件是如圖1中所示的一發光二極體 l(Light Emitting Diode ;簡稱 LED)，其包含一基材 11、分 別由該基材11向遠離該基材丨丨的方向依序疊設的一缓衝層 12(buffer layer) 一 η 型披覆層 I3(n-cladding layer)、一活 性發光層 14(active light-emitting layer)、一 p 型披覆層 15 ’以及一分別電連接該η型披覆層13和p型披覆層15的η 側電極16和ρ側電極17。其中，該緩衝層丨2、η型披覆層 13、活性發光層14，和ρ型披覆層15是由氮化鎵系材料製 成。 當该η側電極16和ρ側電極17被施以一適當電壓差 日守’邊活性發光層14中的電子電洞覆合而產生光。此種發 光二極體1中，由於氮化鎵系材料的介電係數（permittivity) 和折射係數（reflectivity)大，造成光行進至該ρ型披覆層15 和ρ側電極17、或該ρ型披覆層15和環境的空氣之間的介 面時，容易在介面產生全反射（如箭頭18所示之路徑），而 造成光取出（light extraction)效率偏低的現象。 【發明内容】 因此，本發明之目的在於提供一種形成奈米級粗化面 l2?89〇8 的製程方法。 於是’本發明製程方法包含下列步驟： (1)形成一遮罩層於一粗化層上。 (2)退火該遮罩層 於該粗化層上。 以形成複數間隔散佈的奈米 級遮罩部 的部分 (3)姓刻並移除該粗化層中未被該等遮罩部遮蔽 區域。 (4)移除該等遮罩部。 的在於提供利用1278908 IX. Description of the invention: % [Technical field to which the invention pertains] The present invention relates to a process for forming a nano-scale roughened surface and an application thereof. Specifically, it refers to a process for forming a roughened surface having a nano column (nan〇rocJ) structure and its application. [Prior Art] A general light-emitting element is a light-emitting diode (LED) as shown in FIG. 1 , which comprises a substrate 11 which is respectively separated from the substrate by the substrate 11 A buffer layer 12 in the direction of the 丨, an n-cladding layer, an active light-emitting layer, and a p-type cladding layer 15' and an n-side electrode 16 and a p-side electrode 17 which electrically connect the n-type cladding layer 13 and the p-type cladding layer 15, respectively. The buffer layer 丨2, the n-type cladding layer 13, the active light-emitting layer 14, and the p-type cladding layer 15 are made of a gallium nitride-based material. When the n-side electrode 16 and the p-side electrode 17 are applied with an appropriate voltage difference, the electron holes in the side active light-emitting layer 14 are laminated to generate light. In such a light-emitting diode 1, since the dielectric constant (remittivity) and the reflectance of the gallium nitride-based material are large, light is caused to travel to the p-type cladding layer 15 and the p-side electrode 17, or the ρ. When the interface between the type of cladding layer 15 and the ambient air is easy to generate total reflection at the interface (as indicated by the arrow 18), the light extraction efficiency is low. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a process for forming a nano-scale roughened surface l2?89〇8. Thus, the process of the present invention comprises the following steps: (1) forming a mask layer on a roughened layer. (2) annealing the mask layer on the roughened layer. The portion of the nano-shield portion that is formed by the plurality of spaced-apart masks is engraved and removed from the region of the roughened layer that is not covered by the mask portions. (4) Remove the masks. Is to provide utilization
本發明之另一目 成的發光元件。 前述之製程方法所製 於是，本發明具有奈米級粗化面的的發光元件包含— 第-半導體層、一可產生光的發光層、一第二半導體層、 一第一電極，及一第二電極。該第一半導體層具有一第一 側矛相反的第一側，該第二側區分有一第一連接部和一 第一連接部。該第一電極形成於該第一半導體層上的第一 連接部上。該發光層形成於該第一半導體層的第二連接部 上。亥弟一半導體層形成於該發光層上。該第二電極形成遽· 於該第二半導體層遠離該發光層的一側上。 _ 忒發光元件更包含複數奈米柱，該等奈米柱形成於下 列所述位置的其中之一：該第一半導體層的第一連接部上_ 、該第一半導體層的第一側上，及該第二半導體層遠離該 發光層的一側上。 另一方面’本發明具有奈米級粗化面的發光元件包含 具有一出光面的透明基材、一形成於該基材相反於該出 6 1278908 光=的一側面上的第一半導體層、一形成於該第一半導鞟 層遠離該基材的一側面上的第一電極、—形成於該第—半 導體層遠離該基材的一側面上的發光層、一形成於該發光 層遠離該第一半導體層的一側面上第二半導體層、一形成 方、》亥第一半導體層遠離該發光層的一側面上的第二電極， 及複數形成於該基材的出光面上的奈米柱。 本發明之功效能提供具有複數間隔散佈奈米柱的粗化 面的半‘體層或基材，以降低從該發光層所發出的光被該 粗化面反射的比例，並藉此增加該發光元件的亮度。 【實施方式】 本發明形成奈米級粗化面的製程方法包含下列步驟·· (1) 形成一遮罩層於一粗化層上。 (2) 退火該遮罩層以形成複數間隔散佈的奈米級遮罩部 於該粗化層上。 (3) 餘刻並移除該粗化層中未被該等遮罩部遮蔽的部分 區域。 (4) 移除該等遮罩部。 因此’未被移除的粗化層的部分區域形成複數凸起（凹 陷）的奈米柱，並藉此形成一具有該等奈米柱的粗化面的粗 化層。 適用於本發明之粗化層是選自於由下列材料所構成之 群組所製成：藍寶石（Sapphire)、氧化鋅（Zn〇)、石英 (Q tz)以石夕為主之半導體（Si-based semiconductor)、以 無為主之半導體（ΙΠ-V compound)，及以二六族為主之 1278908 半導體（II-VI compound；)。 在一較佳實施例中，該粗化層是由一以三五族半導體 為主的材料所製成之半導體層。該半導體層是一由氮化鎵 系（Gallium Nitride Series)材料所製成的半導體層。較佳地 ，該半導體層選自於由下列氮化鎵系材料所構成之群組·· 氮化蘇（GaN)、氮化銦鎵（GaInN)，及氮化鋁鎵㈧^Ν)。在 一具體實施例中，該氮化鎵系材料是氮化鎵。 在另一較佳實施例中，該粗化層是選自於由下列以透 明材料製成之基板所構成之群組··藍寶石、氧化鋅、氮化 鎵，和石英。在一具體實施例中，該粗化層是一藍寶石基 板0 在另一較佳實施例中，該粗化層是由一以二六族半導 體為主的材料所製成之半導體層。該二六族半導體材料是 選自於由下列材料所構成之群組：硫化辞和硒化辞 該遮罩層包括一形成於該粗化層上的鎳膜。較佳地， 該遮罩層更包括-介於該粗化層和錄膜之間的氮化 膜。 孕父侄地，該鎳膜的厚度落在 ^ 1八令 氮化矽膜的厚度落在2000至4000埃之範圍内v 適用於本發明之退火方式是―快速熱升溫退火㈣ Thermal Annfealing;簡稱RTA)。較佳地該快速熱升溫: 火的攝氏溫度從800度至_纟。在一具體實施例中， 快速熱升溫退火的溫度為85〇度。另一 力万面，適用於本— 明之蝕刻方式是一威庫鉍八式命將 4 I祸Ο式毛名活性化離子姓： 1278908 (Inductively Coupled Plasma 心⑽〜ι〇η 玢咖叩；簡輝 ICP-RIE)。 有關本發明的製程方法之前述及其他技術内容、特點 與功效，在以下配合參考圖式之四具體實施例的詳細說明 中，將可清楚的明白。 在本發明之具體實施例被詳細描述之前，要注意的是 ’在以下的說明書的内容中，類似的元件是以相同的編號 來表示。 <具體實施例一> 蒼閱圖2，本發日月形成奈米級粗化面的具體實施例一的 製程方法為： 百先，如步驟81所示，提供一粗化層21，該粗化層 21為一氮化鎵半導體層（以下稱為氮化鎵半導體層21)，且 ”亥氮化鎵半導體層21具有-大體上為—平面的粗化面2】8 。然後於該氮化鎵半導體層21的粗化面218上形成一遮罩 層22(步驟82)，該遮罩層22包括一形成於該氮化蘇半導體 層21的粗化面218上的氮化石夕膜221，及一形成於該氮化 矽膜221上的錦膜222。 接著，以快速熱升溫退火（RTA)方式退火該遮罩層22 以形成複數間隔散佈的奈米級遮罩部23於該氮化鎵半導體 層21上（步驟83)。每一遮罩部23具有一連接該氮化錄半導 奴層21的氮化矽膜231和一連接於該氮化矽膜上的鎳 膜232。接下來，以感應耦合式電漿活性化離子蝕刻 RIE)的方式，由該粗化面218向該氮化鎵半導體層2丨方向 1278908 J以私除该氮化鎵半導體層2丨中未被該等遮罩部23 这蔽的邛刀區域2丨丨（步驟84)。最後，再移除該等遮罩部 23(步驟 85)。 因此，未被移除的氮化鎵半導體層21的部分區域形成 複數凸起（凹陷）的奈米柱212,並藉此形成—具有該等奈米 柱212的粗化面218的氮化鎵半導體層21，即如圖2中步 驟85所示的氮化鎵半導體層21。 由於該氮化矽膜221和鎳膜222的接合，將使其介面 間的應力增大，而於熱製程中影響鎳原子的遷移，並增加 錄膜222的内聚力。因此該遮罩層22於退火後凝聚而形成 為該等奈米尺寸的遮罩部23。 圖3、4即說明了在該氮化矽膜221之厚度為3〇〇❹埃 ，且該鎳膜222之厚度分別為5〇、1〇〇、15〇埃，以85〇它 的快速熱升溫退火的溫度退火該遮罩層22時，該等奈米柱 212的外觀、尺寸和密度的狀況。其中，奈米柱Μ]的尺寸 是指該等奈米柱212的平均直徑，且圖3中蝕刻的條件為 ，氯氣和氬氣的流量分別為50和2〇 sccm ,蝕刻功率和基 板功率分別為400和l〇〇W，蝕刻腔工作壓力為5 ηιΤ〇η·， I虫刻時間為3 min.。 〈具體實施例二> 參照具體實施例一的圖2說明’本發明形成奈米級粗 化面的具體實施例二的製程方法，大體上是與該具體實施 例一相同，其不同處在於該遮罩層22。 該具體實施例二於該氮化鎵半導體層21上形成一遮罩 10 1278908 層22，該遮罩層22包括一形成於該半導體層2ι上的鎳臈 222。也就是說，該具體實施例二不存在該具體實施例一中 的氮化矽膜221。 圖5說明了該鎳膜222之厚度為15〇埃時，該等奈米 柱2Π的尺寸和密度的隨快速熱升溫退火（rta)的溫度而改 變的狀況。 <具體實施例三> 本發明形成奈米級粗化面的具體實施例三的製程方法 ’大體上S與該具體實施例-相同，其不同處在於該粗化 層2 1 I具體貫施例-中’該粗化層2丨為_氮化鎵半導體 層，而在本具體實施例三中，該粗化層21為一藍寶石基板 0 <具體實施例四> 本發明形成奈米級粗化面的具體實施例四的製程方法 ’大體上是與該具體實施例二相同，其不同處在於該粗化 層21。在具體實施例二中，該粗化層21為一氮化鎵半導體 層，而在本具體實施例四中，該粗化層21為一藍寶石基板 〇 一本發明製程方法之應用是一具有奈米柱粗化面的的發 光元件，纟包含一基材、一第一半導體層、一可產生光的 發光層、-第二半導體層、-第一電極、第二電極，及複 數奈米柱。 該基材具有-出％面。言亥第—半導體層具有一第一側 和—相反的第二側；其中’肖第—側連接該基材相反於該 l2789〇8 出光面的-側面，而該第二側則區分有一第一連接部和一 第二連接部。該第-電極形成於該第—半導體層的第一連 接=形成於該第一半導體層的第二連接部上 + w層形成於該發光層上。該第二電 該第二半導體層上。 成方； 該等奈米柱是如上述之製程方法所製成，並形成於下 列所述位置的其中之至少—者：豸第-半導體層的第一連 接部上、該第—半導體層的第—側上、該第二半導體層遠 離該發光層的-側上，及該基材的出光面。 在-較佳實施例中，該等奈米柱是形成於該第— 體層的第-連接部和該第二半導體層遠離該發光層的—側 上。較佳地’肖等奈米柱分別形成於該第—半導體層的第 一，上未被該第一電極遮蓋之區域，及該第二半導體 層遠離該發光層的-側上且未被該第二電極遮蓋之區域。 在另一較佳實施例中，該等奈米柱形成於該基材的出 光面上0 而在另-較佳實施例中，該等奈米柱形成於與該基材 分離後的第一半導體層的第一側上。 適用方、本發明應用之第一和第二半導體層分別可由一 以矽為主、一以二五族為主或一以二六族為主的半導體材 料所製成。 較佳地，該第二半導體層是選自於由下列以三五族半 導體為主的材料所構成之群組中的氮化鎵系化合物所製成 ••氮化鎵、氮化銦鎵，及氮化鋁鎵。在一較佳實施例中， 12 1278908 5亥第一和第二半導體層分別由氮化鎵所製成。而在一具體 芳知例中，該第一半導體層是由氮化鎵所製成之n型半導 月立層，该弟二半導體層是由氮化嫁所製成之P型半導體層 有關本發明製程方法的應用之前述及其他技術内容、 特點與功效，在以下配合參考圖式之四具體實施例的詳細 "兒明中，將可清楚的明白。而且在本發明之應用的具體實 知例被洋細描述之前’要注意的是，在以下的說明書的内 容中，類似的元件是以相同的編號來表示。 〈具體實施例五> 參閱圖6，本發明具有奈米級粗化面的發光元件是一發 光二極體3 ’其包含一基材31、一形成於該基材31上的緩 衝層37、一形成於該緩衝層37上的第一半導體層32。該 第一半導體層32具有-連接該緩衝層37的第一側321，和 -相反的第二側322。在該第二側322上區分有_第一側部 323 ^—第二側部324，且如圖6的方向所示，該第二側部 3 2 4高於該第一側部3 2 3。 〃該發光二極體3更包含—形成於該第_半導體層^的 第二側部324上且可產生光的發光層33，及一形成於該發 光層33上的第二半導體層34。該第二半導體層34具有一 遠離該發光層33的一電極側341。該第_半導體層u是一 氮化鎵所製成之η型半導體層。該第二半導體層h是一由 氮化鎵所製成之Ρ型半導體層。 其中’該第—半導體層32的第—側部323是利用本發 13 1278908 明之製程方法，以該第一半 一半導麟；π & μ 且g 為一粗化層，使該第 )的担化⑴側部323成為具有複數奈米柱（圖未示 =化面。同樣地’以該第二半_34為另— 使该弟二半導體；：^ 粗化面。 "、电極側341成為具有複數奈米柱的 該發光二極體3更包令一 从 形成方；该弟一側部323上的 弟一電極3 5，以及一形士 —斗； >成在泫龟極侧341上的第二電極36 〇 由方、^弟;-側部323和電極側34ι分別是奈米級的粗 面使仔由為光層33發出的光可被前述的粗化面（第一 側部323、電極側341)散射出去，因此降低了全反射的現象 ，進而增加該發光二極體3的光取出效率。 »該基材31為藍寶石基板，該緩衝層37為氮化錄。該 第一、第二半導體層32、34 ’和發光層33是使用金屬有機 化學氣相沈積法製備而成（meta】_gank ehemieai deposition’·簡稱M0CVD)。需說明的是，該緩衝層π主要 是使該第-半導體層32有良好的結晶成長，但非為必要。 <具體實施例六> ί閱圖7，本|s明形成奈米級粗化面的具體實施例六的 發光元件，大體上是與該具體實施例五的發光元件3相同 ’其不同處在於該第一側部323和電極側341。 在本具體實施例六中’該第一側部323區分有一電極 區3231和一粗化區3232。該第一電極35是形成於該電極 區3231上，該粗化區3232是一具有複數奈米柱（圖未示）之 14 1278908 粗化面。 該電極側341區分有一電極區3411和一粗化區3412。 该第二電極36是形成於該電極區3411上，該粗化區3412 疋一具有該等奈米柱之粗化面。 藉此，利用該第一側部323的粗化區3232和電極側 341的粗化區3412降低光被反射的量，並避免在該第一電 極35和δ亥第一半導體32之間的介面（即第一半導體上的 包極區3231)及該第二電極36和該第二半導體34之間的介 面（即第二半導體34上的電極區3412)產生高電阻，而造成 >μ面間的擴散電流current)減少和該發光層的 發光效率降低的現象。 <具體實施例七> “ ί閱圖8本叙明形成奈米級粗化面的具體實施例七的 發光元件’大體上是與該具體實施例五的發光元件3相同 ，其不同處在於本具體實施例七中： ⑴該第-側部323,和電極側341，不是一具有複數奈米 杈的粗化面。 (2)該基材31，具有—厚度，且該厚度小於該具體實施例 五中的基材31(見圖6)厚度。其中，該基材”，是以背面研 磨方式（back-side polish)來降低其厚度。 ()“材31 $具有一遠離該第一半導體層32(緩衝 層3 7)的出光面3 11的透明誃窨糞 乃凰資石基板，且該出光面311為 一具有奈米柱的粗化面。其中，該粗化面是以該透明藍寶 石基板為粗化層，並利用上述之製程方法而形成。 15 1278908 使用時是將此發光元件以覆晶封裝（flip_chip b〇nding)的 方式，使該第一和第二電極35、36電連接於電路板（圖未示 )而呈倒置的狀態，並使該發光層33產生的光經由該出光面 3 11離開該發光元件。 <具體實施例八> 麥閱圖9,本發明形成奈米級粗化面的具體實施例八的 發光元件，大體上是與該具體實施例七的發光元件相同， 其不同處在該基材31，、緩衝層37(見圖8)，和第一半導體 層32 〇 本具體實施例八不包含有該基材31，和該緩衝層37。且 該第-半導體層32的第-们21是—具有複數奈米柱的粗 化面。 其中，該基材3Γ和緩衝層37是利用雷射剝離技術 (laser lift-0ff technology)自發光元件中剝離，並使該第一半 導體層32裸露。再以該第一半導體層32為粗化層，並利 用本發明之製程方法使該第一半導體層32的第一側321成 為一粗化面。 值得一提的是，本發明形成奈米級粗化面的製程方法 除了應用於如上所述的該等發光二極體外，亦可應用於其 他發光元件或具有奈米結構的元件上，例如半導體雷射， 場發射顯示器等。 的利用了鎳膜和氮化矽 驟製成該等奈米級遮罩 另一方面，亦實際地教 歸納上述，本發明因前所未見 膜做為遮罩層，並以適當的退火步 部’以形成具有奈米柱的粗化面。 16 1278908 不方…亥寺發先兀件中的應用 咏 式例如分別以該第一半導 體層32、弟二半導體層34 干命 相仆层μ八w 土材3〗為粗化層，以在各該 粗化層上分別形成具有該等奈 ’、本柱的粗化面，達到降彳伞 反射及增加光取出效率的目的。 機低儿 准乂上所述者，僅為本發明开j成夺乎级^^ /(卜而&制4 m ^ „ 双不水級粗化面的製程 万凌及具應用之較佳實施例 a 奋 田不月匕以此限定本發明 貝ώ之乾圍’即大凡依本發主 — 甲明專利範圍及發明說明内 谷所作之簡單的等效變化盥 文化胖飾，皆仍屬本發明專利涵蓋 之範圍内。 【圖式簡單說明】 圖1是：習知發光二極體的側視結構示意圖； 圖2疋-流程圖’說明本發明形成奈米級粗化面的製 程方法之一具體實施例一； 疋掃彳田式電子顯微鏡（Scanning Electric sc〇py ’簡稱SEM)的局部放大示意圖，說明該具體實 也幻中 具有複數間隔散佈奈米柱粗化面的氮化鎵半 導體層； 圖4疋一1測數據圖，說明該具體實施例一中，一鎳 膜的厚度影響該等奈米柱尺寸和密度的狀況； 圖5是一量測數據圖，說明本發明之一具體實施例二 中，複數奈米柱的尺寸和密度隨快速熱升溫退火（rta)的溫 度而改變的狀況； 圖6是一發光元件的側視結構示意圖，說明本發明形 成奈米級粗化面之應用的一具體實施例三； 17 1278908 圖7是一發光元件的側視結構示意圖，說明本發明的 一具體實施例六； 圖8是一發光元件的側視結構示意圖，說明本發明的 一具體實施例七；及 圖9是一發光元件的側視結構示意圖，說明本發明的 一具體實施例八。Another object of the invention is a light-emitting element. According to the above process method, the light-emitting element having a nano-roughened surface comprises a first-semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, and a first Two electrodes. The first semiconductor layer has a first side opposite to the first side lance, and the second side has a first connecting portion and a first connecting portion. The first electrode is formed on the first connection portion on the first semiconductor layer. The light emitting layer is formed on the second connection portion of the first semiconductor layer. A semiconductor layer is formed on the light-emitting layer. The second electrode is formed on a side of the second semiconductor layer away from the light emitting layer. The 忒 illuminating element further comprises a plurality of nano-pillars formed on one of the following positions: on the first connection portion of the first semiconductor layer, on the first side of the first semiconductor layer And a side of the second semiconductor layer remote from the light emitting layer. On the other hand, the light-emitting element having a nano-roughened surface of the present invention comprises a transparent substrate having a light-emitting surface, and a first semiconductor layer formed on a side of the substrate opposite to the light of the light. a first electrode formed on a side of the first semi-conductive layer away from the substrate, a light-emitting layer formed on a side of the first semiconductor layer away from the substrate, and a light-emitting layer formed on the light-emitting layer a second semiconductor layer on one side of the first semiconductor layer, a second electrode on a side of the first semiconductor layer away from the light-emitting layer, and a plurality of layers formed on the light-emitting surface of the substrate Rice column. The effect of the present invention is to provide a semi-body layer or substrate having a plurality of spaced apart roughened faces of the nano-pillars to reduce the proportion of light emitted from the luminescent layer being reflected by the roughened surface, thereby increasing the luminescence The brightness of the component. [Embodiment] The process for forming a nano-scale roughened surface of the present invention comprises the following steps: (1) forming a mask layer on a roughened layer. (2) Annealing the mask layer to form a plurality of spaced-apart nano-mask portions on the roughened layer. (3) Residing and removing portions of the roughened layer that are not obscured by the masks. (4) Remove the masks. Thus, the partial regions of the unremoved roughened layer form a plurality of raised (recessed) nanopillars, and thereby form a roughened layer having roughened faces of the nanopillars. The roughened layer suitable for use in the present invention is selected from the group consisting of sapphire, zinc oxide (Zn), and quartz (Q tz). -based semiconductor, non-dominant semiconductor (ΙΠ-V compound), and 2278908 semiconductor (II-VI compound;). In a preferred embodiment, the roughened layer is a semiconductor layer made of a material mainly composed of a tri-five semiconductor. The semiconductor layer is a semiconductor layer made of a gallium nitride (Gallium Nitride Series) material. Preferably, the semiconductor layer is selected from the group consisting of gallium nitride-based materials, GaN, indium gallium nitride (GaInN), and aluminum gallium nitride (A). In a specific embodiment, the gallium nitride based material is gallium nitride. In another preferred embodiment, the roughened layer is selected from the group consisting of sapphire, zinc oxide, gallium nitride, and quartz. In one embodiment, the roughened layer is a sapphire substrate. In another preferred embodiment, the roughened layer is a semiconductor layer made of a material based on a hexa-group semiconductor. The hexa-group semiconductor material is selected from the group consisting of sulphide and selenization. The mask layer includes a nickel film formed on the rough layer. Preferably, the mask layer further comprises a nitride film interposed between the rough layer and the recording film. The thickness of the nickel film falls within the range of 2,000 to 4,000 angstroms. The annealing method suitable for the present invention is "rapid thermal annealing" (4) Thermal Annfealing; RTA). Preferably, the rapid thermal rise: the Celsius temperature of the fire ranges from 800 degrees to _纟. In one embodiment, the temperature of the rapid thermal annealing is 85 degrees. Another powerful method, suitable for this - the way of etching is a weiku 铋 eight-style life will be 4 I Ο Ο 毛 毛 活性 活性 活性 : : 1278908 (Inductively Coupled Plasma heart (10) ~ ι〇η 玢 叩 叩; Jane Hui ICP-RIE). The above and other technical contents, features, and advantages of the process of the present invention will be apparent from the following detailed description of the embodiments of FIG. Before the specific embodiments of the present invention are described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. <Specific Embodiment 1> The method of manufacturing the first embodiment of the present invention is as follows: a first step, as shown in step 81, a roughening layer 21 is provided. The roughened layer 21 is a gallium nitride semiconductor layer (hereinafter referred to as a gallium nitride semiconductor layer 21), and the gallium nitride semiconductor layer 21 has a substantially-planar roughened surface 2 8 . A mask layer 22 is formed on the roughened surface 218 of the gallium nitride semiconductor layer 21 (step 82). The mask layer 22 includes a nitride layer formed on the roughened surface 218 of the silicon nitride semiconductor layer 21. a film 221, and a film 222 formed on the tantalum nitride film 221. Next, the mask layer 22 is annealed by rapid thermal annealing (RTA) to form a plurality of spaced-apart nano-shield portions 23 On the gallium nitride semiconductor layer 21 (step 83), each of the mask portions 23 has a tantalum nitride film 231 connected to the nitride recording semiconductor layer 21 and a nickel film connected to the tantalum nitride film. 232. Next, in the manner of inductively coupled plasma-activated ion etching (RIE), the roughened surface 218 is oriented toward the gallium nitride semiconductor layer 1278908 J cleaves the blade region 2丨丨 of the gallium nitride semiconductor layer 2 that is not covered by the mask portions 23 (step 84). Finally, the mask portions 23 are removed (step 85). Therefore, a portion of the region of the gallium nitride semiconductor layer 21 that has not been removed forms a plurality of raised (recessed) nanopillars 212, and thereby forms a nitrogen having a roughened surface 218 of the nanopillars 212. The gallium semiconductor layer 21, that is, the gallium nitride semiconductor layer 21 as shown in step 85 of Fig. 2. Since the tantalum nitride film 221 and the nickel film 222 are bonded, the stress between the interfaces is increased, and the heat is increased. The process affects the migration of nickel atoms and increases the cohesive force of the film 222. Therefore, the mask layer 22 is agglomerated after annealing to form the mask portion 23 of the nanometer size. Figures 3 and 4 illustrate the nitrogen. The thickness of the ruthenium film 221 is 3 〇〇❹, and the thickness of the nickel film 222 is 5 〇, 1 〇〇, 15 〇, respectively, and the mask layer 22 is annealed at a temperature of 85 〇 its rapid thermal annealing. The appearance, size and density of the nano-pillars 212. The size of the nano-pillars refers to the average straightness of the nano-pillars 212. The etching conditions in FIG. 3 are that the flow rates of chlorine gas and argon gas are 50 and 2 〇 sccm, the etching power and the substrate power are 400 and 10 W, respectively, and the working pressure of the etching chamber is 5 ηιΤ〇η·, I. The insect cutting time is 3 min. <Specific embodiment 2> Referring to FIG. 2 of the specific embodiment 1, the process method of the second embodiment of the present invention for forming a nano-scale roughened surface is described, which is substantially the same as the specific implementation. In the same manner, the difference is in the mask layer 22. The second embodiment forms a mask 10 1278908 layer 22 on the gallium nitride semiconductor layer 21, and the mask layer 22 includes a layer formed on the semiconductor layer 2 Nickel 222 on the top. That is, the specific example 2 does not have the tantalum nitride film 221 in the first embodiment. Fig. 5 illustrates the state in which the size and density of the nano-pillars 2 随 vary with the temperature of rapid thermal annealing (rta) when the thickness of the nickel film 222 is 15 angstroms. <Specific Embodiment 3> The process method of the third embodiment of the present invention for forming a nano-scale roughened surface is substantially the same as the specific embodiment, except that the roughened layer 2 1 I In the embodiment - the 'the roughened layer 2' is a gallium nitride semiconductor layer, and in the third embodiment, the roughened layer 21 is a sapphire substrate 0 <Detailed Embodiment 4> The process method of the fourth embodiment of the m-grade roughened surface is substantially the same as that of the second embodiment, except that the roughened layer 21 is different. In the second embodiment, the roughening layer 21 is a gallium nitride semiconductor layer, and in the fourth embodiment, the roughening layer 21 is a sapphire substrate. The application method of the invention is a a light-emitting element of a rice-column roughened surface, comprising: a substrate, a first semiconductor layer, a light-emitting layer capable of generating light, a second semiconductor layer, a first electrode, a second electrode, and a plurality of nano columns . The substrate has a % face. The semiconductor layer has a first side and an opposite second side; wherein the 'Shaw side-side is connected to the substrate opposite to the side surface of the l2789〇8 light-emitting surface, and the second side is divided into a first side a connecting portion and a second connecting portion. The first electrode is formed on the first semiconductor layer of the first semiconductor layer = formed on the second connection portion of the first semiconductor layer + the w layer is formed on the light emitting layer. The second electricity is on the second semiconductor layer. The nano-pillars are formed by the above-described process method and formed at least at least one of the following positions: the first connection portion of the first semiconductor layer, and the first semiconductor layer On the first side, the second semiconductor layer is away from the side of the light-emitting layer, and the light-emitting surface of the substrate. In a preferred embodiment, the nano-pillars are formed on a side of the first connection portion of the first body layer and the second semiconductor layer away from the light-emitting layer. Preferably, the "Xiao et al. column" is formed on the first portion of the first semiconductor layer, the region not covered by the first electrode, and the second semiconductor layer is away from the side of the light-emitting layer and is not The area covered by the second electrode. In another preferred embodiment, the nano columns are formed on the light exiting surface of the substrate. In another preferred embodiment, the nano columns are formed in the first separated from the substrate. On the first side of the semiconductor layer. The first and second semiconductor layers to which the applicator and the present invention are applied may each be made of a semiconductor material mainly composed of bismuth, mainly composed of two or five groups or one group of two or six groups. Preferably, the second semiconductor layer is made of a gallium nitride-based compound selected from the group consisting of the following three-five semiconductor-based materials: • gallium nitride, indium gallium nitride, And aluminum gallium nitride. In a preferred embodiment, 12 1278908 5H first and second semiconductor layers are respectively made of gallium nitride. In a specific example, the first semiconductor layer is an n-type semi-conducting moon layer made of gallium nitride, and the second semiconductor layer is made of a P-type semiconductor layer made of nitrided marsha. The foregoing and other technical contents, features, and utilities of the application of the process method of the present invention will be apparent from the following detailed description of the embodiments of the present invention. Further, before the specific embodiments of the application of the present invention are described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. <Embodiment 5> Referring to Fig. 6, the light-emitting element having a nano-roughened surface of the present invention is a light-emitting diode 3' which comprises a substrate 31 and a buffer layer 37 formed on the substrate 31. A first semiconductor layer 32 formed on the buffer layer 37. The first semiconductor layer 32 has a first side 321 that connects the buffer layer 37, and a second side 322 that is opposite. A first side portion 323 ^ - a second side portion 324 is distinguished on the second side 322, and the second side portion 3 2 4 is higher than the first side portion 3 2 3 as shown in the direction of FIG. . The light-emitting diode 3 further includes a light-emitting layer 33 formed on the second side portion 324 of the first semiconductor layer and capable of generating light, and a second semiconductor layer 34 formed on the light-emitting layer 33. The second semiconductor layer 34 has an electrode side 341 away from the light-emitting layer 33. The first semiconductor layer u is an n-type semiconductor layer made of gallium nitride. The second semiconductor layer h is a bismuth type semiconductor layer made of gallium nitride. Wherein the first side portion 323 of the first semiconductor layer 32 is a process method according to the method of the present invention, wherein the first half of the lead is used; π & μ and g is a roughened layer to make the first The side portion 323 of the burden (1) has a plurality of nano-pillars (not shown = the same surface; the same as the second half _34 is the other - the second semiconductor;: ^ roughened surface. ", electrode The side 341 becomes a light-emitting diode 3 having a plurality of nano-pillars, and further comprises a slave-forming side; the brother-side electrode 3 5 on the side of the younger brother 323, and a shape-fighting bucket; > The second electrode 36 on the pole side 341 is made up of a square, a side surface 323 and an electrode side 34ι, respectively, which are nano-scale rough surfaces, so that the light emitted by the light layer 33 can be roughened by the aforementioned ( The first side portion 323 and the electrode side 341) are scattered, thereby reducing the phenomenon of total reflection, thereby increasing the light extraction efficiency of the light emitting diode 3. The substrate 31 is a sapphire substrate, and the buffer layer 37 is nitrided. The first and second semiconductor layers 32, 34' and the light-emitting layer 33 are prepared by metal organic chemical vapor deposition (meta)_gank Ehemieai deposition' (M0CVD for short). It should be noted that the buffer layer π mainly causes good crystal growth of the first semiconductor layer 32, but is not necessary. [Embodiment 6] The light-emitting element of the sixth embodiment which forms the nano-roughened surface is substantially the same as the light-emitting element 3 of the fifth embodiment. The difference lies in the first side portion 323 and the electrode side 341. In the sixth embodiment, the first side portion 323 is divided into an electrode region 3231 and a roughening region 3232. The first electrode 35 is formed on the electrode region 3231, and the roughening region 3232 is a plurality of 14 1278908 roughened surface of the rice column (not shown). The electrode side 341 is divided into an electrode region 3411 and a roughening region 3412. The second electrode 36 is formed on the electrode region 3411, and the roughening region 3412 A roughened surface having the nano-pillars. Thereby, the roughened region 3232 of the first side portion 323 and the roughened region 3412 of the electrode side 341 are used to reduce the amount of light reflected, and to avoid the first electrode Interface between 35 and δH first semiconductor 32 (ie, the first semiconductor on the first semiconductor) The region 3231) and the interface between the second electrode 36 and the second semiconductor 34 (i.e., the electrode region 3412 on the second semiconductor 34) generate a high resistance, causing a decrease in the diffusion current current between the > A phenomenon in which the luminous efficiency of the light-emitting layer is lowered. <Detailed Embodiment 7> "Embodiment of the light-emitting element of the seventh embodiment which forms the nano-roughened surface is substantially the same as that of the light-emitting element 3 of the fifth embodiment, and the difference is In the seventh embodiment: (1) the first side portion 323, and the electrode side 341 are not a roughened surface having a plurality of nanometers. (2) the substrate 31 has a thickness of less than the thickness. The thickness of the substrate 31 (see Fig. 6) in the fifth embodiment, wherein the substrate is reduced in thickness by a back-side polish. () "Material 31 $ has a transparent ruthenium ruthenium substrate away from the light-emitting surface 3 11 of the first semiconductor layer 32 (buffer layer 37), and the light-emitting surface 311 is a thick nano-column The roughened surface is formed by using the transparent sapphire substrate as a rough layer and using the above-mentioned process method. 15 1278908 In use, the light-emitting element is flip-chip packaged (flip_chip b〇nding) The first and second electrodes 35, 36 are electrically connected to a circuit board (not shown) to be in an inverted state, and the light generated by the light-emitting layer 33 is separated from the light-emitting element via the light-emitting surface 31. EMBODIMENT 8] The light-emitting element of the eighth embodiment of the present invention forming a nano-roughened surface is substantially the same as the light-emitting element of the seventh embodiment, and the difference is in the substrate. 31, a buffer layer 37 (see FIG. 8), and a first semiconductor layer 32. The eighth embodiment does not include the substrate 31, and the buffer layer 37. And the first semiconductor layer 32 Yes - a roughened surface having a plurality of nano-pillars, wherein the substrate 3 and the buffer layer 37 are utilized The laser lift-off technology (laser lift-0ff technology) is peeled off from the light-emitting element, and the first semiconductor layer 32 is exposed. The first semiconductor layer 32 is further used as a roughened layer, and the first method is used to make the first method. The first side 321 of the semiconductor layer 32 is a roughened surface. It is worth mentioning that the method for forming the nano-scale roughened surface of the present invention can be applied not only to the above-mentioned light-emitting diodes but also to the same. Other light-emitting elements or elements having a nanostructure, such as semiconductor lasers, field emission displays, etc., which utilize nickel films and tantalum nitride to form such nano-level masks, on the other hand, actually teach In the above, the present invention uses a film as a mask layer and uses an appropriate annealing step to form a roughened surface having a nano column. 16 1278908 No.... Application in the ancestors of the hai Temple For example, the first semiconductor layer 32 and the second semiconductor layer 34 are respectively a rough layer, so as to form a column on each of the rough layers. Roughening surface to achieve parachute reflection The purpose of adding light to take out the efficiency. The machine is only mentioned in the above paragraph, and only the invention is in the order of ^^ / (Bu and & 4 m ^ „ double non-water grade roughening surface process 10,000 The preferred embodiment of Ling and the application of a. Fen Tian Wu Yue 匕 匕 限定 限定 匕 匕 匕 匕 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 限定 即 即 即 即 即 即 即 即 即 即Cultural fat ornaments are still covered by the patent of the present invention. [Simplified illustration of the drawings] Fig. 1 is a schematic side view of a conventional light-emitting diode; Figure 2 - Flowchart ' illustrates the formation of nanometers of the present invention One of the processing methods of the grade roughening surface is a specific example 1; a partial enlarged schematic view of a scanning electron microscope (Scanning Electric sc〇py ' SEM), illustrating that the specific real illusion has a plurality of spaced apart nano columns The roughened surface of the gallium nitride semiconductor layer; FIG. 4 is a measured data diagram illustrating the thickness of a nickel film affecting the size and density of the nano column in the first embodiment; FIG. 5 is a measurement a data diagram illustrating one embodiment of the present invention, The size and density of the number of nano columns vary with the temperature of the rapid thermal annealing (rta); FIG. 6 is a side view of a light-emitting element, illustrating a specific application of the present invention to form a nano-scale roughened surface. Embodiment 3; 17 1278908 FIG. 7 is a side view of a light-emitting element, illustrating a sixth embodiment of the present invention; FIG. 8 is a side view of a light-emitting element, illustrating a seventh embodiment of the present invention; And Fig. 9 is a side elevational view showing the structure of a light-emitting element, illustrating an eighth embodiment of the present invention.
18 1278908 【主要元件符號說明】 1… …·…發光二極體 3 <"<. …發光二極體‘ 11 ……基材 3卜… …基材 1 2 *< ......緩衝層 3 11… …出光面 13 ‘* ι……η型披覆層 3 2 <…… …第一半導體層 14， •—…活性發光層 321 -- …第一側 15 - ♦ ρ型披覆層 3 2 2 * … …第二側 16- .......η側電極 323 …第一側部 17… 1……ρ側電極 323 1 … …電極區 18… .......光行進路線 3232 … …粗化區 21 * .......粗化層 324 .… …第二側部 211 •……未遮蔽區域 3 3...... …發光層 212 —…奈米柱 3 4…… …第二半導體層 218 ‘ ...... κ粗化面 341，… …電極側 22… ……遮罩層 3411 … …電極區 221 ……氮化矽膜 3412*- …粗化區 222， ……♦鎳膜 3 5…… …第一電極 23… ......遮罩部 36........ …第二電極 231、 .......氮化$夕膜 3 7...... …緩衝層 232 . .......鎳膜 81〜85 ‘ …步驟 1918 1278908 [Explanation of main component symbols] 1... ...·...Light-emitting diode 3 <"<. ...Light-emitting diode ' 11 ......Substrate 3 Bu...Substrate 1 2 *< ... ... buffer layer 3 11 ... light-emitting surface 13 '* ι... η-type cladding layer 3 2 <...... first semiconductor layer 14, ... - active light-emitting layer 321 - ... first side 15 - ♦ p-type cladding layer 3 2 2 * ... second side 16 - ... η side electrode 323 ... first side portion 17 ... 1 ... ρ side electrode 323 1 ... electrode area 18 ... . ...light travel route 3232 ... roughening zone 21 * ....... roughening layer 324 .... ... second side portion 211 ... ... unmasked area 3 3 ... ... luminescent layer 212 - ... nano column 3 4 ... ... second semiconductor layer 218 '... κ roughened surface 341, ... electrode side 22... ...... mask layer 3411 ... electrode area 221 ...矽 nitride film 3412*-...roughening zone 222, ... ♦ nickel film 3 5 ... first electrode 23... ...... mask part 36........ ... second Electrode 231, . . . nitriding film 3 7 ... ... buffer layer 232 . . . nickel film 81 ~ 85 ' ... step 1 9