GB2520687A - Semiconductor devices and fabrication methods - Google Patents

Semiconductor devices and fabrication methods Download PDF

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GB2520687A
GB2520687A GB1320925.9A GB201320925A GB2520687A GB 2520687 A GB2520687 A GB 2520687A GB 201320925 A GB201320925 A GB 201320925A GB 2520687 A GB2520687 A GB 2520687A
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layer
mask
pillars
semiconductor
islands
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GB201320925D0 (en
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Tao Wang
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Seren Photonics Ltd
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Seren Photonics Ltd
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Priority to GB1320925.9A priority Critical patent/GB2520687A/en
Publication of GB201320925D0 publication Critical patent/GB201320925D0/en
Priority to EP14803236.0A priority patent/EP3075002A1/en
Priority to PCT/GB2014/053496 priority patent/WO2015079222A1/en
Priority to CN201480073098.1A priority patent/CN105917444A/en
Publication of GB2520687A publication Critical patent/GB2520687A/en
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02367—Substrates
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    • H01L21/02612—Formation types
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region

Abstract

A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer 210; forming a first mask layer 220 over the semiconductor layer 210; forming a metal second mask layer 230 over the first mask layer 220; annealing the second mask layer 230 to form islands 233; forming a second metal layer over the islands 233; annealing the second metal layer thereby to increase the size of the islands 233; and etching through the first mask layer 220 and the semiconductor layer 210 using the islands 233 as a mask to form an array of pillars 211. Wherein the islands 233 may be removed after forming the pillars 211. A semiconductor material may then be grown by epitaxial lateral over growth (ELOG) from the sidewalls of the pillars, around the remaining first mask caps 221 such that any lateral strain in the pillar 211 material due to lattice mismatch with the support substrate 205 is not transferred into the semiconductor material grown on the sides of the pillars 211.

Description

SEMICONDUCTOR DEVICES AND FABRICATION METHODS
The invention relates to semiconductor devices and methods of making semiconductor devices. In particular it relates to the formation of nano-scale columns in semiconductor devices. These nano-scale column structures have application, for example, in the production of light emitting diodes (LEDs), as well in the growth of semiconductor devices with high quahtv crystal structure. These high quality crystal structure devices can themsdves be used, for exampk. in the formation of light emitting diodes and solid state lasers.
Currently. there are three main approaches for the fabrication of white light emitting diodes (LEDs) needed for solid state lighting: (I) a package of three LED chips each emitting at a different wavelength (red, green and blue, respectively); (2) a combination of a blue (460 nm) LED and a yellow phosphor pumped by blue light IS from the LED; (3) a single chip emitting UV light which is absorbed in the LED package by three phosphors (red, green and blue) and reemitted as a broad spectrum of white light. For the 1st and 2nd approaches, the key components arc blue/green LEDs, both of which are based on InGaN material systems. For the 3 approach. ultraviolet (U\') emitters with high performance arc required.
Advanced growth technologies for InGaN based and A1GaN-based devices have been well established, but are generally based on c-face sapphire substrates. This polar orientation results in intense buflt-in dectric field due to piezodectric effects and the devices suffer from reduced overlap between the electron and hole wave functions and long radiative recombination times. and thus low quantum efficiency. This is the so-cafled quantum confined Stark effect (QCSE). In particular. when the emitters move towards the green spectral region, much higher InN fractions are required and the internal electric fields generally become extremely high. This presents a major obstacle to achieving InGaN-based enutters (in particular, green emitter) with high performance. The same problem arises for A1GaN-based UV emitters, but it is even Homoepitaxial growth is ideal for Ill-nitride based optoclcctronic devices. However.
due to affordability reasons, growth on foreign substrate such as sapphire, SiC.
silicon, etc., stifl remains a main approach for growth of Ill-nitrides, Such "large lattice-mismatched heteroepitaxv" leads to a very high density of dislocations, This will cause a significant reduction in optical performance of 111-nitride optoelectronics, such as InGaN-based near UV/blue/green emitters and A1GaN/GaN-based UV emitters. The dislocation issue becomes more pronounced in A1GaN/GaN-based UV emitters than InGaN -based emitters, as optical performance of A1GaN/GaN-based UV emitters is more sensitive to dislocations than InGaN-based emitters.
The two issues (QCSE and dislocations) statcd above are two fundamental obstacles in further improving optical performance of 111-nitride-based optoelectronies.
One of the most promising approaches to counteract the negative effects of the QCSE is growth along non-polar or semi-polar orientations, as confirmcd theoretically and experimentally. Another maj or advantage of non-polar or semi-polar 111-nitride emitters is that they can emit polarized light, Liquid-crystal displays (LCDs) require polarized illumination and current LCDs require an extra polarizing element to achieve this. The low transmission efficiency of the polarizer leads to lower efficiency and a device emitting polarized light is advantageous.
Very recently 111-nitride growth on non-polar or semi-polar planes has led to major breakthroughs for green emitters. However, a major challenge has also been exposed, i.e., these non-polar or semi-polar 111-nitride emitters with high performance are exclusively grown on extremely expensive GaN substrates, i.e. using the homoepitaxial growth approach. Unfortunately, non-polar or semi-polar GaN substrates are very small and extremely expensive. In addition, being highly non-uniform also makes them unsuitable for mass production.
Therefore, it is desirable to obtain non-polar or semi-polar GaN with high crystal template on sapphire substrate with any size (such as up to 12 inch) for further growth of InGaN-based or AIGaN-based device structures, So far, conventional epitaxial lateral overgrowth (ELOG) has been employed in improving crystal quality of non-polar or semi-polar GaN on sapphire, The ELOG technique is based on selective area growth. Typically, a standard GaN layer is first grown on sapphire by metalorganie vapour phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) or hydride vapour phase epitaxy (HyPE), and the surface is then coated ex-situ with a dielectric mask such as Si02 or Si3N4, The mask is then patterned into micron-scale stripes (not nanometer scale) using standard photolithography, The masked sample is then used as a template for further growth by MOVFE or MBE or HVPE, The re-growth starts on the exposed GaN in the mask window areas, as the GaN does not grow on top of the dielectric mask. When the growing face reaches above the top of the mask the GaN regrowth extends laterally over the striped mask, and can eventually coalesces to form a smooth surface. The dislocations in the crystal structure originating under the mask stripes, caused by the arge lattice mismatch between sapphire and GaN, are effectively blocked. Due to the limits of standard photolithography, the mask-stripe width and wing width can not be further decreased down to nanometer scale.
Therefore, normally, a flat surface cannot be obtained till the overgrown layer has reached more than 10 -20 m thick. In addition, it is difficult to apply such approach in overgrowth of AIGaN, as AIGaN lateral growth rate is generafly much smaller than GaN lateral growth rate, leading to a very slow coalescence.
IS Therefore, the conventiona' ELOG approach is very complicated, and thus leads to much higher extra cost.
The invention provides a method of making a semiconductor device. The method may comprise providing a semiconductor wafer having a semiconductor layer. The method may comprise foming a first mask ayer over the semiconductor layer. The method may comprise forming a metal second mask layer over the first mask layer. The method may comprise annealing or otherwise applying or modifying the second mask layer to form islands, The method may comprise etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.
The method may further comprise forming a second metal layer over the islands and anneahng the second metal layer thereby to increase the size of the is'ands, The second metal layer may be formed after the second mask layer (which can be considered as a first metal layer). has been annealed or otherwise modified to form islands. The second metal layer may be annealed before the etching step.
The second metal layer may be of the same material as the second mask layer. For example both may be of nickel.
The metal coating and annealing step may be repeated a third time, or indeed ally number of times as required.
The array of pillars may be used in the formation of an LED as described in W02010/146390, Ahernativdy. the method further comprises growing semiconductor material between the pillars and then over the tops of the pillars.
The method may comprise removing the islands before growing the semiconductor material.
A cap formed from one of the mask layers may be left on the top of each of the pillars dlLring the growing of the semiconductor material. This may be the first mask layer.
IS
The semiconductor layer may be supported on a substrate. The substrate may comprise at least one of sapphire, silicon and silicon carbide, The semiconductor material which is grown onto the pillars may be the same material as that making up the semiconductor layer (and hence the pillars), or it may be a different material.
The semiconductor layer may be formed of a group IT! nitride. For example it may be formed of gallium nitride, indium gallium nitride, aluminium gallium nitride, or aluminium nitride. The nitride may be semi-polar or non-polar. For example semi-polar GaN is a suitable, as is non-polar GaN.
The first mask layer may be formed of at least one of silicon dioxide and silicon nitride.
The second mask layer may be formed of a metal, or two different metals, For example the first metal layer may comprise nickel, chromium, tungsten or titanium, or an alloy of two or more of those metals. Similarly the second metal layer may comprise nickel. chromium, tungsten or titanium, or an alloy of two or more of those metals. The second metal layer may comprise the same met& or aHoy as the first metal layer, or it may be a different metal or alloy.
The method may further comprise removing the support substrate. This may include removing a part. e.g. the lowest part, of the pillars.
The present invention further provides a semiconductor device comprising an array of piflars each including a main column formed of semiconductor material, and each including a cap formed of a mask material formed on its top, and a semiconductor material extending between the pillars and over the top of the pillars, and over the caps, to form a continuous layer. The two semiconductor materials may be the same, or they may be different. The pillar array may comprise piflars aH having diameters less than lSOOnm and preferably less than l000nm,. The pillars arc also preferably at least 300nm in diameter. In general there will be irregularity in the diameters such IS that some of the pillars are larger than others, and the cross sections are not circular, and their width is not constant a'ong their ength, The diameter of the pillars may therefore be measured as the mean (over all pillars) of the minimum diameter (i.e. measured in the direction iii which the pillar is narrowest) at the top of the pillars. The height of the pillars is preferably at least SOOnm. more preferably at least l000nm.
The pillars may be all of substantially the same height. The mask material may be a metal.
At least some of the nano-pillars may have cavities around their bases.
The present invention is based on a so-called self-organised nano-mask approach, optionafly with subsequent overgrowth. The fabrication of the self-organised nano-mask is very simple, and does not require extra photolithography. The overgrown layer, when present, can be relatively thin compared to known ELOG methods, but the obtained crystal quality is equivalent to or better than that obtained by the conventional ELOG. Therefore, the cost can be significantly reduced. In addition, the approach can be extended for growth of any ITI-nitrides including polar, non-polar, or semi-polar.
The method or device may further comprise, in any combination, any one or more of the steps or features of the preferred embodiments of the invention, which wifl now be described, by way of example only, with reference to the accompanying drawings in which: Figures la to th show the steps in the formation of a device according an embodiment of the invention; Figure 2 is an image of a known nano-rod array; Figure 3 is an image of a nano-rod array formed as part of a process according to the method of Figures Ia to lh. and a standard sample of semi-polar GaN; and Figure 4 is a graph showing showing the full width at half maximum for the x-ray rocking curve as a function of azimuth angle of the incident x-ray beam, IS for a sample (semi-polar GaN) formed using the nano-rod array of Figure 3, Referring to Figure la, the first step of fabricating the device is providing a suitable semiconductor wafer 201. The wafer 201 is conventional and is made up of a substrate 205, which in this case comprises a layer of sapphire, over which is a semiconductor ayer 210 formed of gallium nitride (GaN). In this cases the GaN is semi-polar GaN, but non-polar GaN can equally be used. Other materials can be used.
For example the substrate may be silicon or silicon carbide. The semiconductor may be another suitabk material, for example another group III nitride such as indium gallium nitride (mOaN), aluminium gallium nitride (A1GaN) or aluminium nitride (A1N) A first mask layer 220 is provided over the semiconductor layer 210, for examplethe first mask layer 220 is formed of silicon dioxidc, although there are suitable alternative materials for this layer e.g. silicon nitride, and is deposited at an approximately uniform thickness of 200 nanometres. A thicker layer, for example up to 600nm. can be used. This can be by plasma-enhanced chemical vapour deposition (PECYD) or thermal evaporation or sputtering or electron beam evaporation.
A second mask layer 230. comprising a metal which in this case is nickel, is provided over the first mask layer 220, This can be by thermal evaporation or sputtering or electron beam evaporation. In this step, a nickel layer of approximately uniform thickness in the range S to 50 nanometres. preferably 5 to 2Snm, is formed and then annealed lLnder flowing nitrogen (N2) at a temperature in the range 600 to 900, preferably 700 to 850 degrees Celsius. The duration of the annealing process is between 1 and 10 minutes. resulting in formation from the nickel layer of a layer 230 comprising self-assembled nickel islands 231 distributed irregularly over the first mask ayer 220 as shown in Figure lb. Each of the nickel islands 23 I covers a respective, approximately circular, area of the upper surface of first mask layer 220 which is, typically, no less than 100 nanometres in diameter and no more than 1500 nanometres in diameter.
In order to increase the size of the nickel is'ands. a second thin nickel film is deposited on the top of the formed nickel islands, which covers both the nickel islands 231 and the exposed areas of the first mask layer 220 between the nickel IS islands. The second nickel film is then annealed at a high temperature, generally in the same temperature range and time period range as the annealing of the first nickel layer. The result of this is that the second layer of nickel 232 collects on the surface, i.e. the sides and the top, of the nickel islands 231, thereby increasing the size of the nickel islands to form larger islands 233. Generally no new nickel islands are formed in the second coating and annealing step. Of course, the second deposited nickel film and the time and temperature at which it is annealed can be different to those done in the first time, respectively. Furthermore, the nickel-deposition and the subsequent anneahng processes can be repeated one or more further times to increase the size of the islands to the required size to act as the second mask layer.
Then the second mask layer 230 can act as a mask for etching the underlying Si02 layer, in which the nickel islands 233 mask areas of the underlying Si02 layer and the spaces between the nickel islands leave exposed areas of the SiO2 layer, defining which areas of the underlying Si02 layer will be etched.
With reference to Figure Ic, the first mask layer 220 is etched through using CHF or SF6 in a reactive ion etching R1E) process using the metal islands 233 of the second mask layer 230 as a mask. This step provides nano-pillars (also referred to as nano-rods) 240 of silicon dioxide distributed irregularly over the GaN layer 210, each comprising a respective part 221 of the first mask layer 220 and a respective nickel
S
island 233, Each nano-rod 240 corresponds to a respective nickel island, having a diameter that is approximately the same as the diameter of the surface area covered its respective nickel island. The nano-pillars 240 resulting from the previous step serve to mask some areas of the GaN layer 210, and to define which areas (i.e. those exposed S areas in the spaces between the nano-pillars 240) of the GaN layer 210 will be etched.
Referring to Figure Id, at the next step the GaN layer 210 is etched, for example by inductive'y coupled p'asma etching, with the nano-piflars 240 that were fomied in the previous steps used as a mask, This step involves etching though the GaN layer 210, such as shown in Figure Id, or partly through the GaN layer 210. This step results in a nano-pillar structure, as shown in Figure id. in which nano-pillars 250 extend upwards from the sapphire substrate 205, each nano-piflar 250 comprising a respective part 211 of the GaN layer 210, a part 221 of the first mask layer 220, and a metal island 233 from the second mask layer 230. Therefore the etching of this step IS produces exposed surfaces 250a of the GaN, which comprise the sides of the nano-pillars 250, The diameter of each nano-piflar 250 is approximately constant from top to bottom, being approximately the same as the diameter of the surface area covered by its respective nickel island 233, although in practice some tapering of the nano-pillars generally occurs.
Referring to Figure le. the nickel islands 233 forming the second mask layer 230 are then removed, leading to the nano-pillar 260 comprising a respective part 211 of the GaN ayer 210. a part 221 of the first mask layer 220, This can be done by wet etching using hydrochloric acid (HC1) or nitric acid (HNO,). This leaves each nano-pillar comprising mainly a CaN column 211 with a Si02 cap 221 on its top end.
Referring to Figure if. the GaN nano-rod array is used as a template for deposition of GaN 270 onto the sides 250a of the GaN columns 211 by mctalorganic chemical vapour deposition (MOCVD) or MBE or I-IVPE for overgrowth. The re-growth starts on the sidewall of CaN nano-rod (firstly laterally and then vertically), where the GaN is exposed. This forms layers 271 on the sides of the nano-piflars. These grow outwards from the pillars and towards each other until they meet where the layers are thickest. This then prevents further growth in the volume 273 below the meeting point 272, and growth continues in the volume 274 above the meeting point. This leaves, in some cases, the volume 273 as hollow gaps or cavities around the base of each of the nano-piHars. These gaps may be interconnected to form a cavity, which is labyrinthine in form and extends between all, or substantially all of the nano-pillars.
The Si02 masks 221 on the top of nano-pillar will prevent GaN growth on their top.
Referring to Figure 1g. when the growing face of the GaN reaches above the top of the Si02 nano-masks 221 the CaN re-growth progresses laterally over the top of the Si02 nano-mask, and eventually coalesces to form a continuous layer extending over the top of the nano-mask, and having a smooth surface 27 as shown in Figure 1 h. In theory, all the dislocations originating from the template (i.e. in the nano-piflars 260) are effectively blocked, On the other hand, of course, due to the nature of the lateral overgrowth, the dislocations in the window regions (i.e., the regions directly above the gaps) will be eliminated or the number of the dislocation will be very low.
Therefore, the invention offers dual reduction in the number of dis'ocations, Once the growth has been completed, the substrate 205 can either be removed or still IS remain unremoved. In the case of the substrate 205 being removed, remova' of the substrate will generafly indude removal of the bottom end of the nano-pillars 260.
This can be made easier by the presence of the hollow volume 273 around the base of the nano-pillars. The bases of the nano-pillars 260 may be removed up to a level which is below the meeting point 272 i.e. below the top of the hollow volume 273.
This can result in a very uniform structure with ow leve's of strain, Figure 2 shows an array of GaN nanorods, each with a diameter of 200nni, which are achieved by the process described above but with on'y a sing'e coating and annealing of nickel, Figure 3 shows an array of GaN nanorods, each with a diameter of about 500-700nm, which are achieved by the process described above with two coatings of nickel each being annealed as described above, Referring to Figure 4 a further improvement in crystal quality has been achieved using the method described above with a doubk nickel layer, In particular the FWHMs of XRD rocking curve have been further reduced compared to the crystal formed with a single annealed nickel layer.
It is also very effective to extend the approach described above to the overgrowth of A1GaN on a GaN nano-pillar structure, without worrying about the coalescence issue, as the gaps between the CaN nano-rods are on a nano-meter scale, which is much narrower than those in the Si02 masks generally used in the conventional FLOG mentioned above. In addition, due to the residual voids left in the gaps between nano-rods during the overgrowth, the cracking issue of A1GaN on GaN which generally happens in conventional ITT-nitride growth can be eliminated, In a further embodiment the nano-pillar array is produced as described above, except that semiconductor layer 210 includes a number of quantum-well layers as described in W02010/146390. This results in each of the nano-pillars including quantum well layers. The gaps between the nano-piflars are fiHed with wavelength conversion material and/or metal nano-particles, and contact layers are applied so that the device forms an LED.
IS
It wifl be appreciated that other embodiments of the invention will vary from those described abovc. The method is applicable to different combinations of substrate, nano-pillar structure material, and grown semiconductor material, but is mostly applicable where the slLbstrate and grown semiconductor have sufficiently different lattice structures for the formation of dislocations in the semiconductor lattice structure to be a problem, Obviously the exact scale of the structure can be varied, though it is a particular advantage of the method that structure can be produced on a smafl scak, Also the first and second metal layers can each comprise different metals or alloys, For example each layer can comprise chromium, tungsten or titanium rather than nickel, or an alloy of any two or more of those metals. These are appropriate as the have relatively high melting points.

Claims (13)

  1. Claims 1. A method of making a semiconductor device comprising: (i) providing a semiconductor wafer having a semiconductor layer; S (ii) forming a first mask layer over the semiconductor layer; (iii) forming a metal second mask layer over the first mask layer; (iv) annealing the second mask layer to form islands; (v) forming a second metal layer over the islands; (vi) annealing the second metal layer thereby to increase the size of the islands; and (vii) etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.
  2. 2. A method according to claim 1 wherein the second metal layer is of the same IS metal or metal alloy as the second mask layer.
  3. 3. A method according to claim 1 or claim 2 further comprising removing the islands before growing the semiconductor material.
  4. 4. A method according to any foregoing claim wherein a cap formed from one of the mask layers is left on the top of each of the pillars during the growing of the semiconductor material.
  5. 5. A method according to any foregoing claim wherein the semiconductor layer is supported on a substrate.
  6. 6. A method according to claim 5 wherein the substrate comprises at least one of sapphire, silicon al1d silicon carbide.
  7. 7. A method according to any foregoing claim wherein the semiconductor layer is formed of a group IT! nitride.
  8. S. A method according to any foregoing claim wherein the first mask layer is formed of at least one of silicon dioxide and silicon nitride.
  9. 9. A method according to any foregoing claim wherein the second mask layer is formed of nickel.
  10. 10. A method according to any foregoing claim further comprising growing semiconductor material between the pillars and then over the tops of the pillars.
  11. 11. A method according to dairn 10 wherein the growing step leaves gaps around the bases of the pillars.
  12. 12. A method according to claim 11 wherein the semiconductor material grown on adjacent piflars meets at a level spaced from the substrate, so that the gaps are left below that lcvcl.IS
  13. 13. A method of making a semiconductor device substantiafly as described herein with reference to the accompanying drawings,
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PCT/GB2014/053496 WO2015079222A1 (en) 2013-11-27 2014-11-25 Semiconductor devices and fabrication methods
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US11634824B2 (en) 2021-06-09 2023-04-25 Epinovatech Ab Device for performing electrolysis of water, and a system thereof
US11652454B2 (en) 2020-02-14 2023-05-16 Epinovatech Ab Monolithic microwave integrated circuit front-end module
US11695066B2 (en) 2019-12-11 2023-07-04 Epinovatech Ab Semiconductor layer structure
US11955972B2 (en) 2020-03-13 2024-04-09 Epinovatech Ab Field-programmable gate array device

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FR3088478B1 (en) 2018-11-08 2020-10-30 Soitec Silicon On Insulator COLLECTIVE MANUFACTURING PROCESS OF A PLURALITY OF SEMI-CONDUCTIVE STRUCTURES

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US11469300B2 (en) * 2018-04-22 2022-10-11 Epinovatech Ab Reinforced thin-film semiconductor device and methods of making same
US11695066B2 (en) 2019-12-11 2023-07-04 Epinovatech Ab Semiconductor layer structure
US11652454B2 (en) 2020-02-14 2023-05-16 Epinovatech Ab Monolithic microwave integrated circuit front-end module
US11955972B2 (en) 2020-03-13 2024-04-09 Epinovatech Ab Field-programmable gate array device
US11634824B2 (en) 2021-06-09 2023-04-25 Epinovatech Ab Device for performing electrolysis of water, and a system thereof

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