CN105917444A - Semiconductor devices and fabrication methods - Google Patents

Semiconductor devices and fabrication methods Download PDF

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Publication number
CN105917444A
CN105917444A CN201480073098.1A CN201480073098A CN105917444A CN 105917444 A CN105917444 A CN 105917444A CN 201480073098 A CN201480073098 A CN 201480073098A CN 105917444 A CN105917444 A CN 105917444A
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mask layer
layer
post
mask
island
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王涛
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Seren Photonics Ltd
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Seren Photonics Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02367—Substrates
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region

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Abstract

A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a metal second mask layer over the first mask layer; annealing the second mask layer to form islands; forming a second metal layer over the islands; annealing the second metal layer thereby to increase the size of the islands; and etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.

Description

Semiconductor device and manufacture method
The present invention relates to semiconductor device and the method manufacturing semiconductor device.Specifically, this Bright relate in semiconductor device formed nanoscale cylinder.These nanoscale column structures are for such as giving birth to Produce light emitting diode (LED), be also used for the growth with the semiconductor device of high-quality crystal structure. These high-quality crystal structure devices itself can be used for such as forming light emitting diode and solid-state laser.
At present, mainly there are three kinds for manufacturing the white light emitting diode (LED) needed for solid-state illumination: The encapsulation of (1) three LED chip, each LED chip send different wave length (respectively red, Green and blue)；(2) blue (460 nanometer) LED and the Huang by the blue light pumping from LED The combination of color phosphor；And (3) single chip sending ultraviolet light, ultraviolet light is by three kinds of phosphorescence Body (red, green and blue) absorbs in LED encapsulates and re-emits as broad-spectrum white-light. For the first and second method, critical piece is blue/green LED, both based on InGaN material system.For the third method, high-performance ultraviolet (UV) is needed to launch Device.
For being in use for a long time based on InGaN and advanced growing technology based on AlGaN device, but It is generally basede on c surface sapphire substrate.Due to piezoelectric effect, this polarity orientation result in the strongest built-in Overlapping minimizing between electric field, and the device electronics and the hole wave effect that stand, and the radiation of device Recombination time is long, and therefore quantum efficiency is low.Here it is so-called quantum confined Stark effect (QCSE). Specifically, when emitter moves towards green spectral regions, need higher InN mark, and internal Electric field generally becomes high.This is to realize high-performance emitter based on InGaN (especially, green Emitter) major obstacle.UV emitter based on AlGaN occurs in that same problem, but It is compared with InGaN, the worse off of AlGaN.
For photoelectric device based on group III-nitride, it is generally desirable to isoepitaxial growth.So And, due to affordability reason, in the upper growth of foreign substrate (such as, sapphire, SiC, silicon etc.) Remain the main method of group III-nitride growth.This " Macrolattice mismatch hetero-epitaxy " causes Dislocation density is the highest.This will cause group III-nitride photoelectric device (such as, based on InGaN Nearly UV/ blue/green emitter and UV emitter based on AlGaN/GaN) optical property show Write and reduce.Due to the optical property of UV emitter based on the AlGaN/GaN sensitivity to dislocation Higher than emitter based on InGaN, therefore the dislocation of UV emitter based on AlGaN/GaN is asked Topic becomes more notable than emitter based on InGaN.
Above-mentioned two problems (QCSE and dislocation) is to improve light based on group III-nitride further Two basic obstacles of the optical property of electrical part.
One of the most promising method offsetting QCSE side effect is to be orientated along nonpolar or semipolar Growth, theoretical and experimental is all confirmed.Nonpolar or semipolar Ill group-III nitride emitter Another major advantage is that they can polarized light-emitting.Liquid crystal display (LCD) needs polarization illumination, The most current LCD needs extra polarizer to realize this point.The low transmission effect of polariser Rate causes efficiency lower, and therefore the device of polarized light-emitting is favourable.
Recently, the growth in nonpolar or semipolar plane of the Ill group-III nitride has made green emitter Achieve important breakthrough.But, additionally expose a significant challenge, i.e. these high performance non-poles Property or semi-polarity Ill group-III nitride emitter only grow in much more expensive GaN substrate, i.e. utilize Isoepitaxial growth method.Regrettably, nonpolar or semipolar GaN substrate is the least and the most high Expensive.Also make them unsuitable for for large-scale production additionally, highly non-uniform.
Accordingly, it would be desirable to utilize high crystal template having any size (such as reaching 12 inches) Sapphire Substrate on obtain nonpolar or semipolar GaN, with further growth based on InGaN or Device architecture based on AlGaN.Up to the present, traditional epitaxial lateral overgrowth has been used (ELOG) crystal quality of nonpolar or semipolar GaN on sapphire is improved.ELOG skill Art grows based on selective area.Generally, gas phase epitaxy of metal organic compound (MOVPE) is first passed through Or molecular beam epitaxy (MBE) or hydride gas-phase epitaxy (HVPE) growth standard on sapphire GaN layer, then utilizes dielectric mask (such as, SiO2Or Si3N4) coating surface of offing normal.Then, Use standard photolithography that mask pattern is melted into micron order striped (rather than nanoscale striped).Then, By MOVPE or MBE or HVPE by the sample the sheltered template acting on further growth. Owing to GaN will not be in the grown on top of dielectric mask, therefore regrowth is in mask hole port area Expose and start on GaN.When aufwuchsplate arrives mask over top, GaN regrowth has whole Horizontal expansion on striped mask, and finally can coalesce formation smooth surface.From mask in crystal structure The dislocation caused by the Macrolattice mismatch between sapphire and GaN below striped is effectively stoped. Due to the restriction of standard photolithography, mask width of fringe and wing width can not be further reduced to nanometer Level.Therefore, it is generally the case that until outgrowth layer has reached more than 10-20 μ m-thick, just can obtain Flat surfaces.Additionally, due to the cross growth speed of AlGaN is generally much less than the horizontal raw of GaN Long speed, so that coalescence is slowly, is therefore difficult to apply when AlGaN outgrowth this Method.
Therefore, traditional ELOG method is extremely complex, thus causes extra cost much higher.
The invention provides a kind of method manufacturing semiconductor device.The method can include that offer has half The semiconductor wafer (wafer) of conductor layer.The method may be included in semiconductor layer formation first and covers Mold layer.The method may be included in formation metal the second mask layer on the first mask layer.The method can be wrapped Include annealing or otherwise apply or revise the second mask layer to form some islands.The method can It is etched through the first mask layer and semiconductor layer to form post as mask including using island Array.The method can further include at and form the second metal level on island and to the second metal level Carry out annealing thus increase the size of island.
The second mask layer (can be regarded as the first metal layer) can annealed or with other side It is modified to be formed after forming island the second metal level by formula.Can be right before etching step Second metal level is annealed.
The material of the second metal level can be identical with the material of the second mask layer.Such as, the two may each be Nickel.
Metal coating and the repeatable third time of annealing steps, or can repeat the most secondary as required.
The array of post can be used for forming LED, as described in WO2010/146390.
Alternately, the method further includes at growth semi-conducting material between post, then at post Semi-conducting material is grown on top.
The method removes island before may be included in growth semi-conducting material.
During the growth of semi-conducting material, one of mask layer the block formed can stay each post Top.This can be the first mask layer.
Semiconductor layer can be supported on substrate.Substrate can include in sapphire, silicon and carborundum extremely Few one.
Growing into the semi-conducting material on post can be with the material phase forming semiconductor layer (thus forming post) With, or it can be different materials.
Semiconductor layer can be formed by group III-nitride.Such as, it can by gallium nitride, InGaN, Aluminium gallium nitride alloy or aluminium nitride are formed.Nitride can be semi-polarity or nonpolar.Such as, semi-polarity GaN is suitable for non-polar GaN.
First mask layer can be formed by least one in silicon dioxide and silicon nitride.
Second mask layer can be formed by a kind of metal or two kinds of different metals.Such as, the first metal layer The alloy of two or more in nickel, chromium, tungsten or titanium, or these metals can be included.Similarly, Second metal level can include the alloy of two or more in nickel, chromium, tungsten or titanium, or these metals. Second metal level can include the metal or alloy identical with the first metal layer, or it can be different gold Belong to or alloy.
The method can farther include to remove support substrate.This part that can include removing post, such as Lowermost portion.
Invention further provides a kind of semiconductor device, including: the array of post, each of which Post all includes the main cylinders formed by semi-conducting material, and each post is included on its top being formed The block formed by mask material；And semi-conducting material, this semi-conducting material prolongs between these posts Stretch and extend to form pantostrat on the top of post and on block.Both semi-conducting materials Can make identical or they be different.The diameter of the post that post array includes can be respectively less than 1500nm, preferably smaller than l000nm.The diameter of post is further preferably at least 300nm.It is said that in general, To there is scrambling in diameter, in order to some posts are more than other post, and post section is non-circular, and post Width along its length and non-constant.Therefore, column diameter can be measured as the minimum diameter of column top (i.e., On the direction that post is the narrowest measure diameter) meansigma methods (all posts).Post highly preferred at least For 500nm, more preferably at least 1000nm.The height of all posts can be essentially identical.Mask material It can be metal.
At least some nano-pillar can have chamber at their bottom periphery.
The present invention, based on so-called self-organizing nanometer mask method, optionally carries out follow-up outgrowth. The manufacture of self-organizing nanometer mask is very simple, and without additionally carrying out photoetching.With known ELOG Method is compared, and outgrowth layer (when there is outgrowth layer) can be relatively thin, but the crystal quality obtained Equivalent to or better than the crystal quality obtained by traditional E LOG method.Therefore, can be substantially reduced into This.Additionally, the method is expansible for growing any group III-nitride, including polarity, non-pole Property or semi-polarity group III-nitride.
The method or device can farther include being preferable to carry out of (mode in any combination) present invention Any one or more of the step of mode or feature, will only be entered this by example reference accompanying drawing now Line description, wherein:
Fig. 1 a to Fig. 1 h shows the step forming device according to the embodiment of the present invention；
Fig. 2 is the image of known nanometer stick array；
Fig. 3 is created as the nanometer stick array of a part for the process of the method according to Fig. 1 a to Fig. 1 h And the image of the standard sample of semi-polarity GaN；And
Fig. 4 shows the sample (semi-polarity GaN) that utilizes the nanometer stick array in Fig. 3 to be formed The song of fill width at half maximun of x-ray rocking curve as azimuthal function of incident x-ray bundle Line chart.
With reference to figure la, the first step manufacturing device is to provide suitable semiconductor wafer 201.Wafer 201 for conventional wafer and are made up of substrate 205, and in this case, substrate includes sapphire layer, blue For the semiconductor layer 210 formed by gallium nitride (GaN) on gem layer.In this case, GaN For semi-polarity GaN, but non-polar GaN can be used equally.Other material can be used.Such as, substrate Can be silicon or carborundum.Quasiconductor can be another kind of suitably material, such as another kind of III Nitride, such as InGaN (InGaN), aluminium gallium nitride alloy (AlGaN) or aluminium nitride (A1N).
First mask layer 220 is arranged on semiconductor layer 210, and the such as first mask layer 220 is by two Silicon oxide forms (although this layer has suitable substitution material, such as silicon nitride), and receives with 200 The substantially uniform thickness deposition of rice.Thicker layer, such as thickness can be used to reach 600nm.This can lead to Cross plasma enhanced chemical vapor deposition (PECVD) or thermal evaporation or sputtering or electron beam evaporation is real Existing.
The second mask layer 230 including metal (in this case for nickel) is arranged on the first mask layer 220 On.This can be realized by thermal evaporation or sputtering or electron beam evaporation.In this step, thickness is defined Spending substantially uniform nickel dam, thickness range is 5 to 50 nanometers (preferably 5 to 25nm), then At flowing nitrogen (N at a temperature of 600 to 900 degrees Celsius (preferably 700 to 850 degrees Celsius)2) In anneal.The persistent period of annealing process is 1 to 10 minute so that defined layer by nickel dam 230, layer 230 includes the self assembly nickel island 231 being allocated in brokenly on the first mask layer 220, As shown in Figure 1 b.Each nickel island 231 all covers the phase of the upper surface of the first mask layer 220 Answering generally circular region, the diameter in region is usually not less than 100 nanometers, but less than 1500 Nanometer.
In order to increase the size of nickel island, thin at deposited atop second nickel of the nickel island formed Being between nickel island of film, the second nickel thin film covering nickel island 231 and the first mask layer 220 Both exposed regions.Then, at high temperature the second nickel film is annealed, the temperature range of annealing The most identical with the annealing of the first nickel dam with time period scope.As a result of which it is, the second nickel dam 232 is at nickel The surface (that is, side and top) of island 231 is upper assembles, thus increases the size of nickel island, To form bigger island 233.It is said that in general, second coats and is not formed new in annealing steps Nickel island.Certainly, the second nickel film of deposition and annealing time thereof and temperature can respectively with enter for the first time The deposition of row is different with annealing.Additionally, nickel deposition and subsequent anneal process can be repeated once further or Repeatedly the size of island is increased to required size to serve as the second mask layer.
Then, the second mask layer 230 may act as etching following SiO2Layer mask, wherein under The SiO in face2Space between nickel island 233 masks area and the nickel island of layer can stay SiO2The region of layer exposes, thus limits following SiO2Which region of layer will be etched.
With reference to Fig. 1 c, the metal islands 233 of the second mask layer 230 is used as the reaction of mask from During son etching (RIE), by using CHF3Or SF6First mask layer 220 is etched. This step provides the silica nanometer post being allocated in brokenly in GaN layer 210 (also referred to as Nanometer rods) 240, each nano-pillar all includes appropriate section 221 and the phase of the first mask layer 220 The nickel island 233 answered.Each nanometer rods 240 is all corresponding with corresponding nickel island, its diameter Roughly the same with the diameter in the region, surface covering its corresponding nickel island.By receiving that step before is formed Rice post 240 is for sheltering some regions of GaN layer 210, and limits which district of GaN layer 210 Territory (that is, those exposed regions in the space between nano-pillar 240) will be etched.
With reference to Fig. 1 d, at next step, such as, etched GaN layer by inductively coupled plasma 210 are etched, and the nano-pillar 240 wherein formed in step before is used as mask.This step bag Include and be etched through GaN layer 210, as shown in Figure 1 d, or be partly etched through GaN layer 210. This step defines nano-pillar structure, and as shown in Figure 1 d, wherein nano-pillar 250 is from Sapphire Substrate 205 upwardly extend, and each nano-pillar 250 all includes the appropriate section 211 of GaN layer 210, the The part 221 of one mask layer 220 and the metal islands 233 from the second mask layer 230.Cause This, the etching of this step defines the exposed surface 250a of GaN, and exposed surface includes nano-pillar 250 Side.The diameter of each nano-pillar 250 constant from top to bottom, its corresponding nickel island The diameter in the region, surface that thing 233 is covered is roughly the same, although nano-pillar would generally go out in practice More existing taperings.
With reference to figure le, then remove the nickel island 233 forming the second mask layer 230, produce nanometer Post 260, this nano-pillar includes the appropriate section 211 of GaN layer 210, the one of the first mask layer 220 Part 221.This can use hydrochloric acid (HC1) or nitric acid (HNO3) carried out by wet etching.This Make each nano-pillar mainly include GaN cylinder 211, the top of cylinder has SiO2Block 221。
With reference to Fig. 1 f, GaN nanometer stick array is used as template to be sunk by metal-organic chemical vapor GaN 270 is deposited to the side of GaN cylinder 211 by long-pending (MOCVD) or MBE or HVPE On carry out outgrowth.Regrowth starts (first laterally, then to erect on the sidewall of GaN nanometer rods Directly), wherein GaN is to expose.This defines layer 271 on the side of nano-pillar.These layers from Post is outwards and towards each other grows, until meeting, the place's of meeting layer is the thickest.Then, this prevent layer Grow in volume 273 below engagement point 272 further, and in the volume 274 above engagement point Growth proceed.In some cases, this makes volume 273 become the end of each nano-pillar Hollow gap around portion or chamber.These gaps can be interconnected so as to form chamber, the outer likeness in form labyrinth in chamber And extend between all nano-pillar or essentially all nano-pillar.SiO on the top of nano-pillar2 Mask 221 will stop the GaN grown on top at them.With reference to Fig. 1 g, when the aufwuchsplate of GaN Arrive SiO2During the over top of nanometer mask 221, GaN regrowth is at SiO2The top of nanometer mask Laterally carry out on portion, and finally coalescence be formed at the pantostrat extended on the top of nanometer mask, And there is smooth surface 271, as shown in figure 1h.In theory, all (that is, receiving from template Rice post 260 in) dislocation all effectively stoped.Certainly, on the other hand, due to horizontal outgrowth Character, the dislocation in window area (that is, the region directly over gap) will eliminate, and dislocation Quantity will be the lowest.Therefore, the present invention serves dual function in terms of reducing number of dislocations.
Once grow and complete, can be removed or not remove substrate 205.In the situation removing substrate 205 Under, remove substrate and typically will include removing the bottom of nano-pillar 260.During nano-pillar bottom periphery exists Empty volume 273 can make to remove easier.The bottom of nano-pillar 260 can be removed to engagement point 272 The height of lower section, i.e. below the top of hollow volume 273.This can make structure highly uniform, and should Change level is low.
Fig. 2 shows the array of GaN nanometer rods, a diameter of～200nm of each GaN nanometer rods, GaN nanometer rods is realized by procedure described above, but this process only includes the coating of single nickel and annealing.
Fig. 3 shows the array of GaN nanometer rods, and the diameter of each GaN nanometer rods is about 500-700nm, GaN nanometer rods is realized by procedure described above, and this process includes that twice nickel is coated with Covering, nickel coating each time is all as described above anneals.
With reference to Fig. 4, utilize described above pair of nickel dam method, further improved crystal quality. Specifically, compared with the crystal being formed with single annealing nickel dam, the FWHM of XRD rocking curve (full width half maximum) reduces the most further.
Process as described above is extended in GaN nano-pillar structure outgrowth AlGaN the most very Effectively, and do not worry agglomeration problem, this is because the gap between GaN nanometer rods is nanoscale, Nanoscale gap SiO more normally used than above-mentioned traditional E LOG2Gap in mask is much narrower. Additionally, due to gap between nanometer rods remains space during outgrowth, biography therefore can be eliminated The problem that the AlGaN on GaN generally occurred in system group III-nitride growth ruptures.
In further embodiment, mode as above produces nano column array, different It is that semiconductor layer 210 includes many quantum well layers as described in WO2010/146390.This makes Each nano-pillar all includes quantum well layer.Gap between nano-pillar be filled with material for transformation of wave length and / or metal nanoparticle, and apply contact layer so that device forms LED.
Should be understood that other embodiments of the present invention will be different with those described above.The party Method is applicable to the various combination of the semi-conducting material of substrate, nano-pillar structural material and growth, but mainly Difference be applicable to substrate Yu the lattice structure of the quasiconductor of growth be enough to semiconductor die lattice structure Form dislocation thus become the situation of problem.Obviously, although the special advantage of the method is can be with little Scale production structure, but the exact scale of structure can change.Additionally, the first metal layer and the second metal Layer can all include different metal or alloy.Such as, each layer can include chromium, tungsten or titanium rather than nickel, Or the alloy of two or more in these metals.Owing to their fusing point is of a relatively high, therefore it Be well suited for.

Claims (13)

1. the method manufacturing semiconductor device, including:
I () provides the semiconductor wafer with semiconductor layer；
(ii) the first mask layer is formed in described semiconductor layer；
(iii) on described first mask layer, form the second mask layer of metal；
(iv) anneal to form multiple island to described second mask layer；
V () forms the second metal level on described island；
(vi) described second metal level is annealed, thus increase the chi of described island Very little；And
(vii) use described island as mask to be etched through described first mask layer and Described semiconductor layer, to form the array of post.
Method the most according to claim 1, the metal of wherein said second metal level or metal close Golden and described second mask layer is identical.
3., according to the method described in claim 1 or claim 2, further include at growth described Described island is removed before semi-conducting material.
4. according to the method according to any one of the claims, wherein raw at described semi-conducting material During length, one of described mask layer each post in described post is stayed in the block formed Top.
5., according to the method according to any one of the claims, wherein said semiconductor layer is supported on On substrate.
Method the most according to claim 5, wherein said substrate includes sapphire, silicon and carbonization At least one in silicon.
7., according to the method according to any one of the claims, wherein said semiconductor layer is by III Group-III nitride is formed.
8., according to the method according to any one of the claims, wherein said first mask layer is by two At least one in silicon oxide and silicon nitride is formed.
9., according to the method according to any one of the claims, wherein said second mask layer is by nickel Formed.
10., according to the method according to any one of the claims, further include between described post And on the top of described post, then grow semi-conducting material.
11. methods according to claim 10, wherein growth step is around the bottom of described post Leaving gap.
12. methods according to claim 11, the wherein described quasiconductor of growth on adjacent post Material meets being separated by certain altitude with described substrate, in order to described height is stayed in described gap The lower section of degree.
13. 1 kinds manufacture basic such as the method herein with reference to the semiconductor device described by accompanying drawing.
CN201480073098.1A 2013-11-27 2014-11-25 Semiconductor devices and fabrication methods Pending CN105917444A (en)

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