EP3075002A1 - Semiconductor devices and fabrication methods - Google Patents

Semiconductor devices and fabrication methods

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Publication number
EP3075002A1
EP3075002A1 EP14803236.0A EP14803236A EP3075002A1 EP 3075002 A1 EP3075002 A1 EP 3075002A1 EP 14803236 A EP14803236 A EP 14803236A EP 3075002 A1 EP3075002 A1 EP 3075002A1
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EP
European Patent Office
Prior art keywords
layer
pillars
mask
semiconductor
islands
Prior art date
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Application number
EP14803236.0A
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German (de)
French (fr)
Inventor
Tao Wang
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Seren Photonics Ltd
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Seren Photonics Ltd
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Publication of EP3075002A1 publication Critical patent/EP3075002A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region

Definitions

  • the invention relates to semiconductor devices and methods of making semiconductor devices.
  • it relates to the formation of nano-scale columns in semiconductor devices.
  • These nano-scale column structures have application, for example, in the production of light emitting diodes (LEDs), as well in the growth of semiconductor devices with high quality crystal structure.
  • These high quality crystal structure devices can themselves be used, for example, in the formation of light emitting diodes and solid state lasers.
  • LEDs white light emitting diodes
  • the key components are blue/green LEDs, both of which are based on InGaN material systems.
  • UV ultraviolet
  • Ill-nitride based optoelectronic devices Homoepitaxial growth is ideal for Ill-nitride based optoelectronic devices.
  • growth on foreign substrate such as sapphire, SiC, silicon, etc.
  • Such "large lattice-mismatched heteroepitaxy" leads to a very high density of dislocations. This will cause a significant reduction in optical performance of Ill-nitride optoelectronics, such as InGaN-based near UV/blue/green emitters and AlGaN/GaN-based UV emitters.
  • the dislocation issue becomes more pronounced in AlGaN/GaN-based UV emitters than InGaN-based emitters, as optical performance of AlGaN/GaN-based UV emitters is more sensitive to dislocations than InGaN-based emitters.
  • Non-polar or semi-polar Ill-nitride emitters are growth along non-polar or semi-polar orientations, as confirmed theoretically and experimentally.
  • Another major advantage of non-polar or semi-polar Ill-nitride emitters is that they can emit polarized light.
  • Liquid-crystal displays (LCDs) require polarized illumination and current LCDs require an extra polarizing element to achieve this.
  • the low transmission efficiency of the polarizer leads to lower efficiency and a device emitting polarized light is advantageous.
  • non-polar or semi-polar GaN with high crystal template on sapphire substrate with any size (such as up to 12 inch) for further growth of InGaN-based or AlGaN-based device structures.
  • conventional epitaxial lateral overgrowth has been employed in improving crystal quality of non- polar or semi-polar GaN on sapphire.
  • the ELOG technique is based on selective area growth.
  • a standard GaN layer is first grown on sapphire by metalorganic vapour phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) or hydride vapour phase epitaxy (HVPE), and the surface is then coated ex-situ with a dielectric mask such as Si0 2 or Si 3 N 4 .
  • MOVPE metalorganic vapour phase epitaxy
  • MBE molecular beam epitaxy
  • HVPE hydride vapour phase epitaxy
  • the mask is then patterned into micron-scale stripes (not nanometer scale) using standard photolithography.
  • the masked sample is then used as a template for further growth by MOVPE or MBE or HVPE.
  • the re-growth starts on the exposed GaN in the mask window areas, as the GaN does not grow on top of the dielectric mask.
  • the GaN regrowth extends laterally over the striped mask, and can eventually coalesces to form a smooth surface .
  • the mask-stripe width and wing width can not be further decreased down to nanometer scale. Therefore, normally, a flat surface cannot be obtained till the overgrown layer has reached more than 10 - 20 ⁇ thick.
  • it is difficult to apply such approach in overgrowth of AlGaN as AlGaN lateral growth rate is generally much smaller than GaN lateral growth rate, leading to a very slow coalescence. Therefore, the conventional ELOG approach is very complicated, and thus leads to much higher extra cost.
  • the invention provides a method of making a semiconductor device .
  • the method may comprise providing a semiconductor wafer having a semiconductor layer.
  • the method may comprise forming a first mask layer over the semiconductor layer.
  • the method may comprise forming a metal second mask layer over the first mask layer.
  • the method may comprise annealing or otherwise applying or modifying the second mask layer to form islands.
  • the method may comprise etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.
  • the method may further comprise forming a second metal layer over the islands and annealing the second metal layer thereby to increase the size of the islands.
  • the second metal layer may be formed after the second mask layer (which can be considered as a first metal layer), has been annealed or otherwise modified to form islands.
  • the second metal layer may be annealed before the etching step.
  • the second metal layer may be of the same material as the second mask layer. For example both may be of nickel.
  • the metal coating and annealing step may be repeated a third time, or indeed any number of times as required.
  • the array of pillars may be used in the formation of an LED as described in WO2010/146390.
  • the method further comprises growing semiconductor material between the pillars and then over the tops of the pillars.
  • the method may comprise removing the islands before growing the semiconductor material.
  • a cap formed from one of the mask layers may be left on the top of each of the pillars during the growing of the semiconductor material. This may be the first mask layer.
  • the semiconductor layer may be supported on a substrate.
  • the substrate may comprise at least one of sapphire, silicon and silicon carbide .
  • the semiconductor material which is grown onto the pillars may be the same material as that making up the semiconductor layer (and hence the pillars), or it may be a different material.
  • the semiconductor layer may be formed of a group III nitride .
  • it may be formed of gallium nitride, indium gallium nitride, aluminium gallium nitride, or aluminium nitride .
  • the nitride may be semi-polar or non-polar.
  • semi- polar GaN is a suitable, as is non-polar GaN.
  • the first mask layer may be formed of at least one of silicon dioxide and silicon nitride.
  • the second mask layer may be formed of a metal, or two different metals.
  • the first metal layer may comprise nickel, chromium, tungsten or titanium, or an alloy of two or more of those metals.
  • the second metal layer may comprise nickel, chromium, tungsten or titanium, or an alloy of two or more of those metals.
  • the second metal layer may comprise the same metal or alloy as the first metal layer, or it may be a different metal or alloy.
  • the method may further comprise removing the support substrate. This may include removing a part, e .g. the lowest part, of the pillars.
  • the present invention further provides a semiconductor device comprising an array of pillars each including a main column formed of semiconductor material, and each including a cap formed of a mask material formed on its top, and a semiconductor material extending between the pillars and over the top of the pillars, and over the caps, to form a continuous layer.
  • the two semiconductor materials may be the same, or they may be different.
  • the pillar array may comprise pillars all having diameters less than 1500nm and preferably less than l OOOnm,.
  • the pillars are also preferably at least 300nm in diameter. In general there will be irregularity in the diameters such that some of the pillars are larger than others, and the cross sections are not circular, and their width is not constant along their length.
  • the diameter of the pillars may therefore be measured as the mean (over all pillars) of the minimum diameter (i.e . measured in the direction in which the pillar is narrowest) at the top of the pillars.
  • the height of the pillars is preferably at least 500nm, more preferably at least l OOOnm.
  • the pillars may be all of substantially the same height.
  • the mask material may be a metal.
  • the present invention is based on a so-called self-organised nano-mask approach, optionally with subsequent overgrowth.
  • the fabrication of the self-organised nano- mask is very simple, and does not require extra photolithography.
  • the overgrown layer, when present, can be relatively thin compared to known ELOG methods, but the obtained crystal quality is equivalent to or better than that obtained by the conventional ELOG. Therefore, the cost can be significantly reduced.
  • the approach can be extended for growth of any Ill-nitrides including polar, non-polar, or semi-polar.
  • the method or device may further comprise, in any combination, any one or more of the steps or features of the preferred embodiments of the invention, which will now be described, by way of example only, with reference to the accompanying drawings in which:
  • Figures l a to lh show the steps in the formation of a device according an embodiment of the invention
  • Figure 2 is an image of a known nano-rod array
  • Figure 3 is an image of a nano-rod array formed as part of a process according to the method of Figures la to lh, and a standard sample of semi-polar GaN;
  • Figure 4 is a graph showing showing the full width at half maximum for the x- ray rocking curve as a function of azimuth angle of the incident x-ray beam, for a sample (semi-polar GaN) formed using the nano-rod array of Figure 3.
  • the first step of fabricating the device is providing a suitable semiconductor wafer 201.
  • the wafer 201 is conventional and is made up of a substrate 205, which in this case comprises a layer of sapphire, over which is a semiconductor layer 210 formed of gallium nitride (GaN).
  • GaN gallium nitride
  • the GaN is semi-polar GaN, but non-polar GaN can equally be used.
  • the substrate may be silicon or silicon carbide.
  • the semiconductor may be another suitable material, for example another group III nitride such as indium gallium nitride (InGaN), aluminium gallium nitride (AlGaN) or aluminium nitride (A1N)
  • a first mask layer 220 is provided over the semiconductor layer 210, for examplethe first mask layer 220 is formed of silicon dioxide, although there are suitable alternative materials for this layer e.g. silicon nitride, and is deposited at an approximately uniform thickness of 200 nanometres.
  • a thicker layer for example up to 600nm, can be used. This can be by plasma-enhanced chemical vapour deposition (PECVD) or thermal evaporation or sputtering or electron beam evaporation.
  • a second mask layer 230 comprising a metal which in this case is nickel, is provided over the first mask layer 220.
  • This can be by thermal evaporation or sputtering or electron beam evaporation.
  • the duration of the annealing process is between 1 and 10 minutes, resulting in formation from the nickel layer of a layer 230 comprising self-assembled nickel islands 23 1 distributed irregularly over the first mask layer 220 as shown in Figure lb.
  • Each of the nickel islands 23 1 covers a respective, approximately circular, area of the upper surface of first mask layer 220 which is, typically, no less than 100 nanometres in diameter and no more than 1500 nanometres in diameter.
  • a second thin nickel film is deposited on the top of the formed nickel islands, which covers both the nickel islands 23 1 and the exposed areas of the first mask layer 220 between the nickel islands.
  • the second nickel film is then annealed at a high temperature, generally in the same temperature range and time period range as the annealing of the first nickel layer.
  • the result of this is that the second layer of nickel 232 collects on the surface, i.e. the sides and the top, of the nickel islands 23 1 , thereby increasing the size of the nickel islands to form larger islands 233.
  • no new nickel islands are formed in the second coating and annealing step.
  • the second deposited nickel film and the time and temperature at which it is annealed can be different to those done in the first time, respectively.
  • the nickel-deposition and the subsequent annealing processes can be repeated one or more further times to increase the size of the islands to the required size to act as the second mask layer.
  • the second mask layer 230 can act as a mask for etching the underlying Si0 2 layer, in which the nickel islands 233 mask areas of the underlying Si0 2 layer and the spaces between the nickel islands leave exposed areas of the Si0 2 layer, defining which areas of the underlying Si0 2 layer will be etched.
  • the first mask layer 220 is etched through using CHF 3 or SF 6 in a reactive ion etching (RIE) process using the metal islands 233 of the second mask layer 230 as a mask.
  • This step provides nano-pillars (also referred to as nano- rods) 240 of silicon dioxide distributed irregularly over the GaN layer 210, each comprising a respective part 221 of the first mask layer 220 and a respective nickel island 233.
  • Each nano-rod 240 corresponds to a respective nickel island, having a diameter that is approximately the same as the diameter of the surface area covered its respective nickel island.
  • the nano-pillars 240 resulting from the previous step serve to mask some areas of the GaN layer 210, and to define which areas (i.e. those exposed areas in the spaces between the nano-pillars 240) of the GaN layer 210 will be etched.
  • the GaN layer 210 is etched, for example by inductively coupled plasma etching, with the nano-pillars 240 that were formed in the previous steps used as a mask.
  • This step involves etching though the GaN layer 210, such as shown in Figure Id, or partly through the GaN layer 210.
  • This step results in a nano-pillar structure, as shown in Figure I d, in which nano-pillars 250 extend upwards from the sapphire substrate 205, each nano-pillar 250 comprising a respective part 21 1 of the GaN layer 210, a part 221 of the first mask layer 220, and a metal island 233 from the second mask layer 230.
  • each nano-pillar 250 is approximately constant from top to bottom, being approximately the same as the diameter of the surface area covered by its respective nickel island 233, although in practice some tapering of the nano- pillars generally occurs.
  • the nickel islands 233 forming the second mask layer 230 are then removed, leading to the nano-pillar 260 comprising a respective part 21 1 of the GaN layer 210, a part 221 of the first mask layer 220.
  • This can be done by wet etching using hydrochloric acid (HC1) or nitric acid (HN0 3 ). This leaves each nano-pillar comprising mainly a GaN column 21 1 with a Si0 2 cap 221 on its top end.
  • the GaN nano-rod array is used as a template for deposition of GaN 270 onto the sides 250a of the GaN columns 21 1 by metalorganic chemical vapour deposition (MOCVD) or MBE or HVPE for overgrowth.
  • MOCVD metalorganic chemical vapour deposition
  • MBE MBE
  • HVPE metalorganic chemical vapour deposition
  • the re-growth starts on the sidewall of GaN nano-rod (firstly laterally and then vertically), where the GaN is exposed.
  • the volume 273 as hollow gaps or cavities around the base of each of the nano-pillars. These gaps may be interconnected to form a cavity, which is labyrinthine in form and extends between all, or substantially all of the nano-pillars .
  • the Si0 2 masks 221 on the top of nano-pillar will prevent GaN growth on their top. Referring to Figure lg, when the growing face of the GaN reaches above the top of the Si0 2 nano-masks 221 the GaN re-growth progresses laterally over the top of the Si0 2 nano-mask, and eventually coalesces to form a continuous layer extending over the top of the nano-mask, and having a smooth surface 271 as shown in Figure lh.
  • the invention offers dual reduction in the number of dislocations.
  • the substrate 205 can either be removed or still remain unremoved.
  • removal of the substrate will generally include removal of the bottom end of the nano-pillars 260. This can be made easier by the presence of the hollow volume 273 around the base of the nano-pillars.
  • the bases of the nano-pillars 260 may be removed up to a level which is below the meeting point 272 i.e. below the top of the hollow volume 273. This can result in a very uniform structure with low levels of strain.
  • Figure 2 shows an array of GaN nanorods, each with a diameter of ⁇ 200nm, which are achieved by the process described above but with only a single coating and annealing of nickel.
  • Figure 3 shows an array of GaN nanorods, each with a diameter of about 500-700nm, which are achieved by the process described above with two coatings of nickel each being annealed as described above.
  • Figure 4 a further improvement in crystal quality has been achieved using the method described above with a double nickel layer.
  • the FWHMs of XRD rocking curve have been further reduced compared to the crystal formed with a single annealed nickel layer.
  • the nano-pillar array is produced as described above, except that semiconductor layer 210 includes a number of quantum-well layers as described in WO2010/146390. This results in each of the nano-pillars including quantum well layers.
  • the gaps between the nano-pillars are filled with wavelength conversion material and/or metal nano-particles, and contact layers are applied so that the device forms an LED.
  • first and second metal layers can each comprise different metals or alloys.
  • each layer can comprise chromium, tungsten or titanium rather than nickel, or an alloy of any two or more of those metals. These are appropriate as they have relatively high melting points.

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Abstract

A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a metal second mask layer over the first mask layer; annealing the second mask layer to form islands; forming a second metal layer over the islands; annealing the second metal layer thereby to increase the size of the islands; and etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.

Description

SEMICONDUCTOR DEVICES AND FABRICATION METHODS
The invention relates to semiconductor devices and methods of making semiconductor devices. In particular it relates to the formation of nano-scale columns in semiconductor devices. These nano-scale column structures have application, for example, in the production of light emitting diodes (LEDs), as well in the growth of semiconductor devices with high quality crystal structure. These high quality crystal structure devices can themselves be used, for example, in the formation of light emitting diodes and solid state lasers.
Currently, there are three main approaches for the fabrication of white light emitting diodes (LEDs) needed for solid state lighting: ( 1 ) a package of three LED chips each emitting at a different wavelength (red, green and blue, respectively); (2) a combination of a blue (460 nm) LED and a yellow phosphor pumped by blue light from the LED; (3) a single chip emitting UV light which is absorbed in the LED package by three phosphors (red, green and blue) and reemitted as a broad spectrum of white light. For the 1 st and 2nd approaches, the key components are blue/green LEDs, both of which are based on InGaN material systems. For the 3rd approach, ultraviolet (UV) emitters with high performance are required.
Advanced growth technologies for InGaN based and AlGaN-based devices have been well established, but are generally based on c-face sapphire substrates. This polar orientation results in intense built-in electric field due to piezoelectric effects and the devices suffer from reduced overlap between the electron and hole wave functions and long radiative recombination times, and thus low quantum efficiency. This is the so- called quantum confined Stark effect (QCSE). In particular, when the emitters move towards the green spectral region, much higher InN fractions are required and the internal electric fields generally become extremely high. This presents a major obstacle to achieving InGaN-based emitters (in particular, green emitter) with high performance . The same problem arises for AlGaN-based UV emitters, but it is even worse for AlGaN than for InGaN.
Homoepitaxial growth is ideal for Ill-nitride based optoelectronic devices. However, due to affordability reasons, growth on foreign substrate such as sapphire, SiC, silicon, etc., still remains a main approach for growth of Ill-nitrides. Such "large lattice-mismatched heteroepitaxy" leads to a very high density of dislocations. This will cause a significant reduction in optical performance of Ill-nitride optoelectronics, such as InGaN-based near UV/blue/green emitters and AlGaN/GaN-based UV emitters. The dislocation issue becomes more pronounced in AlGaN/GaN-based UV emitters than InGaN-based emitters, as optical performance of AlGaN/GaN-based UV emitters is more sensitive to dislocations than InGaN-based emitters.
The two issues (QCSE and dislocations) stated above are two fundamental obstacles in further improving optical performance of Ill-nitride-based optoelectronics.
One of the most promising approaches to counteract the negative effects of the QCSE is growth along non-polar or semi-polar orientations, as confirmed theoretically and experimentally. Another major advantage of non-polar or semi-polar Ill-nitride emitters is that they can emit polarized light. Liquid-crystal displays (LCDs) require polarized illumination and current LCDs require an extra polarizing element to achieve this. The low transmission efficiency of the polarizer leads to lower efficiency and a device emitting polarized light is advantageous.
Very recently Ill-nitride growth on non-polar or semi-polar planes has led to major breakthroughs for green emitters. However, a major challenge has also been exposed, i.e., these non-polar or semi-polar Ill-nitride emitters with high performance are exclusively grown on extremely expensive GaN substrates, i.e. using the homoepitaxial growth approach. Unfortunately, non-polar or semi-polar GaN substrates are very small and extremely expensive . In addition, being highly non- uniform also makes them unsuitable for mass production.
Therefore, it is desirable to obtain non-polar or semi-polar GaN with high crystal template on sapphire substrate with any size (such as up to 12 inch) for further growth of InGaN-based or AlGaN-based device structures. So far, conventional epitaxial lateral overgrowth (ELOG) has been employed in improving crystal quality of non- polar or semi-polar GaN on sapphire. The ELOG technique is based on selective area growth. Typically, a standard GaN layer is first grown on sapphire by metalorganic vapour phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) or hydride vapour phase epitaxy (HVPE), and the surface is then coated ex-situ with a dielectric mask such as Si02 or Si3N4. The mask is then patterned into micron-scale stripes (not nanometer scale) using standard photolithography. The masked sample is then used as a template for further growth by MOVPE or MBE or HVPE. The re-growth starts on the exposed GaN in the mask window areas, as the GaN does not grow on top of the dielectric mask. When the growing face reaches above the top of the mask the GaN regrowth extends laterally over the striped mask, and can eventually coalesces to form a smooth surface . The dislocations in the crystal structure originating under the mask stripes, caused by the large lattice mismatch between sapphire and GaN, are effectively blocked. Due to the limits of standard photolithography, the mask-stripe width and wing width can not be further decreased down to nanometer scale. Therefore, normally, a flat surface cannot be obtained till the overgrown layer has reached more than 10 - 20 μιη thick. In addition, it is difficult to apply such approach in overgrowth of AlGaN, as AlGaN lateral growth rate is generally much smaller than GaN lateral growth rate, leading to a very slow coalescence. Therefore, the conventional ELOG approach is very complicated, and thus leads to much higher extra cost.
The invention provides a method of making a semiconductor device . The method may comprise providing a semiconductor wafer having a semiconductor layer. The method may comprise forming a first mask layer over the semiconductor layer. The method may comprise forming a metal second mask layer over the first mask layer. The method may comprise annealing or otherwise applying or modifying the second mask layer to form islands. The method may comprise etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars. The method may further comprise forming a second metal layer over the islands and annealing the second metal layer thereby to increase the size of the islands.
The second metal layer may be formed after the second mask layer (which can be considered as a first metal layer), has been annealed or otherwise modified to form islands. The second metal layer may be annealed before the etching step.
The second metal layer may be of the same material as the second mask layer. For example both may be of nickel. The metal coating and annealing step may be repeated a third time, or indeed any number of times as required.
The array of pillars may be used in the formation of an LED as described in WO2010/146390.
Alternatively, the method further comprises growing semiconductor material between the pillars and then over the tops of the pillars. The method may comprise removing the islands before growing the semiconductor material.
A cap formed from one of the mask layers may be left on the top of each of the pillars during the growing of the semiconductor material. This may be the first mask layer.
The semiconductor layer may be supported on a substrate. The substrate may comprise at least one of sapphire, silicon and silicon carbide .
The semiconductor material which is grown onto the pillars may be the same material as that making up the semiconductor layer (and hence the pillars), or it may be a different material.
The semiconductor layer may be formed of a group III nitride . For example it may be formed of gallium nitride, indium gallium nitride, aluminium gallium nitride, or aluminium nitride . The nitride may be semi-polar or non-polar. For example semi- polar GaN is a suitable, as is non-polar GaN.
The first mask layer may be formed of at least one of silicon dioxide and silicon nitride.
The second mask layer may be formed of a metal, or two different metals. For example the first metal layer may comprise nickel, chromium, tungsten or titanium, or an alloy of two or more of those metals. Similarly the second metal layer may comprise nickel, chromium, tungsten or titanium, or an alloy of two or more of those metals. The second metal layer may comprise the same metal or alloy as the first metal layer, or it may be a different metal or alloy.
The method may further comprise removing the support substrate. This may include removing a part, e .g. the lowest part, of the pillars.
The present invention further provides a semiconductor device comprising an array of pillars each including a main column formed of semiconductor material, and each including a cap formed of a mask material formed on its top, and a semiconductor material extending between the pillars and over the top of the pillars, and over the caps, to form a continuous layer. The two semiconductor materials may be the same, or they may be different. The pillar array may comprise pillars all having diameters less than 1500nm and preferably less than l OOOnm,. The pillars are also preferably at least 300nm in diameter. In general there will be irregularity in the diameters such that some of the pillars are larger than others, and the cross sections are not circular, and their width is not constant along their length. The diameter of the pillars may therefore be measured as the mean (over all pillars) of the minimum diameter (i.e . measured in the direction in which the pillar is narrowest) at the top of the pillars. The height of the pillars is preferably at least 500nm, more preferably at least l OOOnm. The pillars may be all of substantially the same height. The mask material may be a metal.
At least some of the nano-pillars may have cavities around their bases. The present invention is based on a so-called self-organised nano-mask approach, optionally with subsequent overgrowth. The fabrication of the self-organised nano- mask is very simple, and does not require extra photolithography. The overgrown layer, when present, can be relatively thin compared to known ELOG methods, but the obtained crystal quality is equivalent to or better than that obtained by the conventional ELOG. Therefore, the cost can be significantly reduced. In addition, the approach can be extended for growth of any Ill-nitrides including polar, non-polar, or semi-polar.
The method or device may further comprise, in any combination, any one or more of the steps or features of the preferred embodiments of the invention, which will now be described, by way of example only, with reference to the accompanying drawings in which:
Figures l a to lh show the steps in the formation of a device according an embodiment of the invention;
Figure 2 is an image of a known nano-rod array;
Figure 3 is an image of a nano-rod array formed as part of a process according to the method of Figures la to lh, and a standard sample of semi-polar GaN; and
Figure 4 is a graph showing showing the full width at half maximum for the x- ray rocking curve as a function of azimuth angle of the incident x-ray beam, for a sample (semi-polar GaN) formed using the nano-rod array of Figure 3.
Referring to Figure la, the first step of fabricating the device is providing a suitable semiconductor wafer 201. The wafer 201 is conventional and is made up of a substrate 205, which in this case comprises a layer of sapphire, over which is a semiconductor layer 210 formed of gallium nitride (GaN). In this cases the GaN is semi-polar GaN, but non-polar GaN can equally be used. Other materials can be used. For example the substrate may be silicon or silicon carbide. The semiconductor may be another suitable material, for example another group III nitride such as indium gallium nitride (InGaN), aluminium gallium nitride (AlGaN) or aluminium nitride (A1N)
A first mask layer 220 is provided over the semiconductor layer 210, for examplethe first mask layer 220 is formed of silicon dioxide, although there are suitable alternative materials for this layer e.g. silicon nitride, and is deposited at an approximately uniform thickness of 200 nanometres. A thicker layer, for example up to 600nm, can be used. This can be by plasma-enhanced chemical vapour deposition (PECVD) or thermal evaporation or sputtering or electron beam evaporation.
A second mask layer 230, comprising a metal which in this case is nickel, is provided over the first mask layer 220. This can be by thermal evaporation or sputtering or electron beam evaporation. In this step, a nickel layer of approximately uniform thickness in the range 5 to 50 nanometres, preferably 5 to 25nm, is formed and then annealed under flowing nitrogen (N2), at a temperature in the range 600 to 900, preferably 700 to 850 degrees Celsius. The duration of the annealing process is between 1 and 10 minutes, resulting in formation from the nickel layer of a layer 230 comprising self-assembled nickel islands 23 1 distributed irregularly over the first mask layer 220 as shown in Figure lb. Each of the nickel islands 23 1 covers a respective, approximately circular, area of the upper surface of first mask layer 220 which is, typically, no less than 100 nanometres in diameter and no more than 1500 nanometres in diameter.
In order to increase the size of the nickel islands, a second thin nickel film is deposited on the top of the formed nickel islands, which covers both the nickel islands 23 1 and the exposed areas of the first mask layer 220 between the nickel islands. The second nickel film is then annealed at a high temperature, generally in the same temperature range and time period range as the annealing of the first nickel layer. The result of this is that the second layer of nickel 232 collects on the surface, i.e. the sides and the top, of the nickel islands 23 1 , thereby increasing the size of the nickel islands to form larger islands 233. Generally no new nickel islands are formed in the second coating and annealing step. Of course, the second deposited nickel film and the time and temperature at which it is annealed can be different to those done in the first time, respectively. Furthermore, the nickel-deposition and the subsequent annealing processes can be repeated one or more further times to increase the size of the islands to the required size to act as the second mask layer.
Then the second mask layer 230 can act as a mask for etching the underlying Si02 layer, in which the nickel islands 233 mask areas of the underlying Si02 layer and the spaces between the nickel islands leave exposed areas of the Si02 layer, defining which areas of the underlying Si02 layer will be etched.
With reference to Figure lc, the first mask layer 220 is etched through using CHF3 or SF6 in a reactive ion etching (RIE) process using the metal islands 233 of the second mask layer 230 as a mask. This step provides nano-pillars (also referred to as nano- rods) 240 of silicon dioxide distributed irregularly over the GaN layer 210, each comprising a respective part 221 of the first mask layer 220 and a respective nickel island 233. Each nano-rod 240 corresponds to a respective nickel island, having a diameter that is approximately the same as the diameter of the surface area covered its respective nickel island. The nano-pillars 240 resulting from the previous step serve to mask some areas of the GaN layer 210, and to define which areas (i.e. those exposed areas in the spaces between the nano-pillars 240) of the GaN layer 210 will be etched.
Referring to Figure Id, at the next step the GaN layer 210 is etched, for example by inductively coupled plasma etching, with the nano-pillars 240 that were formed in the previous steps used as a mask. This step involves etching though the GaN layer 210, such as shown in Figure Id, or partly through the GaN layer 210. This step results in a nano-pillar structure, as shown in Figure I d, in which nano-pillars 250 extend upwards from the sapphire substrate 205, each nano-pillar 250 comprising a respective part 21 1 of the GaN layer 210, a part 221 of the first mask layer 220, and a metal island 233 from the second mask layer 230. Therefore the etching of this step produces exposed surfaces 250a of the GaN, which comprise the sides of the nano- pillars 250. The diameter of each nano-pillar 250 is approximately constant from top to bottom, being approximately the same as the diameter of the surface area covered by its respective nickel island 233, although in practice some tapering of the nano- pillars generally occurs.
Referring to Figure l e, the nickel islands 233 forming the second mask layer 230 are then removed, leading to the nano-pillar 260 comprising a respective part 21 1 of the GaN layer 210, a part 221 of the first mask layer 220. This can be done by wet etching using hydrochloric acid (HC1) or nitric acid (HN03). This leaves each nano-pillar comprising mainly a GaN column 21 1 with a Si02 cap 221 on its top end.
Referring to Figure If, the GaN nano-rod array is used as a template for deposition of GaN 270 onto the sides 250a of the GaN columns 21 1 by metalorganic chemical vapour deposition (MOCVD) or MBE or HVPE for overgrowth. The re-growth starts on the sidewall of GaN nano-rod (firstly laterally and then vertically), where the GaN is exposed. This forms layers 271 on the sides of the nano-pillars. These grow outwards from the pillars and towards each other until they meet where the layers are thickest. This then prevents further growth in the volume 273 below the meeting point 272, and growth continues in the volume 274 above the meeting point. This leaves, in some cases, the volume 273 as hollow gaps or cavities around the base of each of the nano-pillars. These gaps may be interconnected to form a cavity, which is labyrinthine in form and extends between all, or substantially all of the nano-pillars . The Si02 masks 221 on the top of nano-pillar will prevent GaN growth on their top. Referring to Figure lg, when the growing face of the GaN reaches above the top of the Si02 nano-masks 221 the GaN re-growth progresses laterally over the top of the Si02 nano-mask, and eventually coalesces to form a continuous layer extending over the top of the nano-mask, and having a smooth surface 271 as shown in Figure lh. In theory, all the dislocations originating from the template (i.e. in the nano-pillars 260) are effectively blocked. On the other hand, of course, due to the nature of the lateral overgrowth, the dislocations in the window regions (i.e., the regions directly above the gaps) will be eliminated or the number of the dislocation will be very low. Therefore, the invention offers dual reduction in the number of dislocations.
Once the growth has been completed, the substrate 205 can either be removed or still remain unremoved. In the case of the substrate 205 being removed, removal of the substrate will generally include removal of the bottom end of the nano-pillars 260. This can be made easier by the presence of the hollow volume 273 around the base of the nano-pillars. The bases of the nano-pillars 260 may be removed up to a level which is below the meeting point 272 i.e. below the top of the hollow volume 273. This can result in a very uniform structure with low levels of strain.
Figure 2 shows an array of GaN nanorods, each with a diameter of ~200nm, which are achieved by the process described above but with only a single coating and annealing of nickel.
Figure 3 shows an array of GaN nanorods, each with a diameter of about 500-700nm, which are achieved by the process described above with two coatings of nickel each being annealed as described above. Referring to Figure 4 a further improvement in crystal quality has been achieved using the method described above with a double nickel layer. In particular the FWHMs of XRD rocking curve have been further reduced compared to the crystal formed with a single annealed nickel layer. It is also very effective to extend the approach described above to the overgrowth of AlGaN on a GaN nano-pillar structure, without worrying about the coalescence issue, as the gaps between the GaN nano-rods are on a nano-meter scale, which is much narrower than those in the Si02 masks generally used in the conventional ELOG mentioned above . In addition, due to the residual voids left in the gaps between nano- rods during the overgrowth, the cracking issue of AlGaN on GaN which generally happens in conventional Ill-nitride growth can be eliminated.
In a further embodiment the nano-pillar array is produced as described above, except that semiconductor layer 210 includes a number of quantum-well layers as described in WO2010/146390. This results in each of the nano-pillars including quantum well layers. The gaps between the nano-pillars are filled with wavelength conversion material and/or metal nano-particles, and contact layers are applied so that the device forms an LED.
It will be appreciated that other embodiments of the invention will vary from those described above . The method is applicable to different combinations of substrate, nano-pillar structure material, and grown semiconductor material, but is mostly applicable where the substrate and grown semiconductor have sufficiently different lattice structures for the formation of dislocations in the semiconductor lattice structure to be a problem. Obviously the exact scale of the structure can be varied, though it is a particular advantage of the method that structure can be produced on a small scale . Also the first and second metal layers can each comprise different metals or alloys. For example each layer can comprise chromium, tungsten or titanium rather than nickel, or an alloy of any two or more of those metals. These are appropriate as they have relatively high melting points.

Claims

Claims
1. A method of making a semiconductor device comprising:
(i) providing a semiconductor wafer having a semiconductor layer;
(ii) forming a first mask layer over the semiconductor layer;
(iii) forming a metal second mask layer over the first mask layer;
(iv) annealing the second mask layer to form islands;
(v) forming a second metal layer over the islands;
(vi) annealing the second metal layer thereby to increase the size of the islands; and
(vii) etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.
2. A method according to claim 1 wherein the second metal layer is of the same metal or metal alloy as the second mask layer.
3. A method according to claim 1 or claim 2 further comprising removing the islands before growing the semiconductor material.
4. A method according to any foregoing claim wherein a cap formed from one of the mask layers is left on the top of each of the pillars during the growing of the semiconductor material.
5. A method according to any foregoing claim wherein the semiconductor layer is supported on a substrate .
6. A method according to claim 5 wherein the substrate comprises at least one of sapphire, silicon and silicon carbide .
7. A method according to any foregoing claim wherein the semiconductor layer is formed of a group III nitride .
8. A method according to any foregoing claim wherein the first mask layer is formed of at least one of silicon dioxide and silicon nitride.
9. A method according to any foregoing claim wherein the second mask layer is formed of nickel.
10. A method according to any foregoing claim further comprising growing semiconductor material between the pillars and then over the tops of the pillars.
1 1. A method according to claim 10 wherein the growing step leaves gaps around the bases of the pillars.
12. A method according to claim 1 1 wherein the semiconductor material grown on adjacent pillars meets at a level spaced from the substrate, so that the gaps are left below that level.
13. A method of making a semiconductor device substantially as described herein with reference to the accompanying drawings.
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