JP2009167057A - Method for manufacturing nitride semiconductor substrate - Google Patents
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本発明は、窒化物半導体基板の製造方法に関し、更に詳しくは、窒化物半導体、例えば、InXAlYGa1−X−YN(0≦X、0≦Y、0≦X+Y≦1)からなるオフ角ばらつきの小さい自立基板を製造できる窒化物半導体基板の製造方法に関する。 The present invention relates to a method of manufacturing a nitride semiconductor substrate, and more particularly, from a nitride semiconductor such as In X Al Y Ga 1-XY N (0 ≦ X, 0 ≦ Y, 0 ≦ X + Y ≦ 1). The present invention relates to a method for manufacturing a nitride semiconductor substrate capable of manufacturing a self-standing substrate having a small off-angle variation.
窒化ガリウム(GaN)、窒化インジウムガリウム(InGaN)、窒化ガリウムアルミニウム(GaAlN)等の窒化物系半導体材料は、禁制帯幅が大きく、バンド間遷移も直接遷移型であるため、短波長発光素子への適用が盛んに検討されている。また、電子の飽和ドリフト速度が大きいこと、ヘテロ接合による2次元キャリアガスの利用が可能なこと等から、電子素子への応用も期待されている。 Nitride-based semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and gallium aluminum nitride (GaAlN) have a large forbidden band and a direct transition type between bands. The application of is being studied actively. In addition, application to electronic devices is also expected due to the high saturation drift velocity of electrons and the use of two-dimensional carrier gas by heterojunction.
窒化物半導体基板は、窒素の蒸気圧が非常に高いためにボート法や引き上げ法などにみられる融液からのバルク状結晶成長が極めて困難であり、高圧を印加することでV族元素の乖離を抑止する原理を利用したこれらの方法からは、ごく小さな基板しか得られていない。
この理由により、窒化物半導体基板の製造方法としては、図8に示すように、一般にサファイア基板やシリコン基板あるいはガリウム砒素基板などの窒化物半導体とは異なる異種基板21上に、主に気相成長法を用いて窒化物半導体層22をヘテロエピタキシャル成長させた後(図8(a))、剥離や研磨あるいはエッチング等の手法を用いて異種基板21を除去し(図8(b))、異種基板21上に形成した前記窒化物半導体層22のみを残し、窒化物半導体層22の表裏面を研磨等することで、いわゆる「自立基板」を得ている(図8(c))。なお、図8における矢印は、結晶の主たる面方位を示している。結晶の主たる面方位とは、表面に最も近い低指数面の方位のことで、例えば、サファイア、GaN等の六方晶系で言えば、C面、A面、またはM面の方位のことである。
Nitride semiconductor substrates have extremely high vapor pressures of nitrogen, making it difficult to grow bulk crystals from melts found in boating and pulling methods. Only a very small substrate can be obtained from these methods using the principle of depressing.
For this reason, as a method for manufacturing a nitride semiconductor substrate, as shown in FIG. 8, generally, vapor phase growth is mainly performed on a heterogeneous substrate 21 different from a nitride semiconductor such as a sapphire substrate, a silicon substrate, or a gallium arsenide substrate. After heteroepitaxial growth of the nitride semiconductor layer 22 using the method (FIG. 8A), the heterogeneous substrate 21 is removed using a technique such as peeling, polishing or etching (FIG. 8B), and the heterogeneous substrate is removed. The so-called “self-supporting substrate” is obtained by leaving only the nitride semiconductor layer 22 formed on the surface 21 and polishing the front and back surfaces of the nitride semiconductor layer 22 (FIG. 8C). In addition, the arrow in FIG. 8 has shown the main surface orientation of the crystal | crystallization. The main plane orientation of the crystal is the orientation of the low index plane closest to the surface. For example, in the hexagonal system such as sapphire or GaN, the orientation is the C plane, A plane, or M plane. .
このようにして自立基板を作製する具体的な方法としては、例えば特許文献1に記載されているような方法が知られている。
また、異種基板を除去した後、残った窒化物半導体層から1枚のみの自立基板を取得する場合もあるが、窒化物半導体層を厚くエピタキシャル成長させてスライスすることにより複数枚の自立基板を取得する場合もある。さらに得られた窒化物半導体自立基板を種結晶として、その上に厚くエピタキシャル成長させてスライスすることにより複数枚の自立基板を取得する場合もある。
本明細書でいう自立基板とは、これらのうちいずれの場合も含むものである。
As a specific method for producing a self-standing substrate in this manner, a method as described in Patent Document 1, for example, is known.
In some cases, after removing the dissimilar substrate, only one free-standing substrate may be obtained from the remaining nitride semiconductor layer, but a plurality of free-standing substrates are obtained by epitaxially growing the nitride semiconductor layer thickly and slicing. There is also a case. Further, there are cases where a plurality of free-standing substrates are obtained by using the obtained nitride semiconductor free-standing substrate as a seed crystal and epitaxially growing it thickly and slicing it.
The self-standing substrate as used in this specification includes any of these cases.
窒化物半導体層の成長方法については、サファイア基板やシリコン基板あるいはガリウム砒素基板などの窒化物半導体とは異なる異種基板上に、窒化物半導体層をヘテロエピタキシャル成長させるため、成長の開始当初は、いわゆるステップフローモードではなく、3次元島状成長モードで結晶成長が進行する。このため、こうして得られた窒化物半導体層は、109〜1010cm−2もの転位密度を有している。この欠陥は、AlGaN系デバイス、特にLDや紫外発光LEDを製作する上で障害となる。 Regarding the growth method of the nitride semiconductor layer, since the nitride semiconductor layer is heteroepitaxially grown on a heterogeneous substrate different from the nitride semiconductor, such as a sapphire substrate, a silicon substrate, or a gallium arsenide substrate, a so-called step is started at the beginning of the growth. Crystal growth proceeds not in the flow mode but in the three-dimensional island growth mode. For this reason, the nitride semiconductor layer obtained in this way has a dislocation density of 10 9 to 10 10 cm −2 . This defect becomes an obstacle in manufacturing an AlGaN-based device, particularly an LD or an ultraviolet light emitting LED.
近年、このような欠陥の密度を低減する方法として、ELOや、FIELO、ペンデオエピタキシーといった成長技術が報告された。これらの成長技術は、サファイア等の基板上に成長させたGaN上に、SiO2等でパターニングされたマスクを形成し、マスクの窓部からさらにGaN結晶を選択的に成長させて、マスク上をGaNがラテラル成長で覆うようにすることで、下地結晶からの転位の伝播を防ぐものである。これらの成長技術の
開発により、GaN中の転位密度は107cm−2台程度にまで、飛躍的に低減させることができるようになった。
In recent years, growth techniques such as ELO, FIELO, and pendeo epitaxy have been reported as methods for reducing the density of such defects. In these growth techniques, a mask patterned with SiO 2 or the like is formed on GaN grown on a substrate such as sapphire, and further a GaN crystal is selectively grown from the window portion of the mask. By covering GaN with lateral growth, the propagation of dislocations from the underlying crystal is prevented. With the development of these growth techniques, the dislocation density in GaN can be drastically reduced to about 10 7 cm −2 .
更に、サファイア基板等の異種基板上に転位密度を低減したGaN層を厚くエピ成長させ、成長後に下地から剥離して、GaN層を自立したGaN基板として用いる方法が種々提案されている。例えば、前述のELO技術を用いてサファイア基板上にGaN層を形成した後、サファイア基板をエッチング等により除去し、GaN自立基板を得ることが提案されている。
また、VAS(Void-assisted Separation:例えば、非特許文献1)法や、DEEP(Dislocation Elimi nation by the Epi-growth with inverted-Pyramidal pits:例えば
、非特許文献2)法などが公開されている。VASは、サファイア等の基板上で、網目構造のTiN薄膜を介してGaNを成長することで、下地基板とGaN層の界面にボイドを形成し、GaN基板の剥離と低転位化を同時に可能にしたものである。また、DEEPは、エッチング等で除去が可能なGaAs基板上にパターニングしたSiN等のマスクを用いてGaNを成長させ、結晶表面に故意にファセット面で囲まれたピットを複数形成し、前記ピットの底部に転位を集積させることで、その他の領域を低転位化するものである。
Further, various methods have been proposed in which a GaN layer with a reduced dislocation density is epitaxially grown on a dissimilar substrate such as a sapphire substrate, and the GaN layer is peeled off from the substrate after growth and used as a self-supporting GaN substrate. For example, it has been proposed to form a GaN layer on a sapphire substrate using the above-described ELO technique, and then remove the sapphire substrate by etching or the like to obtain a GaN free-standing substrate.
In addition, VAS (Void-assisted Separation: for example, Non-Patent Document 1) method, DEEP (Dislocation Elimi nation by the Epi-growth with inverted-Pyramidal pits: For example, Non-Patent Document 2) method and the like are disclosed. VAS grows GaN on a substrate such as sapphire via a TiN thin film with a network structure, thereby forming a void at the interface between the base substrate and the GaN layer, and simultaneously enabling peeling and low dislocation of the GaN substrate. It is a thing. Further, DEEP grows GaN using a mask such as SiN patterned on a GaAs substrate that can be removed by etching or the like to form a plurality of pits deliberately surrounded by facet surfaces on the crystal surface. By accumulating dislocations at the bottom, other regions are reduced in dislocation.
しかしながら、上述した従来方法で作製した窒化物半導体層22には、表裏面に欠陥密度差が存在することから、結晶格子が歪み内部応力が生じて、下地基板21から剥離した後の窒化物半導体層22は、どのようにしても裏面22bが凸形状になるように反ってしまう(図8(b))。そのように反った窒化物半導体層22は、研磨などで平坦な加工を施したとしても、表面22aの面内の各位置で面方位が一様な方向に向いていないため、オフ角が面内でばらついてしまうという問題が発生する(図8(c))。ここでいう「オフ角」とは、「表面の各位置の法線の、主たる面方位からのずれの角度」(あるいは「表面と、主たる結晶面とのなす角度」)のことであり、「オフ角がばらつく」というのは、「表面の各位置の法線の、主たる面方位からずれの角度が一様にならず、面内の位置によって、ずれの角度が異なってしまう」ことである。
面内のオフ角がばらつくと、その上に形成した発光素子デバイスの発光波長のばらつきに大きな影響を与え、著しく歩留まりを低下させてしまう。
さらに面内でオフ角がばらついている窒化物半導体自立基板23(図8(c))を種結晶として、その上にエピタキシャル成長しても、配向性は引き継がれるので、エピタキシャル層を厚く成長してスライスして得られる自立基板も、結局オフ角がばらついてしまうことになる。また、面方位が一様に揃っている窒化物半導体基板上に成長しても、貫通転位の減少などによる表裏面の欠陥密度差により、再び反ってしまうため、オフ角ばらつきの原因となる。
However, since the nitride semiconductor layer 22 manufactured by the above-described conventional method has a defect density difference between the front and back surfaces, the nitride semiconductor after the crystal lattice is distorted and the internal stress is generated and peels from the base substrate 21. The layer 22 is warped so that the back surface 22b has a convex shape in any way (FIG. 8B). Even if the nitride semiconductor layer 22 warped as described above is flattened by polishing or the like, the off-angle is a surface because the plane orientation is not oriented in a uniform direction at each position in the surface 22a. There arises a problem that it varies within the range (FIG. 8C). The “off angle” here means “the angle of deviation of the normal of each position on the surface from the main plane orientation” (or “the angle between the surface and the main crystal plane”), “The off-angle varies” means that the angle of deviation of the normal of each position on the surface from the main surface orientation is not uniform, and the angle of deviation varies depending on the position in the surface. .
If the in-plane off-angle varies, it greatly affects the variation in the emission wavelength of the light-emitting element device formed thereon, and the yield is significantly reduced.
Further, even when epitaxial growth is performed on a nitride semiconductor free-standing substrate 23 (FIG. 8C) having an off-angle variation in the plane as a seed crystal, the orientation is inherited, so that the epitaxial layer is grown thickly. The free-standing substrate obtained by slicing will also vary in off-angle. Further, even when grown on a nitride semiconductor substrate having a uniform plane orientation, it is warped again due to a defect density difference between the front and back surfaces due to a decrease in threading dislocations, etc., which causes off-angle variation.
本発明は、上記課題を解決し、オフ角ばらつきの小さい、窒化物半導体基板を製造することができる窒化物半導体基板の製造方法を提供することにある。 An object of the present invention is to solve the above-described problems and to provide a method for manufacturing a nitride semiconductor substrate capable of manufacturing a nitride semiconductor substrate with small off-angle variation.
上記課題を解決するために、本発明は次のように構成されている。
本発明の第1の態様は、下地基板上に窒化物半導体層を形成し、前記下地基板から分離した前記窒化物半導体層を用いて自立した窒化物半導体基板を作製する窒化物半導体基板
の製造方法において、前記下地基板の反り量を、前記下地基板の中心位置と前記下地基板の中心から距離Rの位置とにおける結晶成長面である表面の高さの差(ただし、前記表面の高さの差の正負を、前記下地基板の表面が凸形状の場合をマイナス、凹形状の場合をプラスとする)と定義したとき、前記下地基板は、R=25mmに換算した場合の前記反り量が−100μm以上−20μm以下の範囲にあることを特徴とする窒化物半導体基板の製造方法である。
In order to solve the above problems, the present invention is configured as follows.
According to a first aspect of the present invention, a nitride semiconductor substrate is formed by forming a nitride semiconductor layer on a base substrate and using the nitride semiconductor layer separated from the base substrate to produce a self-supporting nitride semiconductor substrate. In the method, the amount of warpage of the base substrate is determined by a difference in height of a surface that is a crystal growth surface between a center position of the base substrate and a position of a distance R from the center of the base substrate (however, When the difference is defined as negative if the surface of the base substrate has a convex shape and positive if the surface of the base substrate is concave, the base substrate has a warpage amount of −25 mm when converted to R = 25 mm. A method for manufacturing a nitride semiconductor substrate, which is in a range of 100 μm or more and −20 μm or less.
本発明の第2の態様は、第1の態様の窒化物半導体基板の製造方法において、前記反りを有する前記下地基板の表面は、面内でオフ角が一様に揃っていることを特徴とする。 According to a second aspect of the present invention, in the method for manufacturing a nitride semiconductor substrate according to the first aspect, the surface of the base substrate having the warp has a uniform off-angle in a plane. To do.
本発明の第3の態様は、第1の態様又は第2の態様の窒化物半導体基板の製造方法において、前記下地基板は、サファイア基板、窒化物半導体基板、シリコン基板またはガリウム砒素基板であることを特徴とする。 According to a third aspect of the present invention, in the method for manufacturing a nitride semiconductor substrate according to the first aspect or the second aspect, the base substrate is a sapphire substrate, a nitride semiconductor substrate, a silicon substrate, or a gallium arsenide substrate. It is characterized by.
本発明によれば、クラックが発生せず、かつオフ角ばらつきの小さい窒化物半導体の自立基板が得られる。また、得られた窒化物半導体自立基板上にLEDやLDなどの半導体発光素子を作製した場合の歩留りを著しく向上させることができる。 According to the present invention, it is possible to obtain a nitride semiconductor free-standing substrate in which cracks do not occur and off-angle variation is small. Moreover, the yield in the case where semiconductor light emitting devices such as LEDs and LDs are fabricated on the obtained nitride semiconductor free-standing substrate can be significantly improved.
以下、本発明に係る窒化物半導体基板の製造方法の実施形態を図面を用いて説明する。 Hereinafter, embodiments of a method for manufacturing a nitride semiconductor substrate according to the present invention will be described with reference to the drawings.
図1は、本実施形態に係る窒化物半導体基板の製造方法の工程を概略的に示す工程図である。
本実施形態の窒化物半導体基板の製造方法は、まず、下地基板1を準備し、下地基板上1に窒化物半導体層2を形成する(図1(a))。
下地基板1には、サファイア基板、シリコン基板、ガリウム砒素基板などの窒化物半導体とは異なる異種基板、あるいは窒化物半導体基板を用いる。窒化物半導体層2は、例えば、InXAlYGa1−X−YN(0≦X、0≦Y、0≦X+Y≦1)層などである。窒化物半導体層2の形成方法には、有機金属気相成長法(MOVPE法)やハイドライド気相成長法(HVPE法)、或いはこれらを組み合わせた気相成長法などが用いられる。
FIG. 1 is a process diagram schematically showing the steps of the method for manufacturing a nitride semiconductor substrate according to the present embodiment.
In the method for manufacturing a nitride semiconductor substrate according to the present embodiment, first, a base substrate 1 is prepared, and a nitride semiconductor layer 2 is formed on the base substrate 1 (FIG. 1A).
As the base substrate 1, a heterogeneous substrate different from a nitride semiconductor, such as a sapphire substrate, a silicon substrate, or a gallium arsenide substrate, or a nitride semiconductor substrate is used. Nitride semiconductor layer 2 is, for example, In X Al Y Ga 1- X-Y N (0 ≦ X, 0 ≦ Y, 0 ≦ X + Y ≦ 1) layer, and the like. As a method for forming the nitride semiconductor layer 2, a metal organic vapor phase epitaxy method (MOVPE method), a hydride vapor phase epitaxy method (HVPE method), or a vapor phase epitaxy method combining these is used.
次に、下地基板1上に形成した窒化物半導体層2を、下地基板1から分離する(図1(b))。分離方法(除去方法)は、剥離(図示例)のほか、研磨、エッチング、レーザー照射などの方法を用いてもよい。 Next, the nitride semiconductor layer 2 formed on the base substrate 1 is separated from the base substrate 1 (FIG. 1B). As a separation method (removal method), in addition to peeling (illustrated example), methods such as polishing, etching, and laser irradiation may be used.
最後に、分離された窒化物半導体層2の表面2a及び裏面2bを研磨し(図1(b)の破線部分を残し)、洗浄などすることで、自立した窒化物半導体基板3を作製する(図1(c))。なお、図1における矢印は、結晶の主たる面方位を示している。
自立した窒化物半導体基板3は、分離された窒化物半導体層2から1枚のみ取得しても、窒化物半導体層3を厚くエピタキシャル成長させてスライスすることにより複数枚の窒化物半導体自立基板を取得してもよい。なお、窒化物半導体の「自立基板」は、搬送などの基板処理が可能な強度を有する基板であって、基板の厚さは、例えば200μm以上が好ましい。
Finally, the front surface 2a and the back surface 2b of the separated nitride semiconductor layer 2 are polished (leaving the broken line portion in FIG. 1B), washed, etc., thereby producing a self-supporting nitride semiconductor substrate 3 ( FIG. 1 (c)). In addition, the arrow in FIG. 1 has shown the main surface orientation of the crystal | crystallization.
Even if only a single nitride semiconductor substrate 3 is obtained from the separated nitride semiconductor layer 2, a plurality of nitride semiconductor free-standing substrates can be obtained by epitaxially growing the nitride semiconductor layer 3 thickly and slicing. May be. Note that the “self-standing substrate” of nitride semiconductor is a substrate having a strength that allows substrate processing such as transportation, and the thickness of the substrate is preferably 200 μm or more, for example.
上記実施形態の製造方法で特徴とするところは、窒化物半導体層2を形成するための下地となる下地基板1、特に下地基板1の反り量を所定範囲に規定したことにある。
下地基板1の反り量は、図2に示すように、下地基板1の中心位置と下地基板1の中心から距離Rの位置とにおける結晶成長面である表面1aの高さの差で定義した。ただし、下地基板1の表面1aの高さの差である反り量の正負は、下地基板1の表面1aが凸形状
の場合(図2(a))をマイナス、凹形状の場合(図2(b))をプラスとする。
このとき、下地基板1として、R=25mmに換算した場合の前記反り量が−100μm以上−20μm以下の範囲にある表面が凸形状の基板を用いる。
ここで、「R=25mmに換算した場合の前記反り量が−100μm以上−20μm以下の範囲」とは、言い換えれば「下地基板1を2インチ(=50.8mm)径に規格化し
たときの、反り量が−100μm以上−20μm以下の範囲である」という意味であって、下地基板の径に対応して、例えば、もっと大きい場合には、反り量の数値(絶対値)は、後述する反りのキャンセル効果を発揮できるように、より大きくなる。
The manufacturing method of the above embodiment is characterized in that the warpage amount of the base substrate 1, which is the base for forming the nitride semiconductor layer 2, in particular, the base substrate 1 is defined within a predetermined range.
As shown in FIG. 2, the amount of warpage of the base substrate 1 was defined by the difference in height between the surface 1a, which is the crystal growth surface, at the center position of the base substrate 1 and the distance R from the center of the base substrate 1. However, the amount of warpage, which is the difference in height of the surface 1a of the base substrate 1, is negative when the surface 1a of the base substrate 1 is convex (FIG. 2 (a)), and when it is concave (FIG. 2 ( b)) shall be positive.
At this time, a substrate having a convex surface is used as the base substrate 1 when the amount of warpage when converted to R = 25 mm is in the range of −100 μm to −20 μm.
Here, “the range in which the amount of warpage when converted to R = 25 mm is −100 μm to −20 μm” is, in other words, “when the base substrate 1 is standardized to a diameter of 2 inches (= 50.8 mm)”. The amount of warpage is in the range of −100 μm or more and −20 μm or less ”, and the numerical value (absolute value) of the amount of warpage will be described later when the warpage amount is larger, for example, corresponding to the diameter of the base substrate. It becomes larger so that the warp canceling effect can be exhibited.
下地基板1上に形成した窒化物半導体層2は、その表面2aの欠陥密度が小さく、裏面2bの欠陥密度が大きいため、必ず表面2aが凹形状に反るように内部応力が働く。
従って、図8(a)に示す従来の下地基板21のように、下地基板の表面が平坦で反りがない場合、下地基板21から分離された窒化物半導体層22は、図8(b)に示すように、その表面22aが凹形状に反ってしまう。このため、下地基板21上の窒化物半導体層22の主たる面方位が一様な方向に揃って形成されていても、分離された窒化物半導体層22は、欠陥密度差に起因した内部応力により歪んで表面22aが凹形状に反ってしまい、研磨などで平坦な加工を施した窒化物半導体自立基板23の表面内の各位置で面方位が一様な方向に向かず、オフ角が面内でばらついてしまう。
Since the nitride semiconductor layer 2 formed on the base substrate 1 has a low defect density on the front surface 2a and a high defect density on the back surface 2b, internal stress always acts so that the front surface 2a warps in a concave shape.
Therefore, as in the conventional base substrate 21 shown in FIG. 8A, when the surface of the base substrate is flat and has no warp, the nitride semiconductor layer 22 separated from the base substrate 21 is shown in FIG. As shown, the surface 22a warps in a concave shape. For this reason, even if the main plane orientation of the nitride semiconductor layer 22 on the base substrate 21 is formed in a uniform direction, the separated nitride semiconductor layer 22 is caused by internal stress due to the difference in defect density. The surface 22a is warped in a concave shape due to distortion, and the plane orientation is not directed to a uniform direction at each position within the surface of the nitride semiconductor free-standing substrate 23 that has been flattened by polishing or the like, and the off angle is in-plane It will vary.
そこで、本実施形態では、分離後の窒化物半導体層2に生じる凹形状の反りとは、反対向きで絶対値が同程度の凸形状の反りを有する下地基板1を用いることにより、分離後の窒化物半導体層2に欠陥密度差に起因して生じる凹形状の反りをキャンセルすること(打ち消すこと)ができ、図1(b)に示すように主たる面方位はほぼ一様に揃い、分離後の窒化物半導体層2の表裏面を研磨して作製される自立した窒化物半導体基板3も面内のオフ角ばらつきは小さくなる。すなわち、下地基板1の反り量を規定することによって、エピタキシャル成長して分離した後の窒化物半導体層2の反り量を調整・制御でき、結果としてオフ角ばらつきの小さい、面方位の一様に揃った窒化物半導体基板3を作製できる。また、反りをキャンセルするように調整しているので、分離後の窒化物半導体層2の反りは少なく、表裏面を研磨する研磨量も少なくて済み、分離後の窒化物半導体層2を無駄なく有効に活用できると共に、研磨加工の時間等も削減できる。 Therefore, in the present embodiment, by using the base substrate 1 having the convex warpage in the opposite direction to the concave warpage generated in the nitride semiconductor layer 2 after the separation, The concave warpage caused by the defect density difference in the nitride semiconductor layer 2 can be canceled (cancelled), and the main plane orientations are almost uniform as shown in FIG. The self-standing nitride semiconductor substrate 3 produced by polishing the front and back surfaces of the nitride semiconductor layer 2 also has less in-plane off-angle variation. That is, by defining the warpage amount of the base substrate 1, the warpage amount of the nitride semiconductor layer 2 after the epitaxial growth and separation can be adjusted and controlled. As a result, the surface orientation is uniform with small off-angle variation. The nitride semiconductor substrate 3 can be produced. Further, since the warpage is adjusted so as to cancel, the warpage of the nitride semiconductor layer 2 after separation is small, the amount of polishing for polishing the front and back surfaces is small, and the nitride semiconductor layer 2 after separation is not wasted. It can be used effectively and the polishing time can be reduced.
ただし、下地基板1は、その表面が凸形状に反っていた方がいいと言っても、大きく反り過ぎていると、下地基板1上に窒化物半導体層2をエピタキシャル成長する際、面内で温度の不均一が生じ、表面にピットが形成されるなどの不具合を生じる。これを防止するためには、R=25mmに換算した場合の下地基板1の反り量を−100μm以上とするのが好ましい。また、後述するように、得られた窒化物半導体自立基板3上にLEDやLDなどの半導体発光素子を作製した場合の歩留りなどを考慮すると、R=25mmの場合の下地基板1の反り量を−20μm以下とするのが好ましい。 However, even if the surface of the base substrate 1 is preferably warped in a convex shape, if the base substrate 1 is warped too much, the temperature of the nitride semiconductor layer 2 is epitaxially grown on the base substrate 1 in the plane. Non-uniformity occurs, resulting in defects such as formation of pits on the surface. In order to prevent this, it is preferable that the amount of warpage of the base substrate 1 when converted to R = 25 mm is −100 μm or more. As will be described later, in consideration of the yield when a semiconductor light emitting device such as an LED or LD is fabricated on the obtained nitride semiconductor free-standing substrate 3, the amount of warpage of the base substrate 1 when R = 25 mm is set. It is preferable to be −20 μm or less.
下地基板1上にエピタキシャル成長される窒化物半導体層2は、図1(a)に示すように、下地基板1の配向性が引き継がれる。このため、分離後の窒化物半導体層2の欠陥密度差に起因する反りを下地基板1の反りによってキャンセルさせて、図1(b)に示すように、層内で主たる面方位がほぼ平行に揃った窒化物半導体層2を分離するには、前記反りを有する下地基板1の表面は、面内でオフ角が一様に揃っていることが好ましい。ここで、下地基板1の表面内でオフ角が一様に揃っているとは、下地基板1表面の各位置において、表面の法線と主たる面方位とのずれがほぼ一致していること、即ち、下地基板1の表面内の各位置で、主たる面方位が下地基板1の表面に垂直な方向から±0.3°程度の
ばらつきの範囲内にあることをいう。
また、下地基板が平板状で反りがなく、面内でオフ角がほぼ揃っている場合(図8(a)の下地基板21のような場合)には、この下地基板を多少、撓ませることが可能である
ならば、上記反り量の範囲の凸球面を有する基材上に、この下地基板を撓ませて密着させた状態で接着剤等により固定したものを、下地基板として用いてもよい。
The nitride semiconductor layer 2 epitaxially grown on the base substrate 1 inherits the orientation of the base substrate 1 as shown in FIG. For this reason, the warp due to the defect density difference of the nitride semiconductor layer 2 after the separation is canceled by the warp of the base substrate 1, and the main plane orientations in the layer are almost parallel as shown in FIG. In order to separate the uniform nitride semiconductor layers 2, it is preferable that the surface of the base substrate 1 having the warp has a uniform off angle in the plane. Here, that the off-angles are uniformly aligned within the surface of the base substrate 1 means that the deviation between the surface normal and the main plane orientation substantially coincides at each position on the surface of the base substrate 1. That is, it means that the main plane orientation is within a range of variation of about ± 0.3 ° from the direction perpendicular to the surface of the base substrate 1 at each position in the surface of the base substrate 1.
In addition, when the base substrate is flat and has no warpage, and the off angles are substantially uniform in the plane (such as the base substrate 21 in FIG. 8A), the base substrate is bent slightly. If it is possible, a substrate having a convex spherical surface within the range of the above-described warpage amount and fixed by an adhesive or the like in a state where the substrate is bent and adhered may be used as the substrate. .
次に、本発明の実施例を説明する。 Next, examples of the present invention will be described.
[実施例1]
この実施例1では、種々の反り量を有する直径2インチのサファイア単結晶基板(下地基板)上に、MOVPE法によりGaN層を形成して、サファイア単結晶基板の反りの大きさとGaN層表面のピットとの関係を調べた。
[Example 1]
In Example 1, a GaN layer is formed by a MOVPE method on a sapphire single crystal substrate (underlying substrate) having a diameter of 2 inches and having various warpage amounts. I investigated the relationship with the pit.
まず、サファイア基板をMOVPE成長炉内のサセプタにセットし、1200℃まで昇温して水素雰囲気中で10分間サーマルクリーニングを行った。その後500℃まで降温して、原料としてトリメチルガリウム(TMG)、トリメチルインジウム(TMI)及びアンモニア(NH3)を、キャリアガスとしてH2、N2を含んだ混合ガスを流し、低温InGaN層を20nm形成した。その後、NH3及びH2、N2雰囲気中で1100℃まで昇温して、再びTMGを流して、GaN層を300nm成長した。成長後、NH3とN2雰囲気にて500℃まで降温し、500℃以下になった所で、N2のみで降温し、100℃以下となったところで、サファイア基板を取り出した。 First, the sapphire substrate was set on a susceptor in the MOVPE growth furnace, heated to 1200 ° C., and subjected to thermal cleaning in a hydrogen atmosphere for 10 minutes. Thereafter, the temperature is lowered to 500 ° C., trimethyl gallium (TMG), trimethyl indium (TMI) and ammonia (NH 3 ) are used as raw materials, and a mixed gas containing H 2 and N 2 is supplied as a carrier gas. Formed. Thereafter, the temperature was raised to 1100 ° C. in an atmosphere of NH 3, H 2 , and N 2 , TMG was flowed again, and a GaN layer was grown to 300 nm. After the growth, the temperature was lowered to 500 ° C. in an NH 3 and N 2 atmosphere. When the temperature dropped to 500 ° C. or lower, the temperature was lowered only with N 2 and when the temperature dropped to 100 ° C. or lower, the sapphire substrate was taken out.
本実施例1では、下記の表1に示す凸150μm(反り量−150μm)〜凹20μm(反り量+20μm)までの反り量のサファイア基板を用いた。そして、サファイア基板上に形成したGaN層の表面をノマルスキ光学顕微鏡で観察を行った。その結果、凸反り150μmのものと、凸反り120μmのものに、サファイア基板の端から10mm程度の範囲の全周にわたって、図3に見られるようなピット(黒点状)が密集している様子が見られた。それ以外の反り量のサファイア基板では、ピットは発生しておらず、平坦なGaN膜が得られていた。
以上の結果から、下地基板の反りは、凸反り(反り量がマイナス)に関しては、100μm以下が必要である事が分かった。
From the above results, it has been found that the warpage of the base substrate needs to be 100 μm or less with respect to the convex warpage (the amount of warpage is negative).
[実施例2]
ボイド形成剥離法(Void-assisted Separation Method:VAS法)を用いてサファイ
ア基板上にGaNエピタキシャル層を成長させ、その後、サファイア基板を除去することにより、自立したGaN基板を得て、その評価を行った。
VAS法は、サファイア基板とGaN成長層との間に網目構造を有する窒化チタンの薄膜を挟み込んで結晶成長を行う方法であるが、その詳細は例えば非特許文献1に記載されている。
[Example 2]
A GaN epitaxial layer is grown on the sapphire substrate using the Void-Assisted Separation Method (VAS method), and then the sapphire substrate is removed to obtain a self-supporting GaN substrate for evaluation. It was.
The VAS method is a method of performing crystal growth by sandwiching a titanium nitride thin film having a network structure between a sapphire substrate and a GaN growth layer, and details thereof are described in Non-Patent Document 1, for example.
以下、本実施例2のGaN自立基板の製造方法について説明する。
まず、直径2インチのサファイアC面基板上に、MOVPE法により、トリメチルガリウム(TMG)とNH3を原料として、アンドープGaN層を300nmの厚さに成長させた。次に、このGaNエピタキシャル基板上に、Ti薄膜を20nmの厚さに蒸着し、これを電気炉に入れて、20%のNH3と80%のH2の混合ガスの雰囲気中、1050℃で20分間熱処理を施した。その結果、アンドープGaN層の一部がエッチングされて高密度の空隙が発生してボイド形成GaN層に変化するとともに、Ti薄膜が窒化されて表面にサブミクロンの微細な穴が高密度に形成された穴形成TiN層に変化した。
この基板をHVPE炉に入れ、GaNを全体で800μmの厚さに堆積させた。Gaメタルのボートは900℃に加熱し、基板側は1100℃とし、キャリアガスとして水素5%と窒素95%の混合ガスを用いた。原料ガスとしてHClガスとGaを反応させてGaClを生成させ、同時にアンモニアガスを供給し、成長の開始時にはV/III比が10に
なるように流量を調整した。
この条件で、GaNの核がTiN層上に3次元の島状に成長し、次いで結晶同士が横方向に成長して互いに結合し、表面の平坦化が進行していった。この様子は、成長時間を変えて炉外に取り出した基板表面及び断面を顕微鏡観察することにより確認した。さらに成長時間を延ばして成長を続けた。GaN結晶成長の終了後、HVPE装置を冷却する過程で、GaN層はボイド層を境にサファイアの下地基板から自然に剥離し、800μm厚さ
のGaN自立基板が得られた。
Hereinafter, a method for manufacturing the GaN free-standing substrate of Example 2 will be described.
First, an undoped GaN layer was grown to a thickness of 300 nm on a sapphire C-plane substrate having a diameter of 2 inches by MOVPE using trimethyl gallium (TMG) and NH 3 as raw materials. Next, a Ti thin film is deposited on the GaN epitaxial substrate to a thickness of 20 nm, and this is put in an electric furnace, and at 1050 ° C. in an atmosphere of a mixed gas of 20% NH 3 and 80% H 2. Heat treatment was applied for 20 minutes. As a result, a part of the undoped GaN layer is etched to generate high-density voids and change into a void-formed GaN layer, and the Ti thin film is nitrided to form submicron fine holes at high density on the surface. It changed into the hole formation TiN layer.
This substrate was placed in an HVPE furnace, and GaN was deposited to a total thickness of 800 μm. The Ga metal boat was heated to 900 ° C., the substrate side was set to 1100 ° C., and a mixed gas of 5% hydrogen and 95% nitrogen was used as a carrier gas. HCl gas and Ga were reacted as source gases to generate GaCl, and ammonia gas was supplied at the same time, and the flow rate was adjusted so that the V / III ratio was 10 at the start of growth.
Under these conditions, the GaN nuclei grew in a three-dimensional island shape on the TiN layer, and then the crystals grew laterally and joined to each other, and the surface was flattened. This state was confirmed by observing the substrate surface and cross-section taken out of the furnace with different growth times under a microscope. We continued to grow by extending the growth time. In the process of cooling the HVPE apparatus after completion of the GaN crystal growth, the GaN layer naturally separated from the sapphire base substrate with the void layer as a boundary, and a GaN free-standing substrate having a thickness of 800 μm was obtained.
本実施例において、表1の中の、凸150μm〜凹20μmまでの反り量のサファイア基板を用いて、上記成長を行った。
それぞれ反り量の異なるサファイア基板から得られたGaN自立基板は、表1に示すように、凸形状に100μm反ったサファイア基板(反り量−100μm)上に成長したものが、最も反り量が小さく、逆に凹形状に20μm反ったサファイア基板(反り量+20μm)上に成長したものが、最も反り量が大きい結果となった。また、凸形状に150μm、120μm反ったサファイア基板上に成長したものは、どちらもHVPE成長中に割れてしまった。
In this example, the above growth was performed using a sapphire substrate having a warpage amount of 150 μm to 20 μm in Table 1.
As shown in Table 1, GaN free-standing substrates obtained from sapphire substrates having different warpage amounts grew on a sapphire substrate (warp amount−100 μm) warped to a convex shape, and the warpage amount is the smallest. On the contrary, those grown on a sapphire substrate (warp amount + 20 μm) warped in a concave shape by 20 μm resulted in the largest warp amount. In addition, those grown on a sapphire substrate warped in a convex shape of 150 μm and 120 μm both cracked during HVPE growth.
次に、上記GaN自立基板が平坦になるように、さらに表裏面研磨し、厚さ400μmの平坦なGaN自立基板を得た。
これらGaN自立基板のオフ角を、図4に示すように、面内で5点、すなわち中心及び中心から20mm離れた正方形の四隅の位置でX線回折測定装置(パナリティカル社製)により測定した。その結果、オフ角のばらつきは、表1に示すような結果となった。ばらつき(±度)は、次に述べるように、面内の5点の測定結果から、(|最大オフ角|−|最小オフ角|)/2を計算して、得たものである。
Next, the front and back surfaces were further polished so that the GaN free-standing substrate was flat, and a flat GaN free-standing substrate having a thickness of 400 μm was obtained.
As shown in FIG. 4, the off-angles of these GaN free-standing substrates were measured with an X-ray diffractometer (manufactured by Panalical) at five points in the plane, that is, at the four corners of the square and 20 mm away from the center. . As a result, the variation in off angle was as shown in Table 1. The variation (± degree) is obtained by calculating (| maximum off angle | − | minimum off angle |) / 2 from the measurement results at five points in the plane as described below.
上述したように「オフ角」とは、「表面と、結晶面とのなす角度」の事で、X線回折装置を用いて測ることができる。結晶面の回折角度は、例えばC面の回折角度で、{0002}面などの回折ピーク角度から得ることができる。表面の角度は、入射角=反射角となる位置で生じるX線の表面での全反射現象を利用して得られる回折ピーク角度から得ることができる。
上記結晶面の回折ピーク角度と表面の回折ピーク角度との差を全周囲方向(少なくとも90°おきに4方向)から測定することにより、「表面と、結晶面とのなす角度」すなわちオフ角を決定することができる。オフ角の測定を面内の各点で測定すると、オフ角は、その位置によって、大きさも方向も異なる場合がある。上記5点の測定結果のうち、そのオフ角の大きさが一番大きい値(絶対値)を|最大オフ角|、一番小さい値(絶対値)を|最小オフ角|とした場合、|最大オフ角|−|最小オフ角|(度)が、ばらつきの範囲の大きさを表し、それを2で割って、「±度」という単位にして、「ばらつき」を表現した。また、(|最大オフ角|+|最小オフ角|)/2は、オフ角の中心値となる。
As described above, the “off angle” means “an angle formed between the surface and the crystal plane” and can be measured using an X-ray diffractometer. The diffraction angle of the crystal plane is, for example, the diffraction angle of the C plane and can be obtained from the diffraction peak angle such as the {0002} plane. The surface angle can be obtained from the diffraction peak angle obtained by utilizing the total reflection phenomenon on the surface of the X-ray generated at the position where the incident angle = the reflection angle.
By measuring the difference between the diffraction peak angle on the crystal plane and the diffraction peak angle on the surface from all directions (4 directions at least every 90 °), the “angle between the surface and the crystal plane”, that is, the off-angle Can be determined. When the off angle is measured at each point in the plane, the off angle may vary in size and direction depending on the position. Among the above five measurement results, when the maximum off-angle value (absolute value) is | maximum off-angle |, and the smallest value (absolute value) is | minimum off-angle | The maximum off angle | − | minimum off angle | (degrees) represents the size of the range of variation, which is divided by 2 to express “variation” in units of “± degrees”. Also, (| maximum off angle | + | minimum off angle |) / 2 is the center value of the off angle.
表1に示すように、凸形状に100μm反ったサファイア基板上に成長したものが、最もオフ角のばらつきが小さい結果となった。また、表1におけるサファイア基板(下地基板)の反り量とオフ角のばらつきとの関係をグラフ化した図5を見ると、反り量−100μm〜+20μmの範囲において、下地基板の凸形状の反り量が小さくなるにつれて、オフ角ばらつきは大きくなり、凹形状の場合は反転して、反り量が大きくなるにつれて、オフ角ばらつきが大きくなる結果となった。 As shown in Table 1, those grown on a sapphire substrate warped to a convex shape by 100 μm resulted in the smallest variation in off-angle. Further, referring to FIG. 5 which is a graph showing the relationship between the amount of warpage of the sapphire substrate (underlying substrate) and the variation in off-angle in Table 1, the amount of warpage of the convex shape of the underlying substrate in the range of the amount of warping −100 μm to +20 μm. As the angle decreases, the off-angle variation increases, and in the case of the concave shape, the off-angle variation is reversed. As the amount of warpage increases, the off-angle variation increases.
[実施例3]
実施例2で作製して得られたGaN自立基板上に、次に示す発光素子構造の成長層を形成した。図7は、この実施例3に係わる窒化物半導体発光素子を示す構造断面図である。
実施例3の半導体活性層は、量子井戸構造を有している。発光ダイオード用の多層膜は、有機金属気相成長(MOCVD)法により作製した。有機金属原料として、トリメチルガリウム(TMG)、トリメチルアルミニウム(TMA)、トリメチルインジウム(TMI)、ビスシクロペンタジエニルマグネシウム(Cp2Mg)を用いた。ガス原料として、アンモニア(NH3)、シラン(SiH4)を用いた。また、キャリアガスとして、水素及び窒素を用いた。
[Example 3]
A growth layer having the following light-emitting element structure was formed on the GaN free-standing substrate produced in Example 2. FIG. 7 is a structural sectional view showing the nitride semiconductor light emitting device according to the third embodiment.
The semiconductor active layer of Example 3 has a quantum well structure. A multilayer film for a light emitting diode was produced by metal organic chemical vapor deposition (MOCVD). Trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), and biscyclopentadienylmagnesium (Cp 2 Mg) were used as organometallic raw materials. Ammonia (NH 3 ) and silane (SiH 4 ) were used as gas raw materials. Moreover, hydrogen and nitrogen were used as carrier gas.
本実施例の半導体発光素子は、次のようにして製造した。
まず、上記の実施例2により得られたGaN自立基板(オフ角のばらつきを異にする)11を用いて、GaN自立基板11上に、1050℃にて、Siをキャリア濃度1×1019cm−3ドープしたn型GaN層12を4μmの膜厚で成長させた。次に800℃で、活性層として、厚さ10nmのGaN障壁層13(4層)と、厚さ3nmのIn0.1
Ga0.9N井戸層14(3層)とが交互に積層された多重量子井戸構造(MQW)を有
するInGaN系活性層15を成長させた。その上部に、p型Al0.1Ga0.9Nクラッド層16と、p型GaNコンタクト層17をこの順で形成した。更に、p型GaNコンタクト層17上に正電極19、GaN自立基板11裏面に負電極18を形成した後、チップ化して作製した。
The semiconductor light emitting device of this example was manufactured as follows.
First, using the GaN free-standing substrate 11 obtained by the above-described Example 2 (with different variations in off-angle), Si is deposited on the GaN free-standing substrate 11 at 1050 ° C. with a carrier concentration of 1 × 10 19 cm. -3 doped n-type GaN layer 12 was grown to a thickness of 4 μm. Next, at 800 ° C., as an active layer, a GaN barrier layer 13 (four layers) having a thickness of 10 nm, and In 0.1 having a thickness of 3 nm.
An InGaN-based active layer 15 having a multiple quantum well structure (MQW) in which Ga 0.9 N well layers 14 (three layers) were alternately stacked was grown. A p-type Al 0.1 Ga 0.9 N clad layer 16 and a p-type GaN contact layer 17 were formed in this order on the top. Further, a positive electrode 19 was formed on the p-type GaN contact layer 17 and a negative electrode 18 was formed on the back surface of the GaN free-standing substrate 11, and then fabricated as a chip.
本実施例で作製した全サンプルについて、その後、上記オフ角の測定箇所と同じ箇所に位置する5個のチップ(発光素子)を選んで、EL(Electro Luminescence)測定により、各チップの発光波長を測定し、基板面内の発光波長のばらつきを求めた。5つの発光波長の測定値のうち、「発光波長の最大値−発光波長の最小値」を発光波長のばらつきと定義した。
発光波長ばらつきを測定した結果を表1に示すが、オフ角のばらつきの小さいサンプルで、発光波長のばらつきが小さくなる結果が得られた。
発光波長のばらつきは、もちろん小さい方が良いが、実用上、20nm以下に収めるのが良い。そのためには、GaN自立基板のオフ角のばらつきと発光波長のばらつきとの関係を示すグラフ(図6)より、窒化物半導体自立基板のオフ角のばらつきを、±0.25
度以下とするのが好ましい。さらに、オフ角のばらつきを±0.25度以下とするために
は、図5より下地基板の反り量を、−20μm以下とするのが良いことが分かった。
For all the samples produced in this example, five chips (light-emitting elements) located at the same location as the off-angle measurement location were selected, and the emission wavelength of each chip was determined by EL (Electro Luminescence) measurement. Measurements were made to determine the variation in emission wavelength within the substrate surface. Of the measured values of the five emission wavelengths, “the maximum value of the emission wavelength−the minimum value of the emission wavelength” was defined as the variation in the emission wavelength.
The results of measuring the emission wavelength variation are shown in Table 1. A sample with a small variation in off-angle gave a result that the variation in emission wavelength was small.
Of course, the variation in the emission wavelength is preferably small, but in practice, it should be within 20 nm or less. For this purpose, from the graph (FIG. 6) showing the relationship between the variation in the off-angle of the GaN free-standing substrate and the variation in the emission wavelength, the variation in the off-angle of the nitride semiconductor free-standing substrate is ± 0.25.
It is preferable to make it below the degree. Furthermore, it was found from FIG. 5 that the warpage amount of the base substrate should be −20 μm or less in order to make the variation in the off angle ±± 0.25 degrees or less.
1 下地基板
1a 下地基板の表面
1b 下地基板の裏面
2 窒化物半導体層
2a 分離された窒化物半導体層の表面
2b 分離された窒化物半導体層の裏面
3 自立した窒化物半導体基板
11 GaN自立基板
15 InGaN系活性層
DESCRIPTION OF SYMBOLS 1 Ground substrate 1a Surface 1b of ground substrate 2 Back surface of ground substrate 2 Nitride semiconductor layer 2a Surface 2b of separated nitride semiconductor layer 3 Back surface of separated nitride semiconductor layer 3 Free standing nitride semiconductor substrate 11 GaN free standing substrate 15 InGaN-based active layer
Claims (3)
前記下地基板の反り量を、前記下地基板の中心位置と前記下地基板の中心から距離Rの位置とにおける結晶成長面である表面の高さの差(ただし、前記表面の高さの差の正負を、前記下地基板の表面が凸形状の場合をマイナス、凹形状の場合をプラスとする)と定義したとき、前記下地基板は、R=25mmに換算した場合の前記反り量が−100μm以上−20μm以下の範囲にあることを特徴とする窒化物半導体基板の製造方法。 In a method for manufacturing a nitride semiconductor substrate, a nitride semiconductor layer is formed on a base substrate, and a self-standing nitride semiconductor substrate is manufactured using the nitride semiconductor layer separated from the base substrate.
The amount of warpage of the base substrate is defined as the difference in the height of the surface that is the crystal growth surface between the center position of the base substrate and the position of the distance R from the center of the base substrate (however, the sign of the difference in the height of the surface is positive or negative) Is defined as negative when the surface of the base substrate is convex, and positive when the surface of the base substrate is concave), the warpage amount of the base substrate when converted to R = 25 mm is −100 μm or more− A method for manufacturing a nitride semiconductor substrate, which is in a range of 20 μm or less.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005166945A (en) * | 2003-12-02 | 2005-06-23 | Nichia Chem Ind Ltd | Semiconductor laser element and manufacturing method thereof |
JP2008124151A (en) * | 2006-11-09 | 2008-05-29 | Namiki Precision Jewel Co Ltd | Single crystal substrate and method of manufacturing nitride semiconductor single crystal |
JP2009143796A (en) * | 2007-12-12 | 2009-07-02 | Siltron Inc | Method for manufacturing gallium nitride single crystalline substrate using self-split |
-
2008
- 2008-01-16 JP JP2008007171A patent/JP5051455B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005166945A (en) * | 2003-12-02 | 2005-06-23 | Nichia Chem Ind Ltd | Semiconductor laser element and manufacturing method thereof |
JP2008124151A (en) * | 2006-11-09 | 2008-05-29 | Namiki Precision Jewel Co Ltd | Single crystal substrate and method of manufacturing nitride semiconductor single crystal |
JP2009143796A (en) * | 2007-12-12 | 2009-07-02 | Siltron Inc | Method for manufacturing gallium nitride single crystalline substrate using self-split |
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