JP5488562B2 - Manufacturing method of nitride semiconductor substrate - Google Patents

Manufacturing method of nitride semiconductor substrate Download PDF

Info

Publication number
JP5488562B2
JP5488562B2 JP2011231199A JP2011231199A JP5488562B2 JP 5488562 B2 JP5488562 B2 JP 5488562B2 JP 2011231199 A JP2011231199 A JP 2011231199A JP 2011231199 A JP2011231199 A JP 2011231199A JP 5488562 B2 JP5488562 B2 JP 5488562B2
Authority
JP
Japan
Prior art keywords
substrate
nitride semiconductor
semiconductor layer
gan
angle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2011231199A
Other languages
Japanese (ja)
Other versions
JP2012020934A (en
Inventor
健 目黒
貴征 鈴木
健 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Metals Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP2011231199A priority Critical patent/JP5488562B2/en
Publication of JP2012020934A publication Critical patent/JP2012020934A/en
Application granted granted Critical
Publication of JP5488562B2 publication Critical patent/JP5488562B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Led Devices (AREA)

Description

本発明は、窒化物半導体基板の製造方法に関し、更に詳しくは、窒化物半導体、例えば(InXAlYGa1-X-YN、0≦X、0≦Y、0≦X+Y≦1)からなる、オフ角ばらつきの小さい自立基板を製造できる窒化物半導体基板の製造方法に関する。 The present invention relates to a method for manufacturing a nitride semiconductor substrate, and more particularly, a nitride semiconductor, for example, (In X Al Y Ga 1-XY N, 0 ≦ X, 0 ≦ Y, 0 ≦ X + Y ≦ 1). The present invention relates to a method for manufacturing a nitride semiconductor substrate capable of manufacturing a self-standing substrate with small off-angle variation.

窒化ガリウム(GaN)、窒化インジウムガリウム(InGaN)、窒化ガリウムアルミニウム(GaAlN)等の窒化物系半導体材料は、禁制帯幅が大きく、バンド間遷移も直接遷移型であるため、可視光及び紫外光用途の短波長発光素子への展開が進んでいる。   Nitride-based semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and gallium aluminum nitride (GaAlN) have a large forbidden band and direct transition between bands, so visible light and ultraviolet light Development of applications for short-wavelength light emitting devices is progressing.

窒化物半導体基板は、窒素の蒸気圧が非常に高いために融液からのバルク状結晶成長が極めて困難である。この理由により、窒化物半導体基板の主に用いられている製造方法としては、図4に示すように、サファイア基板やシリコン基板あるいはガリウム砒素基板などの窒化物半導体とは異なる異種基板21上に、主に気相成長法を用いて窒化物半導体層22をヘテロエピタキシャル成長させた後(図4(a))、剥離や研磨あるいはエッチング等の手法を用いて異種基板21を除去し(図4(b))、異種基板21上に形成した前記窒化物半導体層22の表裏面を研磨等することで、いわゆる「自立基板」を得ている(図4(c))。なお、図4における矢印は、結晶の主たる面方位、例えば、サファイア、GaNなどではC軸を示している。
このようにして、自立基板を作製する具体的な方法としては、例えば特許文献1に記載の方法などが知られている。
The nitride semiconductor substrate has a very high vapor pressure of nitrogen, so that bulk crystal growth from the melt is extremely difficult. For this reason, as a manufacturing method mainly used for a nitride semiconductor substrate, as shown in FIG. 4, on a different substrate 21 different from a nitride semiconductor such as a sapphire substrate, a silicon substrate, or a gallium arsenide substrate, After the nitride semiconductor layer 22 is heteroepitaxially grown mainly using a vapor phase growth method (FIG. 4A), the heterogeneous substrate 21 is removed using a technique such as peeling, polishing or etching (FIG. 4B). )), The so-called “self-supporting substrate” is obtained by polishing or the like on the front and back surfaces of the nitride semiconductor layer 22 formed on the heterogeneous substrate 21 (FIG. 4C). In addition, the arrow in FIG. 4 has shown the C-axis in the main surface orientation of a crystal | crystallization, for example, sapphire, GaN, etc.
Thus, as a specific method for producing a self-standing substrate, for example, a method described in Patent Document 1 is known.

窒化物半導体層の成長方法については、上述したように窒化物半導体とは異なる異種基板上に窒化物半導体層をヘテロエピタキシャル成長させるため、大きな格子定数差により、成長初期に大きく結晶が歪み、109〜1010cm-2もの転位密度が入ってしまう。これらの欠陥は、LD(Laser diode)やLED(Light emitted diode)などの発光デバイスの信頼性を著しく低下させてしまうため、転位密度を低減させる必要がある。 For the method of growing the nitride semiconductor layer, in order to hetero-epitaxially growing a nitride semiconductor layer on a different heterogeneous substrate which is a nitride semiconductor as described above, due to the large lattice constant difference, large distortion crystals initial growth, 109 Dislocation density of -10 10 cm -2 is included. These defects significantly reduce the reliability of light emitting devices such as LDs (Laser diodes) and LEDs (Light emitted diodes), so it is necessary to reduce the dislocation density.

近年、このような欠陥の密度を低減する方法として、ELO(epitaxial lateral overgrowth)や、FIELO(facet initiated epitaxial lateral overgrowth)、ペンデオエピタキシーといった成長技術が報告された。これらの成長技術は、サファイア等の基板上に成長させたGaN上に、SiO2等でパターニングされたマスクを形成し、マスクの窓部からさらにGaN結晶を選択的に成長させて、マスク上をGaNがラテラル成長で覆うようにすることで、下地結晶からの転位の伝播を防ぐものである。これらの成長技術の開発により、GaN中の転位密度は107cm-2台程度にまで、飛躍的に低減させることができるようになった。 In recent years, growth techniques such as ELO (epitaxial lateral overgrowth), FIELO (facet initiated epitaxial lateral overgrowth), and pendeo epitaxy have been reported as methods for reducing the density of such defects. In these growth techniques, a mask patterned with SiO 2 or the like is formed on GaN grown on a substrate such as sapphire, and further a GaN crystal is selectively grown from the window portion of the mask. By covering GaN with lateral growth, the propagation of dislocations from the underlying crystal is prevented. With the development of these growth techniques, the dislocation density in GaN can be drastically reduced to about 10 7 cm −2 .

更に、サファイア基板等の異種基板上に転位密度を低減したGaN層を厚くエピタキシャル成長させ、成長後に下地から剥離して、GaN層を自立したGaN基板として用いる方法が種々提案されている。例えば、前述のELO技術を用いてサファイア基板上にGaN層を形成した後、サファイア基板をエッチング等により除去し、GaN自立基板を得ることが提案されている。
また、VAS(Void-assisted Separation:例えば、非特許文献1)法や、DEEP(Dislocation Elimination by the Epi-growth with inverted-Pyramidal pits:例えば、非特許文献2)法などが公開されている。VASは、サファイア等の基板上で、網目構造のTiN薄膜を介してGaNを成長することで、下地基板とGaN層の界面にボイドを形成し、GaN基板の剥離と低転位化を同時に可能にしたものである。また、DEEPは、エッチング等で除去が可能なGaAs基板上にパターニングしたSiN等のマスクを用いてGaNを成長させ、結晶表面に故意にファセット面で囲まれたピットを複数形成し、前記ピットの底部に転位を集積させることで、その他の領域を低転位化するものである。
Furthermore, various methods have been proposed in which a GaN layer having a reduced dislocation density is epitaxially grown thickly on a dissimilar substrate such as a sapphire substrate, peeled off from the underlying layer after growth, and used as a self-supporting GaN substrate. For example, it has been proposed to form a GaN layer on a sapphire substrate using the above-described ELO technique, and then remove the sapphire substrate by etching or the like to obtain a GaN free-standing substrate.
VAS (Void-assisted Separation: for example, Non-Patent Document 1) method, DEEP (Dislocation Elimination by the Epi-growth with inverted-Pyramidal pits: For example, Non-Patent Document 2) method, and the like are disclosed. VAS grows GaN on a substrate such as sapphire via a TiN thin film with a network structure, thereby forming a void at the interface between the base substrate and the GaN layer, and simultaneously enabling peeling and low dislocation of the GaN substrate. It is a thing. Further, DEEP grows GaN using a mask such as SiN patterned on a GaAs substrate that can be removed by etching or the like to form a plurality of pits deliberately surrounded by facet surfaces on the crystal surface. By accumulating dislocations at the bottom, other regions are reduced in dislocation.

特開2002−57119号公報JP 2002-57119 A Y.Oshima et.al., Jpn.J.Appl.Phys., Vol.42(2003), pp.L1-L3Y. Oshima et.al., Jpn.J.Appl.Phys., Vol.42 (2003), pp.L1-L3 K.Motoki et.al., Jpn.J.Appl.Phys., Vol.40(2001), pp.L140-L143K. Motoki et.al., Jpn.J.Appl.Phys., Vol.40 (2001), pp.L140-L143

しかしながら、上述した従来方法で作製した窒化物半導体層22には、表裏面に欠陥密度差が存在することから、結晶格子が歪み内部応力が生じて、下地基板21から剥離した後の窒化物半導体層22は、どのようにしても裏面22bが裏面側に凸形状(中心部が出っ張る形状)になるように反ってしまう(図4(b))。このように反った窒化物半導体層22は、研磨などで平坦な加工を施したとしても、表面22aの面内の各位置で面方位が一様な方向に向いていないため、窒化物半導体自立基板23のオフ角が面内でばらついてしまうという問題が発生する(図4(c))。ここでいう「オフ角」とは、「表面の各位置の法線の、主たる面方位からのずれの角度」(あるいは「表面と、主たる結晶面とのなす角度」)のことであり、「オフ角がばらつく」というのは、「表面の各位置の法線の、主たる面方位からずれの角度が一様にならず、面内の位置によって、ずれの角度が異なってしまう」ことである。
面内のオフ角がばらつくと、その上に形成した発光素子デバイスの発光波長のばらつきに大きな影響を与え、著しく歩留まりを低下させてしまう。
さらに面内でオフ角がばらついている窒化物半導体自立基板23(図4(c))を種結晶として、その上にエピタキシャル成長しても、配向性は引き継がれるので、エピタキシャル層を厚く成長してスライスして得られる自立基板も、結局オフ角がばらついてしまうことになる。また、面方位が一様に揃っている窒化物半導体基板上に成長しても、貫通転位の減少などによる表裏面の欠陥密度差により、再び反ってしまうため、オフ角ばらつきの原因となる。
However, since the nitride semiconductor layer 22 manufactured by the above-described conventional method has a defect density difference between the front and back surfaces, the nitride semiconductor after the crystal lattice is distorted and the internal stress is generated and peels from the base substrate 21. In any way, the layer 22 warps so that the back surface 22b has a convex shape (a shape in which the central portion protrudes) on the back surface side (FIG. 4B). Even if the nitride semiconductor layer 22 warped as described above is flattened by polishing or the like, the nitride semiconductor layer 22 is not oriented in a uniform direction at each position within the surface 22a. There arises a problem that the off-angle of the substrate 23 varies in the plane (FIG. 4C). The “off angle” here means “the angle of deviation of the normal of each position on the surface from the main plane orientation” (or “the angle between the surface and the main crystal plane”), “The off-angle varies” means that the angle of deviation of the normal of each position on the surface from the main surface orientation is not uniform, and the angle of deviation varies depending on the position in the surface. .
If the in-plane off-angle varies, it greatly affects the variation in the emission wavelength of the light-emitting element device formed thereon, and the yield is significantly reduced.
Further, even if epitaxial growth is performed on the nitride semiconductor free-standing substrate 23 (FIG. 4C) having an off-angle variation in the plane as a seed crystal, the orientation is inherited, so that the epitaxial layer is grown thickly. The free-standing substrate obtained by slicing will also vary in off-angle. Further, even when grown on a nitride semiconductor substrate having a uniform plane orientation, it is warped again due to a defect density difference between the front and back surfaces due to a decrease in threading dislocations, etc., which causes off-angle variation.

本発明は、上記課題を解決し、オフ角ばらつきの小さい、窒化物半導体基板を製造することができる窒化物半導体基板の製造方法を提供することにある。   An object of the present invention is to solve the above-described problems and to provide a method for manufacturing a nitride semiconductor substrate capable of manufacturing a nitride semiconductor substrate with small off-angle variation.

上記課題を解決するために、本発明は次のように構成されている。
本発明の第1の態様は、サファイア基板上に窒化物半導体層を形成し、前記サファイア基板から分離した前記窒化物半導体層を用いて自立した窒化物半導体基板を作製する窒化物半導体基板の製造方法において、分離された前記窒化物半導体層の表裏面の欠陥密度差に起因する反りによる前記窒化物半導体層のC軸の半径方向内方への傾きを相殺するように、予め前記サファイア基板表面の全面におけるC軸には半径方向外方に傾きを持たせたことを特徴とする窒化物半導体基板の製造方法である。
In order to solve the above problems, the present invention is configured as follows.
According to a first aspect of the present invention, a nitride semiconductor substrate is formed by forming a nitride semiconductor layer on a sapphire substrate and producing a self-supporting nitride semiconductor substrate using the nitride semiconductor layer separated from the sapphire substrate. In the method, the surface of the sapphire substrate is previously set so as to cancel out the inward inclination of the C-axis of the nitride semiconductor layer due to the warp due to the defect density difference between the front and back surfaces of the separated nitride semiconductor layer. The nitride semiconductor substrate manufacturing method is characterized in that the C axis on the entire surface of the substrate is inclined radially outward.

本発明によれば、オフ角ばらつきの小さい窒化物半導体自立基板が得られる。また、得られた窒化物半導体自立基板上にLEDやLDなどの半導体発光素子を作製した場合の歩留りを著しく向上させることができる。   According to the present invention, a nitride semiconductor free-standing substrate with small off-angle variation can be obtained. Moreover, the yield in the case where semiconductor light emitting devices such as LEDs and LDs are fabricated on the obtained nitride semiconductor free-standing substrate can be significantly improved.

以下、本発明に係る窒化物半導体基板の製造方法の実施形態を図面を用いて説明する。   Hereinafter, embodiments of a method for manufacturing a nitride semiconductor substrate according to the present invention will be described with reference to the drawings.

図1は、本実施形態に係る窒化物半導体基板の製造方法の工程を概略的に示す工程図である。
本実施形態の窒化物半導体基板の製造方法は、まず、下地基板としてC面サファイア基板1を準備し、C面サファイア基板上1に窒化物半導体層2を形成する(図1(a))。
窒化物半導体層2は、例えば、InXAlYGa1-X-YN(0≦X、0≦Y、0≦X+Y≦1)層などである。窒化物半導体層2の形成方法には、有機金属気相成長法(MOVPE法)やハイドライド気相成長法(HVPE法)、或いはこれらを組み合わせた気相成長法などが用いられる。
FIG. 1 is a process diagram schematically showing the steps of the method for manufacturing a nitride semiconductor substrate according to the present embodiment.
In the method for manufacturing a nitride semiconductor substrate according to the present embodiment, first, a C-plane sapphire substrate 1 is prepared as a base substrate, and a nitride semiconductor layer 2 is formed on the C-plane sapphire substrate 1 (FIG. 1A).
The nitride semiconductor layer 2 is, for example, an In X Al Y Ga 1-XY N (0 ≦ X, 0 ≦ Y, 0 ≦ X + Y ≦ 1) layer or the like. As a method for forming the nitride semiconductor layer 2, a metal organic vapor phase epitaxy method (MOVPE method), a hydride vapor phase epitaxy method (HVPE method), or a vapor phase epitaxy method combining these is used.

次に、サファイア基板1上に形成した窒化物半導体層2を、サファイア基板1から分離する(図1(b))。分離方法(除去方法)は、剥離(図示例)のほか、研磨、エッチングなどの方法を用いてもよい。   Next, the nitride semiconductor layer 2 formed on the sapphire substrate 1 is separated from the sapphire substrate 1 (FIG. 1B). As the separation method (removal method), methods such as polishing and etching may be used in addition to peeling (illustrated example).

最後に、分離された窒化物半導体層2の表面2a及び裏面2bを研磨し(図1(b)の破線部分を残し)、洗浄処理などすることで、自立した窒化物半導体基板3を作製する(図1(c))。なお、図1における矢印は、C軸(結晶の主たる面方位)である。
自立した窒化物半導体基板3は、分離された窒化物半導体層2から1枚のみ取得しても、窒化物半導体層3を厚くエピタキシャル成長させてスライスすることにより複数枚の窒化物半導体自立基板を取得してもよい。なお、窒化物半導体の「自立基板」は、搬送などの基板処理が可能な強度を有する基板であって、基板の厚さは、例えば200μm以上が好ましい。
Finally, the front surface 2a and the back surface 2b of the separated nitride semiconductor layer 2 are polished (leaving the broken line portion in FIG. 1B), and a self-supporting nitride semiconductor substrate 3 is manufactured by performing a cleaning process or the like. (FIG. 1 (c)). In addition, the arrow in FIG. 1 is the C axis (main plane orientation of the crystal).
Even if only one isolated nitride semiconductor layer 2 is obtained from the separated nitride semiconductor layer 2, a plurality of nitride semiconductor free-standing substrates can be obtained by epitaxially growing the nitride semiconductor layer 3 thickly and slicing. May be. Note that the “self-standing substrate” of nitride semiconductor is a substrate having a strength that allows substrate processing such as transportation, and the thickness of the substrate is preferably 200 μm or more, for example.

上記実施形態の製造方法で特徴とするところは、窒化物半導体層2を形成するための下地となるサファイア基板1の表面におけるC軸の傾きの方向と大きさを所定範囲に規定したことにある。   The manufacturing method of the above embodiment is characterized in that the direction and magnitude of the C-axis inclination on the surface of the sapphire substrate 1 that is the base for forming the nitride semiconductor layer 2 are defined within a predetermined range. .

従来用いられているサファイア基板の表面(C面)は、図4(a)に示すように、オフ角が小さくC軸が表面にほぼ垂直に揃っており、このサファイア基板上にエピタキシャル成長される窒化物半導体層も配向性が引き継がれてC軸が一様に揃って形成される。しかし、サファイア基板上に形成される窒化物半導体層は、その表面の欠陥密度が小さく、裏面の欠陥密度が大きいため、必ず窒化物半導体層の表面が凹形状に反るように内部応力が働く。このため、分離された窒化物半導体層は、図4(b)に示すように、欠陥密度差に起因した内部応力により歪んで表面が凹形状に反ってしまい、研磨などで平坦な加工を施した窒化物半導体自立基板は、図4(c)に示すように、C軸が半径方向内方に傾き、オフ角が面内でばらついてしまう。   As shown in FIG. 4A, the surface (C-plane) of a sapphire substrate used conventionally has a small off angle and the C-axis is almost perpendicular to the surface, and is nitrided epitaxially on the sapphire substrate. The physical semiconductor layer is also formed so that the orientation is inherited and the C-axis is uniformly aligned. However, since the nitride semiconductor layer formed on the sapphire substrate has a small defect density on the front surface and a large defect density on the back surface, internal stress always acts so that the surface of the nitride semiconductor layer warps in a concave shape. . For this reason, as shown in FIG. 4B, the separated nitride semiconductor layer is distorted by the internal stress caused by the difference in defect density and the surface warps into a concave shape, and is subjected to flat processing by polishing or the like. In the nitride semiconductor free-standing substrate, as shown in FIG. 4C, the C-axis is inclined inward in the radial direction, and the off-angle varies in the plane.

そこで、本実施形態では、分離された窒化物半導体層2の表裏面の欠陥密度差に起因する反りによる窒化物半導体層2のC軸の半径方向内方への傾きを見込んで、このC軸の半径方向内方への傾きを相殺して分離後の窒化物半導体層2中のC軸がほぼ一様に揃うように、予めサファイア基板1表面のC軸を半径方向外方に傾きを持たせるようにしている。
すなわち、図1に示すように、サファイア基板1のC軸の傾きが、分離後の窒化物半導体層2の欠陥密度差に起因した反りによるC軸の傾きをキャンセルする向きに同程度に傾いていれば、分離後の窒化物半導体層2に反りが生じても、C軸はほぼ一様に揃い、凹形状の窒化物半導体層2表面を研磨することにより、窒化物半導体自立基板3の面内のオフ角のばらつきは小さくなる。このように、サファイア基板1のC軸のオフ角の方向と大きさを規定することによって、分離後の窒化物半導体層2のC軸の傾きのばらつきを制御し、結果としてオフ角ばらつきの小さい、C軸の一様に揃った窒化物半導体自立基板3が得られる。
窒化物半導体層2の成長条件にもよるが、窒化物半導体層2が欠陥密度差によって生じるC軸の傾き(半径方向内方)のばらつきは、0.3°〜0.7°程度あり、これに対してサファイア基板1のオフ角ばらつきを反対方向(基板の半径方向外方)に0.3°〜1°傾けてやることにより、窒化物半導体基板3のオフ角ばらつきを実用上問題のない、0.3°以下に制御することが可能になる。
Therefore, in the present embodiment, in consideration of the inclination of the C-axis of the nitride semiconductor layer 2 in the radial direction due to warping caused by the defect density difference between the front and back surfaces of the separated nitride semiconductor layer 2, this C-axis The C-axis of the surface of the sapphire substrate 1 has an inclination outward in the radial direction in advance so that the C-axis in the nitride semiconductor layer 2 after separation is substantially uniformly aligned by offsetting the inclination inward in the radial direction. I try to make it.
That is, as shown in FIG. 1, the inclination of the C-axis of the sapphire substrate 1 is inclined to the same extent in such a direction as to cancel the inclination of the C-axis due to the warp caused by the defect density difference of the nitride semiconductor layer 2 after separation. Then, even if warpage occurs in the nitride semiconductor layer 2 after separation, the C-axis is substantially uniform, and the surface of the nitride semiconductor free-standing substrate 3 is polished by polishing the surface of the concave nitride semiconductor layer 2. The variation in the off angle is reduced. Thus, by defining the direction and magnitude of the off-angle of the C-axis of the sapphire substrate 1, variation in the inclination of the C-axis of the nitride semiconductor layer 2 after separation is controlled, and as a result, variation in off-angle is small. Thus, a nitride semiconductor free-standing substrate 3 having a uniform C axis is obtained.
Although depending on the growth conditions of the nitride semiconductor layer 2, the variation of the C-axis inclination (inward in the radial direction) caused by the difference in defect density in the nitride semiconductor layer 2 is about 0.3 ° to 0.7 °. On the other hand, when the off-angle variation of the sapphire substrate 1 is tilted by 0.3 ° to 1 ° in the opposite direction (outward in the radial direction of the substrate), the off-angle variation of the nitride semiconductor substrate 3 is a practical problem. It is possible to control to below 0.3 °.

分離後の窒化物半導体層2の欠陥密度差に起因した反りによる半径方向内方のC軸の傾きは、窒化物半導体層2の中心部では小さく、外周部に行くほど大きくなる。
従って、分離後の窒化物半導体層2のC軸が一様に揃うようにするためには、サファイア基板1表面の半径の半分よりも内側では、サファイア基板1のC軸の半径方向外方への傾きが、0.3°より小さいことが好ましい。また、サファイア基板1表面の半径の半分を含む外側では、サファイア基板1のC軸の傾きが半径方向外方に傾いているのが好ましく、更には、サファイア基板1表面の半径の半分を含む外側では、サファイア基板1のC軸の半径方向外方への傾きが外側に行くほど大きくなるのが好ましい。
The inclination of the C-axis radially inward due to warping caused by the difference in defect density of the nitride semiconductor layer 2 after separation is small at the center of the nitride semiconductor layer 2 and increases toward the outer periphery.
Therefore, in order to uniformly align the C-axis of the nitride semiconductor layer 2 after separation, the C-axis of the sapphire substrate 1 is radially outward from the half of the radius of the sapphire substrate 1 surface. Is preferably smaller than 0.3 °. Moreover, it is preferable that the inclination of the C axis of the sapphire substrate 1 is inclined outward in the radial direction on the outside including the half of the radius of the surface of the sapphire substrate 1, and further, the outside including the half of the radius of the surface of the sapphire substrate 1. Then, it is preferable that the inclination of the C-axis of the sapphire substrate 1 in the radial direction outward increases.

次に、本発明の実施例を説明する。
[実施例1]
ボイド形成剥離法(Void-assisted Separation Method:VAS法)を用いてサファイア基板上にGaNエピタキシャル層を成長させ、その後、サファイア基板を除去することにより、自立したGaN基板を得て、その評価を行った。
VAS法は、サファイア基板とGaN成長層との間に網目構造を有する窒化チタンの薄膜を挟み込んで結晶成長を行う方法であるが、その詳細は、例えば上記の非特許文献1に記載されている。
Next, examples of the present invention will be described.
[Example 1]
A GaN epitaxial layer is grown on the sapphire substrate using the Void-Assisted Separation Method (VAS method), and then the sapphire substrate is removed to obtain a self-supporting GaN substrate for evaluation. It was.
The VAS method is a method of performing crystal growth by sandwiching a titanium nitride thin film having a network structure between a sapphire substrate and a GaN growth layer, and details thereof are described in Non-Patent Document 1, for example. .

以下に、本実施例のGaN自立基板の製造方法について説明する。
まず、直径2インチのサファイアC面基板上に、MOVPE法により、トリメチルガリウム(TMG)とNH3を原料として、アンドープGaN層を300nmの厚さに成長させた。次に、このGaNエピタキシャル基板上に、Ti薄膜を20nmの厚さに蒸着し、これを電気炉に入れて、20%のNH3と80%のH2の混合ガスの雰囲気中にて、1050度で20分間熱処理を施した。その結果、アンドープGaN層の一部がエッチングされて高密度の空隙(ボイド)が発生してボイド形成GaN層に変化するとともに、Ti薄膜が窒化されて表面にサブミクロンの微細な穴が高密度に形成された穴形成TiN層に変化した。
この基板をHVPE炉に入れ、GaNを全体で800μmの厚さに堆積させた。Gaメタルのボートは900℃に加熱し、基板側は1100℃とし、キャリアガスとして水素5%と窒素95%の混合ガスを用いた。原料ガスとしてHClガスとGaを反応させてGaClを生成させ、同時にアンモニアガスを供給し、成長の開始時にはV/III比が10になるように流量を調整した。
この条件で、GaNの核がTiN層上に3次元の島状に成長し、次いで結晶同士が横方向に成長して互いに結合し、表面の平坦化が進行していった。この様子は、成長時間を変えて炉外に取り出した基板表面及び断面を顕微鏡観察することにより確認した。さらに成長時間を延ばして成長を続けた。GaN結晶成長の終了後、HVPE装置を冷却する過程で、GaN層はボイド層を境にサファイアの下地基板から自然に剥離し、800μm厚さのGaN自立基板が得られた。
Below, the manufacturing method of the GaN free-standing substrate of a present Example is demonstrated.
First, an undoped GaN layer was grown to a thickness of 300 nm on a sapphire C-plane substrate having a diameter of 2 inches by MOVPE using trimethyl gallium (TMG) and NH 3 as raw materials. Next, a Ti thin film having a thickness of 20 nm is deposited on the GaN epitaxial substrate, and this is put in an electric furnace, and in an atmosphere of a mixed gas of 20% NH 3 and 80% H 2 1050 Heat treatment was performed for 20 minutes. As a result, a part of the undoped GaN layer is etched to generate high-density voids and change to void-formed GaN layers, and the Ti thin film is nitrided to form high-density submicron holes on the surface. It changed into the hole formation TiN layer formed in this.
This substrate was placed in an HVPE furnace, and GaN was deposited to a total thickness of 800 μm. The Ga metal boat was heated to 900 ° C., the substrate side was set to 1100 ° C., and a mixed gas of 5% hydrogen and 95% nitrogen was used as a carrier gas. HCl gas and Ga were reacted as source gases to generate GaCl, and ammonia gas was supplied at the same time, and the flow rate was adjusted so that the V / III ratio was 10 at the start of growth.
Under these conditions, the GaN nuclei grew in a three-dimensional island shape on the TiN layer, and then the crystals grew laterally and joined to each other, and the surface was flattened. This state was confirmed by observing the substrate surface and cross-section taken out of the furnace with different growth times under a microscope. We continued to grow by extending the growth time. In the process of cooling the HVPE apparatus after completion of the GaN crystal growth, the GaN layer naturally separated from the sapphire base substrate with the void layer as a boundary, and a GaN free-standing substrate having a thickness of 800 μm was obtained.

このGaN自立基板の作製を、従来用いられている通常のサファイア基板(オフ角のばらつきは0.1°以下)と、実施例のサファイア基板とについて行った。
実施例のサファイア基板は、サファイア基板表面の各点におけるC軸の半径方向外方への傾きの最大値と最小値との差であるC軸の傾きのばらつき(半径方向外方へのオフ角のばらつき)が、0.3°以上1°以下であって、サファイア基板表面の半径の半分よりも内側では、サファイア基板のC軸の半径方向外方への傾きが、0.3°より小さく、サファイア基板表面の半径の半分を含む外側では、サファイア基板のC軸の傾きが半径方向外方に傾き、且つC軸の半径方向外方への傾きが外側に行くほど大きくなっているサファイア基板を用いた。
用いるサファイア基板のオフ角のばらつきが異なる以外は、全て上記した同一の製造条件でGaN自立基板を作製し、得られたGaN自立基板のオフ角のばらつきを測定した。
その結果、通常のサファイア基板(オフ角のばらつき0.1°以下)を用いた場合には、GaN自立基板のオフ角のばらつきは0.45°であり、本実施例のサファイア基板を用いた場合には、GaN自立基板のオフ角のばらつきは、0.23°以下であった。
ここで、オフ角のばらつきを、基板面内の複数点のオフ角のうち、「オフ角の最大値−オフ角の最小値」と定義し、基板面内のオフ角のばらつきを求めた。具体的には、オフ角の測定にはX線回折装置を用い、図2に示すように、2インチ(50.8mm)の基板の中心を通る直線上にある5mm間隔の10点の位置におけるオフ角を測定して、オフ角のばらつきを求めた。
成長条件によって、サファイア基板のC軸のオフ角のばらつきを適時、選択しなければならないが、サファイア基板のオフ角のばらつき(半径方向の外向き)が0.3°以上〜1°以下に入っていれば、大多数の成長条件に対して、成長した窒化物半導体基板のオフ角のばらつきを実用上問題のない、0.3°以内に抑え込めることが分かった。
The GaN free-standing substrate was produced for a conventional sapphire substrate (off-angle variation of 0.1 ° or less) and a sapphire substrate of the example.
In the sapphire substrate of the example, the variation of the C-axis inclination (the off-angle to the outer side in the radial direction) is the difference between the maximum value and the minimum value of the C-axis radial outward inclination at each point on the surface of the sapphire substrate. The dispersion of the sapphire substrate is less than 0.3 ° in the radial direction of the C-axis of the sapphire substrate. The sapphire substrate whose C-axis inclination of the sapphire substrate is inclined outward in the radial direction and the inclination of the C-axis outward in the radial direction is increased outward, including the half of the radius of the sapphire substrate surface. Was used.
A GaN free-standing substrate was manufactured under the same manufacturing conditions as described above except that the off-angle variation of the sapphire substrate used was different, and the off-angle variation of the obtained GaN free-standing substrate was measured.
As a result, when a normal sapphire substrate (off-angle variation of 0.1 ° or less) was used, the off-angle variation of the GaN free-standing substrate was 0.45 °, and the sapphire substrate of this example was used. In this case, the variation in the off-angle of the GaN free-standing substrate was 0.23 ° or less.
Here, the variation in off-angle is defined as “maximum off-angle−minimum off-angle” among a plurality of off-angles in the substrate surface, and the variation in off-angle in the substrate surface was obtained. Specifically, an X-ray diffractometer is used to measure the off-angle, and as shown in FIG. 2, at a position of 10 points at intervals of 5 mm on a straight line passing through the center of a 2-inch (50.8 mm) substrate. The off-angle was measured to determine the variation in off-angle.
Depending on the growth conditions, the variation in the off-axis angle of the sapphire substrate must be selected in a timely manner, but the variation in the off-angle of the sapphire substrate (radially outward) falls within the range of 0.3 ° to 1 °. As a result, it has been found that, for most growth conditions, the variation in the off-angle of the grown nitride semiconductor substrate can be suppressed to within 0.3 °, which has no practical problem.

[実施例2]
実施例1で作製したGaN基板上に、次に示す発光素子構造の成長層を形成した。図3は、本実施例2に係わる窒化物系半導体発光素子を示す構造断面図である。
本実施例2の半導体層には、量子井戸構造を有している。発光ダイオード用の多層膜は、有機金属気相成長(MOCVD)法により作製した。有機金属原料として、トリメチルガリウム(TMG)、トリメチルアルミニウム(TMA)、トリメチルインジウム(TMI)、ビスシクロペンタジエニルマグネシウム(Cp2Mg)を用いた。ガス原料として、アンモニア(NH3)、シラン(SiH4 )を用いた。また、キャリアガスとして、水素及び窒素を用いた。
[Example 2]
On the GaN substrate produced in Example 1, a growth layer having the following light emitting element structure was formed. FIG. 3 is a structural cross-sectional view showing the nitride-based semiconductor light-emitting device according to the second embodiment.
The semiconductor layer of Example 2 has a quantum well structure. A multilayer film for a light emitting diode was produced by metal organic chemical vapor deposition (MOCVD). Trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), and biscyclopentadienylmagnesium (Cp 2 Mg) were used as organometallic raw materials. Ammonia (NH 3 ) and silane (SiH 4 ) were used as gas raw materials. Moreover, hydrogen and nitrogen were used as carrier gas.

本実施例の半導体発光素子は、次のようにして製造した。
まず、上記の実施例1により得られたGaN自立基板(オフ角のばらつきを異にする)11を用いて、GaN自立基板11上に、1050℃にて、Siをキャリア濃度1×1019cm-3ドープしたn型GaN層12を4μmの膜厚で成長させた。
次に800℃で、活性層として、厚さ10nmのGaN障壁層13(4層)と、厚さ3nmのIn0.1Ga0.9N井戸層14(3層)とが交互に積層された多重量子井戸構造(MQW)を有するInGaN系活性層15を成長させた。その上部に、p型Al0.1Ga0.9Nクラッド層16と、p型GaNコンタクト層17とをこの順で形成した。
更に、p型GaNコンタクト層17上に正電極19、GaN自立基板11裏面に負電極18を形成した後、チップ化して作製した。
その後、図2に示す上記オフ角の測定箇所と同じ10点の箇所からチップを選んで、EL(Electro Luminescence)測定により、各チップの発光波長を測定し、基板面内の発光波長のばらつきを求めた。ここで、「発光波長の最大値−発光波長の最小値」を発光波長のばらつきと定義した。
The semiconductor light emitting device of this example was manufactured as follows.
First, using the GaN free-standing substrate 11 (with different variations in off-angle) 11 obtained in Example 1 above, Si is added at a carrier concentration of 1 × 10 19 cm at 1050 ° C. on the GaN free-standing substrate 11. A −3 doped n-type GaN layer 12 was grown to a thickness of 4 μm.
Next, a multi-quantum well in which GaN barrier layers 13 (4 layers) having a thickness of 10 nm and In 0.1 Ga 0.9 N well layers 14 (3 layers) having a thickness of 3 nm are alternately stacked as active layers at 800 ° C. An InGaN-based active layer 15 having a structure (MQW) was grown. A p-type Al 0.1 Ga 0.9 N clad layer 16 and a p-type GaN contact layer 17 were formed in this order on the top.
Further, a positive electrode 19 was formed on the p-type GaN contact layer 17 and a negative electrode 18 was formed on the back surface of the GaN free-standing substrate 11, and then fabricated as a chip.
After that, the chip is selected from the same 10 points as the off-angle measurement points shown in FIG. 2, and the emission wavelength of each chip is measured by EL (Electro Luminescence) measurement. Asked. Here, “the maximum value of the emission wavelength−the minimum value of the emission wavelength” was defined as the variation in the emission wavelength.

本実施例で作製した全サンプルについて、発光波長のばらつきを測定した結果を表1に示す。表1に示すように、オフ角のばらつきの小さいサンプルでは、発光波長のばらつきが小さくなる結果が得られた。

Figure 0005488562
Table 1 shows the results of measuring the variation in emission wavelength for all the samples prepared in this example. As shown in Table 1, a sample with a small variation in off-angle gave a result that the variation in emission wavelength was small.
Figure 0005488562

本発明の実施形態に係る窒化物半導体基板の製造方法の工程を概略的に示す工程図である。It is process drawing which shows schematically the process of the manufacturing method of the nitride semiconductor substrate which concerns on embodiment of this invention. 基板面内のオフ角のばらつきを説明するための基板の平面図である。It is a top view of the board | substrate for demonstrating the dispersion | variation in the off angle in a board | substrate surface. 実施例において作製されたGaN自立基板を用いて形成した窒化物半導体発光素子の断面構造を示す概略図である。It is the schematic which shows the cross-section of the nitride semiconductor light-emitting device formed using the GaN self-supporting substrate produced in the Example. 従来の異種基板上に窒化物半導体自立基板を作製する製造工程を模式的に示す工程図である。It is process drawing which shows typically the manufacturing process which produces the nitride semiconductor self-supporting board | substrate on the conventional dissimilar board | substrate.

1 サファイア基板(C面サファイア基板)
2 窒化物半導体層
3 窒化物半導体基板(窒化物半導体自立基板)
11 GaN自立基板
15 InGaN系活性層
1 Sapphire substrate (C-plane sapphire substrate)
2 Nitride semiconductor layer 3 Nitride semiconductor substrate (nitride semiconductor free-standing substrate)
11 GaN free-standing substrate 15 InGaN-based active layer

Claims (1)

サファイア基板上に窒化物半導体層を形成し、前記サファイア基板から分離した前記窒化物半導体層を用いて自立した窒化物半導体基板を作製する窒化物半導体基板の製造方法において、
分離された前記窒化物半導体層の表裏面の欠陥密度差に起因する反りによる前記窒化物半導体層のC軸の半径方向内方への傾きを相殺するように、予め前記サファイア基板表面の全面におけるC軸には半径方向外方に傾きを持たせたことを特徴とする窒化物半導体基板の製造方法。
In a method of manufacturing a nitride semiconductor substrate, a nitride semiconductor layer is formed on a sapphire substrate, and a self-supporting nitride semiconductor substrate is produced using the nitride semiconductor layer separated from the sapphire substrate.
So as to cancel the inclination of the radially inward in the C-axis of the nitride semiconductor layer due to warping caused by a defect density difference on the front and back surfaces of the separated the nitride semiconductor layer, the entire surface in advance the sapphire substrate surface A method for manufacturing a nitride semiconductor substrate, wherein the C-axis is inclined radially outward.
JP2011231199A 2011-10-21 2011-10-21 Manufacturing method of nitride semiconductor substrate Expired - Fee Related JP5488562B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011231199A JP5488562B2 (en) 2011-10-21 2011-10-21 Manufacturing method of nitride semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011231199A JP5488562B2 (en) 2011-10-21 2011-10-21 Manufacturing method of nitride semiconductor substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2008052902A Division JP4952616B2 (en) 2008-03-04 2008-03-04 Manufacturing method of nitride semiconductor substrate

Publications (2)

Publication Number Publication Date
JP2012020934A JP2012020934A (en) 2012-02-02
JP5488562B2 true JP5488562B2 (en) 2014-05-14

Family

ID=45775506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011231199A Expired - Fee Related JP5488562B2 (en) 2011-10-21 2011-10-21 Manufacturing method of nitride semiconductor substrate

Country Status (1)

Country Link
JP (1) JP5488562B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6144630B2 (en) * 2012-08-30 2017-06-07 日本碍子株式会社 Method for producing composite substrate, method for producing functional layer made of group 13 element nitride
JP2016008166A (en) * 2014-06-26 2016-01-18 古河機械金属株式会社 Manufacturing method of self-standing substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003113000A (en) * 2001-10-05 2003-04-18 Hitachi Cable Ltd Semiconductor epitaxial wafer and method for manufacturing the same
JP2005340747A (en) * 2003-11-04 2005-12-08 Hitachi Cable Ltd Iii-v group nitride series semiconductor substrate and manufacturing method of the same, iii-v group nitride series semiconductor device, iii-v group nitride series semiconductor substrate lot
JP4581490B2 (en) * 2004-05-31 2010-11-17 日立電線株式会社 III-V group nitride semiconductor free-standing substrate manufacturing method and III-V group nitride semiconductor manufacturing method
JP4691911B2 (en) * 2004-06-11 2011-06-01 日立電線株式会社 III-V nitride semiconductor free-standing substrate manufacturing method
JP4696935B2 (en) * 2006-01-27 2011-06-08 日立電線株式会社 III-V nitride semiconductor substrate and III-V nitride light emitting device
JP4952616B2 (en) * 2008-03-04 2012-06-13 日立電線株式会社 Manufacturing method of nitride semiconductor substrate

Also Published As

Publication number Publication date
JP2012020934A (en) 2012-02-02

Similar Documents

Publication Publication Date Title
JP4720125B2 (en) III-V nitride semiconductor substrate, method of manufacturing the same, and III-V nitride semiconductor
JP4581490B2 (en) III-V group nitride semiconductor free-standing substrate manufacturing method and III-V group nitride semiconductor manufacturing method
JP4462251B2 (en) III-V nitride semiconductor substrate and III-V nitride light emitting device
JP5051455B2 (en) Method of manufacturing nitride semiconductor substrate for epitaxial growth
KR101222299B1 (en) Group ⅲ-nitride crystal, manufacturing method thereof, group ⅲ-nitride crystal substrate and semiconductor device
JP2009132613A (en) Group iii-v nitride semiconductor substrate and its manufacturing method, group iii-v nitride semiconductor device, and lot of group iii-v nitride semiconductor substrate
JP2006253628A (en) Compound semiconductor apparatus and manufacturing method thereof
US20070215901A1 (en) Group III-V nitride-based semiconductor substrate and method of fabricating the same
JP2000106455A (en) Nitride semiconductor structure, fabrication thereof and light emitting element
JP4952616B2 (en) Manufacturing method of nitride semiconductor substrate
WO2010113423A1 (en) Method for growing crystals of nitride semiconductor, and process for manufacture of semiconductor device
JP2011126745A (en) Group iii nitride semiconductor substrate and method for producing the same
JP5056299B2 (en) Nitride semiconductor base substrate, nitride semiconductor multilayer substrate, and method of manufacturing nitride semiconductor base substrate
JP7260089B2 (en) nitride semiconductor
JP2005340747A (en) Iii-v group nitride series semiconductor substrate and manufacturing method of the same, iii-v group nitride series semiconductor device, iii-v group nitride series semiconductor substrate lot
JP2011216549A (en) METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR EPITAXIAL SUBSTRATE
JP5488562B2 (en) Manufacturing method of nitride semiconductor substrate
US8466471B2 (en) Nitride semiconductor free-standing substrate and method for making same
JP2005203418A (en) Nitride compound semiconductor substrate and its manufacturing method
JP2013040059A (en) Method for manufacturing group-iii nitride semiconductor crystal, and group-iii nitride semiconductor crystal manufactured by the same
JP2007063121A (en) METHOD FOR MANUFACTURING GaN SELF-STANDING SUBSTRATE, GaN SELF-STANDING SUBSTRATE, AND BLUE LED
JP2005057064A (en) Group iii nitride semiconductor layer and growth method thereof
JP2005020026A (en) Gallium nitride based compound semiconductor and semiconductor substrate
JP4998407B2 (en) Method for manufacturing group III-V nitride semiconductor substrate
JP4609334B2 (en) Nitride semiconductor substrate manufacturing method, nitride semiconductor substrate, and nitride semiconductor light emitting device

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130402

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20130614

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131021

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131101

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20131101

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20131106

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140210

R150 Certificate of patent or registration of utility model

Ref document number: 5488562

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R370 Written measure of declining of transfer procedure

Free format text: JAPANESE INTERMEDIATE CODE: R370

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees