JP2024119396A - Semiconductor substrate and manufacturing method thereof - Google Patents

Abstract

[Problem] To eliminate V pits in a semiconductor layer having a large number of V pits formed on its surface and to flatten the surface. [Solution] In a method for manufacturing a semiconductor substrate, a first substrate 10 having a first semiconductor layer 13 of a group III nitride semiconductor having a large number of V pits formed on its surface and a second substrate 20 having a second semiconductor layer 23 of a group III nitride semiconductor on its surface are prepared, and the first and second substrates 10, 20 are arranged so that the first substrate 10 is on the upper side and the second substrate 20 is on the lower side and the first and second semiconductor layers 13, 23 face each other, and the first and second semiconductor layers 13, 23 are annealed while flowing NH3 gas between them. [Selected Figure] Figure 2

Description

The present invention relates to a semiconductor substrate and a method for manufacturing the same.

In the semiconductor manufacturing process, semiconductor layers are annealed (heat-treated) for various purposes. For example, Patent Document 1 discloses that the distortion in the light-emitting layer is suppressed by annealing the InGaN layer while flowing NH ₃ gas. In addition, Non-Patent Document 1 discloses that a pair of substrates, each of which has an AlN layer grown on a sapphire substrate, is prepared, the substrates are arranged so that the AlN layers face each other, and the AlN layers are annealed while flowing N ₂ gas between the AlN layers, thereby improving the quality of the AlN crystal.

WO2008/078301

H. Miyake et al., J. Cryst. Growth 456 (2016) 155.

In light-receiving devices using group III nitride semiconductors, the active layer is usually composed of an InGaN layer. However, when this InGaN active layer is crystal-grown on top of a GaN underlayer, there is a problem that the energy conversion efficiency is low due to defects caused by the lattice mismatch difference between the underlayer and the active layer.

Therefore, if the base layer is made of an InGaN layer and the InGaN active layer is crystal-grown on top of it, the introduction of defects into the InGaN active layer is suppressed, and the semiconductor lattice mismatch difference between the base layer and the active layer is reduced, which is believed to result in high energy conversion efficiency.

However, when the underlayer is made of an InGaN layer, a large number of V-pits (V-shaped defects) are formed on the surface due to the large number of defects contained in the crystal, which causes a problem of poor surface flatness. As the thickness of the InGaN layer increases, the V-pits become larger, so this problem is particularly severe when the thickness of the InGaN layer exceeds the critical thickness. If the surface flatness of the underlayer is poor, the area of the underlayer for forming the active layer becomes smaller, and the active layer also becomes smaller accordingly, and the crystal growth of the active layer becomes non-uniform, resulting in a problem of low energy conversion efficiency. Thus, in the past, even if an InGaN film was grown to cover the V-pits in order to reduce the V-pits formed in the InGaN layer as the underlayer, it was not possible to grow the InGaN film without eliminating the V-pits, as described above.

The objective of the present invention is to eliminate the V-pits in a semiconductor layer having a large number of V-pits formed on its surface, thereby flattening the surface.

The present invention is a method for manufacturing a semiconductor substrate, the method including: a substrate preparation step of preparing a first substrate having a first semiconductor layer made of a Group III nitride semiconductor with a large number of V pits formed on its surface, and a second substrate having a second semiconductor layer made of a Group III nitride semiconductor on its surface; and an annealing step of arranging the first and second substrates prepared in the substrate preparation step such that the first substrate is on the upper side and the second substrate is on the lower side and the first and second semiconductor layers face each other, and annealing the first and second semiconductor layers while flowing _NH3 gas between the first and second semiconductor layers.

The present invention is a semiconductor substrate having a semiconductor layer of a group III nitride semiconductor on its surface, in which a large number of V-pits formed in the semiconductor layer are filled with a semiconductor material.

According to the present invention, a first substrate having a first semiconductor layer made of a Group III nitride semiconductor with a large number of V pits formed on its surface, and a second substrate having a second semiconductor layer made of a Group III nitride semiconductor on its surface are arranged so that the first substrate is on the upper side and the second substrate is on the lower side and the first and second semiconductor layers face each other, and the first and second semiconductor layers are annealed while flowing _NH3 gas between the first and second semiconductor layers, thereby eliminating the V pits in the first semiconductor layer of the upper first substrate and flattening the surface.

FIG. 2 is a cross-sectional view of a first and second substrate. FIG. 2 is an explanatory diagram showing an annealing step. FIG. 13 is an explanatory diagram showing a first modified example of the annealing step. FIG. 13 is an explanatory diagram showing a second modified example of the annealing step. 13 shows SEM images of the surface of the surface InGaN layer of sample substrate 1 placed on the upper side during annealing in test evaluation 1 before annealing and after annealing times of 10 minutes, 20 minutes, and 30 minutes. 13 shows SEM images of the surface of the surface InGaN layer of sample substrate 2 placed on the upper side during annealing in test evaluation 1 before annealing and after annealing times of 10 minutes, 20 minutes, and 30 minutes. 13 shows SEM images of the surface of the surface InGaN layer of sample substrate 3 placed on the upper side during annealing in test evaluation 1 before annealing and after annealing times of 10 minutes, 20 minutes, and 30 minutes. 13 shows cathode luminescence (CL) images of the surface of the surface InGaN layer at annealing times of 10 minutes, 20 minutes, and 30 minutes for sample substrate 1 placed on the upper side during annealing in test evaluation 1. 13 shows cathode luminescence (CL) images of the surface of the surface InGaN layer at annealing times of 10 minutes, 20 minutes, and 30 minutes for sample substrate 2 placed on the upper side during annealing in test evaluation 1. 13 shows cathode luminescence (CL) images of the surface of the surface InGaN layer at annealing times of 10 minutes, 20 minutes, and 30 minutes for sample substrate 3 placed on the upper side during annealing in test evaluation 1. 13 shows optical microscope images of the surface of the surface InGaN layer for sample substrate 1 placed underneath during annealing in test evaluation 1, at annealing times of 10 minutes, 20 minutes, and 30 minutes. 13 shows optical microscope images of the surface of the surface InGaN layer for sample substrate 2 placed underneath during annealing in test evaluation 1, at annealing times of 10 minutes, 20 minutes, and 30 minutes. 13 shows optical microscope images of the surface of the surface InGaN layer for sample substrate 3 placed underneath during annealing in test evaluation 1, at annealing times of 10 minutes, 20 minutes, and 30 minutes. 11 is a graph showing the results of analysis by Auger electron spectroscopy of the surface of the surface InGaN layer before and after annealing for sample substrate 1 placed on the upper side in test evaluation 1. 13 shows SEM images of the surface of the surface InGaN layer before and after annealing for each of sample substrates 1 to 3 placed on the upper side during annealing in test evaluation 2. 13 is a graph showing the results of analysis by Auger electron spectroscopy of the surface of the surface InGaN layer after annealing for sample substrate 1 placed on the upper side in test evaluation 2. 13 is a graph showing the results of analysis by Auger electron spectroscopy of the surface of the surface InGaN layer after annealing for sample substrate 2 placed on the upper side in test evaluation 2. 13 is an SEM image of the surface of the surface InGaN layer for sample substrate 1 placed on top when sample substrate X was placed on the bottom during annealing in test evaluation 3, with an annealing time of 10 minutes. 13 is an SEM image of the surface of the surface InGaN layer for sample substrate 3 placed on top when sample substrate X was placed on the bottom during annealing in test evaluation 3, with an annealing time of 10 minutes. 13 is an SEM image of the surface of the surface InGaN layer for sample substrate 2 placed on top when sample substrate Y was placed on the bottom during annealing in test evaluation 3, with an annealing time of 10 minutes. 13 is an SEM image of the surface of the surface InGaN layer for sample substrate 3 placed on top when sample substrate Y was placed on the bottom during annealing in test evaluation 3, with an annealing time of 10 minutes.

The following describes the embodiments.

The method for manufacturing a semiconductor substrate according to the embodiment includes a substrate preparation step and an annealing step.

<Substrate preparation step>
1, a first and a second substrate 10, 20 are prepared. The first substrate 10 has a first low-temperature buffer layer 12, a first intermediate semiconductor layer 13, and a first surface semiconductor layer 14 laminated in this order on a first base substrate 11. Similarly, the second substrate 20 has a second low-temperature buffer layer 22, a second intermediate semiconductor layer 23, and a second surface semiconductor layer 24 laminated in this order on a second base substrate 21.

Here, examples of the first and second base substrates 11, 21 include a sapphire substrate, a ZnO substrate, and a SiC substrate. The main surfaces of the first and second base substrates 11, 21 may be any of the a-plane, c-plane, m-plane, and r-plane, or may be crystal planes of other plane orientations, but among these, the c-plane is preferable. Here, the "main surface" refers to a surface perpendicular to the semiconductor layer growth direction, and is usually the widest surface on the substrate surface.

The first and second low-temperature buffer layers 12 and 22 are semiconductor layers formed of Group III nitride semiconductors epitaxially grown on the first and second base substrates 11 and 21, respectively. Examples of Group III nitride semiconductors forming the first and second low-temperature buffer layers 12 and 22 include binary compounds such as GaN, InN, and AlN; ternary compounds such as AlGaN and InGaN; and quaternary compounds such as AlGaInN. The film thickness of the first and second low-temperature buffer layers 12 and 22 is, for example, 10 nm or more and 50 nm or less.

The first and second intermediate semiconductor layers 13 and 23 are formed of III-nitride semiconductors epitaxially grown on the first and second low-temperature buffer layers 12 and 22, respectively. As with the first and second low-temperature buffer layers 12 and 22, the III-nitride semiconductors forming the first and second intermediate semiconductor layers 13 and 23 include, for example, binary compounds such as GaN, InN, and AlN; ternary compounds such as AlGaN and InGaN; and quaternary compounds such as AlGaInN. The first intermediate semiconductor layer 13 may be formed of the same III-nitride semiconductor as the first low-temperature buffer layer 12, or may be formed of a different III-nitride semiconductor from the first low-temperature buffer layer 12. The second intermediate semiconductor layer 23 may be formed of the same III-nitride semiconductor as the second low-temperature buffer layer 22, or may be formed of a different III-nitride semiconductor from the second low-temperature buffer layer 22. The film thickness of the first and second intermediate semiconductor layers 13, 23 is, for example, 50 nm or more and 5000 nm or less.

The first surface semiconductor layer 14 is formed of a group III nitride semiconductor epitaxially grown on the first intermediate semiconductor layer 13. A large number of V pits are formed on the surface of the first surface semiconductor layer 14 before annealing in the annealing step. Specifically, the V pit density on the surface of the first surface semiconductor layer 14 before annealing is 2×10 ⁸ cm ⁻² or more. As group III nitride semiconductors forming the first surface semiconductor layer 14, since a large number of V pits are formed on the surface, examples of the group III nitride semiconductors include {11-22} GaN as a binary compound and InGaN as a ternary compound. The first surface semiconductor layer 14 may be formed of either the same group III nitride semiconductor as the first intermediate semiconductor layer 13 or a group III nitride semiconductor different from the first intermediate semiconductor layer 13. The film thickness of the first surface semiconductor layer 14 is, for example, 50 nm or more and 5000 nm or less.

The second surface semiconductor layer 24 is formed of a group III nitride semiconductor epitaxially grown on the second intermediate semiconductor layer 23. As the group III nitride semiconductor forming the second surface semiconductor layer 24, similar to the first and second low-temperature buffer layers 12, 22 and the first and second intermediate semiconductor layers 13, 23, for example, binary compounds of GaN, InN, AlN; ternary compounds of AlGaN, InGaN; and quaternary compounds of AlGaInN. The second surface semiconductor layer 24 may be formed of the same group III nitride semiconductor as the second intermediate semiconductor layer 23, or may be formed of a group III nitride semiconductor different from the second intermediate semiconductor layer 23. The second surface semiconductor layer 24 may be formed of a group III nitride semiconductor different from the first surface semiconductor layer 14, but from the viewpoint of flattening the surface of the first InGaN layer by annealing, it is preferable that the second surface semiconductor layer 24 is formed of the same group III nitride semiconductor as the first surface semiconductor layer 14. The film thickness of the second surface semiconductor layer 24 is, for example, 50 nm or more and 5000 nm or less.

The first and second substrates 10, 20 can be fabricated by chemical vapor deposition (CVD). Examples of chemical vapor deposition (CVD) include metal organic vapor phase epitaxy (MOVPE) and hydride vapor phase epitaxy (HVPE). Of these, metal organic vapor phase epitaxy (MOVPE) is preferred for fabricating the first and second substrates 10, 20.

<Annealing step>
2, in the reactor chamber, the first and second substrates 10, 20 prepared in the substrate preparation step are arranged so that the first substrate 10 is on the upper side and the second substrate 20 is on the lower side and the first and second surface semiconductor layers 14, 24 face each other, and the first and second surface semiconductor layers 14, 24 are annealed while flowing _NH3 gas between the first and second surface semiconductor layers 14, 24. That is, face-to-face annealing is performed on the first and second substrates 10, 20.

According to the method for manufacturing a semiconductor substrate according to the embodiment, the first substrate 10 having the first surface semiconductor layer 14 of a group III nitride semiconductor on whose surface a large number of V pits are formed as described above and the second substrate 20 having the second surface semiconductor layer 24 of a group III nitride semiconductor are arranged so that the first substrate 10 is on the upper side and the second substrate 20 is on the lower side and the first and second surface semiconductor layers 14, 24 face each other, and the first and second surface semiconductor layers 14, 24 are annealed while flowing NH ₃ gas between the first and second surface semiconductor layers 14, 24, thereby eliminating the V pits in the first surface semiconductor layer 14 in the upper first substrate 10 and flattening the surface. This is believed to be because, by annealing in a state in which the first and second surface semiconductor layers 14, 24 face each other, semiconductor material moves from the lower second surface semiconductor layer 24 so as to fill the V pits in the upper first surface semiconductor layer 14. In addition, it is believed that one of the reasons for this is that dislocations in the first surface semiconductor layer 14 move laterally due to annealing.

Here, the first and second surface semiconductor layers 14, 24 are arranged so that they face each other. The first and second surface semiconductor layers 14, 24 are preferably arranged so that they face each other with a gap therebetween, but there does not necessarily have to be a gap between them. The gap between the first and second surface semiconductor layers 14, 24 is preferably 1 mm or less, more preferably 0.5 mm or less, from the viewpoint of planarizing the surface of the first surface semiconductor layer 14 by annealing.

The flow rate of the _NH3 gas is preferably 0.1 slm or more and 10 slm or less, more preferably 1 slm or more and 5 slm or less, from the viewpoint of planarizing the surface of the first surface semiconductor layer 14 by annealing. Note that, together with the _NH3 gas, _N2 gas or _H2 gas may be flowed as a carrier gas.

From the viewpoint of planarizing the surface of the first surface semiconductor layer 14 by annealing, the annealing temperature is preferably 600°C or higher and 1150°C or lower, and more preferably 800°C or higher and 1150°C or lower. From the viewpoint of planarizing the surface of the first surface semiconductor layer 14 by crystal growth of InGaN by annealing, the annealing temperature is preferably 800°C or higher and 1100°C or lower, more preferably 850°C or higher and 1100°C or lower, and even more preferably 950°C or higher and 1050°C or lower.

From the viewpoint of planarizing the surface of the first surface semiconductor layer 14 by annealing, the annealing time is preferably from 1 minute to 60 minutes, more preferably from 5 minutes to 30 minutes, and even more preferably from 10 minutes to 20 minutes.

The V pit density on the surface of the first surface semiconductor layer 14 after annealing is preferably 1×10 ⁷ cm ⁻² or less, and more preferably 1×10 ⁶ cm ⁻² or less.

The surface condition, root mean square roughness (RMS), and elements present on the surface of the first surface semiconductor layer 14 after annealing are measured using, for example, a scanning electron microscope (SEM), an atomic force microscope (AFM), and an Auger electron spectrometer, respectively.

After annealing, the first substrate 10 placed on the upper side is removed from the chamber. It is then used as a semiconductor substrate having a first surface semiconductor layer 14 of a group III nitride semiconductor on its surface, with numerous V-pits formed in the first surface semiconductor layer 14 filled with a semiconductor material to form a planarized substrate, for use in the manufacture of various semiconductor devices. For example, if the semiconductor substrate has a high-quality InGaN layer with a planarized surface, it is possible to fabricate red LEDs, LDs, solar cells, light-receiving devices, and the like with high energy conversion efficiency on top of the InGaN layer as a base layer.

In the above embodiment, the second surface semiconductor layer 24 provided on the surface of the second substrate 20 is arranged to face the first surface semiconductor layer 14 on the surface of the first substrate 10, but this is not particularly limited. For example, as shown in FIG. 3A, the second low-temperature buffer layer 22 provided on the surface of the second substrate 20 may be arranged to face the first surface semiconductor layer 14 on the surface of the first substrate 10, or as shown in FIG. 3B, the second intermediate semiconductor layer 23 provided on the surface of the second substrate 20 may be arranged to face the first surface semiconductor layer 14 on the surface of the first substrate 10.

(Test evaluation 1)
A plurality of sample substrates 1 were fabricated by epitaxially growing a 30 nm-thick low-temperature GaN buffer layer, a 2000 nm-thick undoped GaN layer, and a 200 nm-thick surface InGaN layer on a sapphire substrate having a c-plane main surface by metal-organic vapor phase epitaxy (MOVPE). The surface V-pit density of the surface InGaN layer of sample substrate 1 was 3.30×10 ⁸ cm ^-2 . The molar ratio of indium, gallium, and nitrogen in the surface InGaN layer determined by photoluminescence was In:Ga:N=2:98:100.

Furthermore, a plurality of sample substrates 2 and 3 were fabricated, each having the same configuration as sample substrate 1, except that the thicknesses of the surface InGaN layers were set to 400 nm and 700 nm, respectively. The V-pit density of the surface InGaN layer of sample substrate 2 was 2.54×10 ⁸ cm ^-2 . The V-pit density of the surface InGaN layer of sample substrate 3 was 2.23×10 ⁸ cm ^-2 .

For each of the sample substrates 1 to 3, a pair of sample substrates was placed in a chamber (flow path area 800 mm ² (=8 mm×100 mm)) of a reactor at a pressure of 100 kPa, with one on the top and the other on the bottom, and with one surface InGaN layer facing the other surface InGaN layer, and an experiment was performed in which the surface InGaN layer was annealed at an annealing temperature of 1150° C. and an annealing time of 10 minutes while flowing NH ₃ gas with a purity of 99.999% together with N ₂ gas with a purity of 99.999% as a carrier gas at a flow rate of 5 slm (see FIG. 2). The flow rate of the N ₂ gas as a carrier gas was about 10 times that of the NH ₃ gas. Experiments with annealing times of 20 minutes and 30 minutes were also performed.

Figures 4A to 4C show the surfaces of the surface InGaN layers of sample substrates 1 to 3 arranged on the upper side before annealing and after annealing times of 10 minutes, 20 minutes, and 30 minutes, respectively. Figures 5A to 5C show cathode luminescence (CL) images of the surfaces of the surface InGaN layers of sample substrates 1 to 3 arranged on the upper side after annealing times of 10 minutes, 20 minutes, and 30 minutes, respectively. Figures 6A to 6C show the surfaces of the surface InGaN layers of sample substrates 1 to 3 arranged on the lower side after annealing times of 10 minutes, 20 minutes, and 30 minutes, respectively. Figure 7 shows the results of Auger electron spectroscopy analysis using an Auger electron microscope on the surfaces of the surface InGaN layers of sample substrate 1 arranged on the upper side before annealing and after annealing (annealing time 30 minutes).

Table 1 shows the V pit density and cathodoluminescence (CL) spectrum peak wavelength of the surface InGaN layer before annealing and after annealing for 10, 20, and 30 minutes for sample substrates 1 to 3 arranged on the upper side. It also shows the root mean square roughness (RMS) measured using an atomic force microscope (AFM) for sample substrate 2 arranged on the upper side before annealing and with an annealing time of 20 minutes, and sample substrate 3 arranged on the upper side before annealing and with an annealing time of 10 and 20 minutes. The RMS was measured at one or more locations on the same substrate.

According to the results of Figures 4A to 4C and Table 1, it can be seen that in sample substrates 1 to 3 arranged on the upper side, the V pits in the surface InGaN layer were filled and disappeared by annealing. From Table 1, in sample substrates 2 and 3 arranged on the upper side, the surface roughness was 8.2 nm to 54 nm before annealing, but after annealing it became 0.67 nm to 5.3 nm, and the surface of the InGaN layer was flattened. In addition, Auger electron spectroscopy in Figure 7 confirmed that GaN crystals had grown on the surface of sample substrate 1 arranged on the upper side. According to the results of Figures 6A to 6C, the surface of the surface InGaN layer of sample substrates 1 to 3 arranged on the lower side after annealing is rough, and this is thought to be due to the movement of semiconductor material from the surface InGaN layer of the sample substrate arranged on the lower side to fill the V pits in the surface InGaN layer of the sample substrate arranged on the upper side. In addition, according to the results of Figures 5A to 5C, cathodoluminescence (CL) analysis showed that dislocations moved laterally in sample substrates 1 to 3 placed on the upper side due to annealing, which is also thought to be one of the factors that caused the surface of the InGaN layer on the upper sample substrate to become flat.

(Test Evaluation 2)
For each of sample substrates 1 to 3, an experiment similar to that of test evaluation 1 was carried out, except that the annealing temperature was 1050° C. and the annealing time was 20 minutes.

Figure 8 shows the surface of the InGaN layer before and after annealing for sample substrates 1 to 3 arranged on the upper side. Figures 9A and 9B show the results of Auger electron spectroscopy analysis using an Auger electron microscope on the surface of the InGaN layer after annealing for sample substrates 1 and 2 arranged on the upper side, respectively. Table 2 shows the V-pit density on the surface of the InGaN layer before and after annealing for sample substrates 1 to 3 arranged on the upper side. It also shows the root mean square roughness (RMS) measured using an atomic force microscope (AFM) for sample substrates 2 and 3 arranged on the upper side before and after annealing. The RMS was measured at one location on the same substrate.

The results in Figure 8 and Table 2 show that in sample substrates 1 to 3 placed on the top, the V pits in the surface InGaN layer were filled and disappeared by annealing. The results in Table 2 show that in sample substrates 2 and 3 placed on the top, the surface roughness was 8.2 nm to 54 nm before annealing, but after annealing it became 1.8 nm to 3.8 nm, and the surface of the InGaN layer was flattened. Furthermore, the results in Figures 9A and B confirmed that InGaN crystals had grown on the surfaces of sample substrates 1 and 2 placed on the top by Auger electron spectroscopy.

(Test Evaluation 3)
A plurality of sample substrates X were fabricated by epitaxially growing a 30 nm-thick low-temperature GaN buffer layer on a sapphire substrate having a c-plane main surface by metal-organic vapor phase epitaxy (MOVPE). A plurality of sample substrates Y were fabricated by epitaxially growing a 30 nm-thick low-temperature GaN buffer layer and a 2000 nm-thick undoped GaN layer in that order by metal-organic vapor phase epitaxy (MOVPE) on a sapphire substrate having a c-plane main surface.

In a chamber (flow path area 800 mm ² (= 8 mm × 100 mm)) of a reactor at a pressure of 100 kPa, the sample substrate 1 with a surface InGaN layer thickness of 200 nm was placed on the upper side and the sample substrate X was placed on the lower side, and the surface InGaN layer of the sample substrate 1 was placed so as to face the low-temperature GaN buffer layer of the sample substrate X. An experiment was performed in which the surface _InGaN layer and the low-temperature GaN buffer layer were annealed at an annealing temperature of 1150°C and an annealing time of 10 minutes while flowing NH ₃ gas with a purity of 99.999% together with N 2 gas with a purity of 99.999% as a carrier gas at a flow rate of 5 slm (see FIG. 3A). At this time, the flow rate of the N ₂ gas as a carrier gas was about 10 times the flow rate of the NH ₃ gas. An experiment was also performed using a sample substrate 3 with a surface InGaN layer thickness of 700 nm instead of the sample substrate 1. Further, an experiment was also carried out in which sample substrate Y was used instead of sample substrate X, and sample substrate 2 and sample substrate 3, each having a surface InGaN layer with a thickness of 400 nm, were used instead of sample substrate 1 (see FIG. 3B).

Figures 10A and B show the surface of the surface InGaN layer for sample substrates 1 and 3 arranged on the upper side, respectively, when sample substrate X is arranged on the lower side during annealing, with an annealing time of 10 minutes. Figures 11A and B show the surface of the surface InGaN layer for sample substrates 2 and 3 arranged on the upper side, respectively, when sample substrate Y is arranged on the lower side during annealing, with an annealing time of 10 minutes. Table 3 shows the spectral peak wavelength of the cathodoluminescence (CL) of the surface InGaN layer for sample substrates 1 to 3 arranged on the upper side for each substrate combination, with an annealing time of 10 minutes.

The results of Figures 10A and B, Figures 11A and B, and Table 3 show that the III-nitride semiconductor on the surfaces of sample substrates X and Y arranged on the lower side is GaN, which is different from the III-nitride semiconductor InGaN on the surfaces of sample substrates 1 to 3 arranged on the upper side, but as in the case of test evaluation 1, the V-pits in the surface InGaN layer of sample substrates 1 to 3 arranged on the upper side are filled and reduced, and as a result, the surface of the surface InGaN layer is flattened.

The present invention is useful in the technical field of semiconductor substrates and their manufacturing methods.

10 First substrate 11 First base substrate 12 First low-temperature buffer layer 13 First intermediate semiconductor layer 14 First surface semiconductor layer 20 Second substrate 21 Second base substrate 22 Second low-temperature buffer layer 23 Second intermediate semiconductor layer 24 Second surface semiconductor layer

Claims (4)

a substrate preparation step of preparing a first substrate having a first semiconductor layer of a Group III nitride semiconductor on the surface of which a large number of V pits are formed, and a second substrate having a second semiconductor layer of a Group III nitride semiconductor on the surface of which;
an annealing step of annealing the first and second semiconductor layers while arranging the first and second substrates prepared in the substrate preparation step so that the first substrate is on the upper side and the second substrate is on the lower side and the first and second semiconductor layers face each other, and flowing _NH3 gas between the first and second semiconductor layers;
A method for manufacturing a semiconductor substrate comprising the steps of: 2. The method for manufacturing a semiconductor substrate according to claim 1,
A method for manufacturing a semiconductor substrate, wherein the second semiconductor layer is made of a Group III nitride semiconductor that is the same as the first semiconductor layer. 2. The method for manufacturing a semiconductor substrate according to claim 1,
The method for producing a semiconductor substrate, wherein the Group III nitride semiconductor forming the first semiconductor layer is InGaN. A semiconductor substrate having a semiconductor layer made of a Group III nitride semiconductor on a surface thereof,
A semiconductor substrate in which a large number of V-pits formed in the semiconductor layer are filled with a semiconductor material.