CN103545212A - 半导体器件制造方法 - Google Patents
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Abstract
本发明公开了一种半导体器件制造方法,包括:在衬底上形成栅极堆叠结构;刻蚀栅极堆叠结构两侧的衬底,形成C型源漏凹槽;湿法腐蚀C型源漏凹槽,形成∑型源漏凹槽。依照本发明的半导体器件制造方法,通过刻蚀C型源漏凹槽并且进一步湿法腐蚀而形成∑型源漏凹槽,有效增大了沟道区应力并且精确控制了源漏凹槽深度、减小了缺陷,降低凹槽的侧壁和底部的粗糙度,提高了器件性能。
Description
技术领域
本发明涉及半导体集成电路制造领域,更具体地,涉及一种具有∑型源漏的半导体器件方法。
背景技术
进入90nm节点后,应变硅技术成为一种通过抑制短沟道效应、提升载流子迁移率来提高MOSFET器件性能的基本技术。在应变硅技术中,诸如STI、SPT、源漏硅锗嵌入、金属栅应力、刻蚀停止层(CESL)等应力技术被相继提出,通过各种方案向沟道区施加应力从而增大载流子迁移率以提高驱动能力。
在这些技术之中,源漏硅锗嵌入技术在进入90nm节点后逐渐被主流的CMOS工艺厂商采用,使用在源漏干法刻蚀后外延生长硅锗的方法提供压应力挤压沟道从而提高MOSFET的性能。在进入60nm技术节点后,某些公司在源漏刻槽方面做出了进一步改变。
如图1所示,在含有浅沟槽隔离(STI)1A的衬底1上形成由栅绝缘层2A和栅导电层2B构成的栅极堆叠结构2,在栅极堆叠结构2周围形成栅极侧墙3,以栅极侧墙3为掩模,对由STI1A包围的有源区进行干法刻蚀,通过等离子刻蚀、反应离子刻蚀等各向异性的干法刻蚀了栅极侧墙3周围的衬底1形成了第一源漏凹槽1B。其中,两条交叉虚线显示了两个(111)晶面交叉在A1点,在稍后的湿法腐蚀过程中,湿法腐蚀液对于(110)或者(100)晶面的腐蚀速率大于(111)晶面,因此腐蚀会最终停止在(111)晶面及其交点A1上,并且第一凹槽1B的侧壁(平行于栅极侧墙3的侧壁并优选与之重合)距离该交点A1的距离为a1。
随后如图2所示,采用对衬底晶向的各向异性的湿法刻蚀(例如TMAH腐蚀),对第一源漏凹槽1B进行进一步腐蚀,最终得到了剖面为Sigma(∑)型的第二源漏凹槽1C。其中,腐蚀液在侧向刻蚀第一凹槽1B侧壁直至A1点的同时,还向下刻蚀第一凹槽1B的底部,使得第二凹槽1C的底部比第一凹槽1B的底部低距离b1。如图1和图2所示,上述距离a1决定了∑型源漏凹槽1C向沟道区凹进的深度并且进而决定了稍后外延生长的SiGe和/或SiC向沟道区施加应力的大小,而上述距离b1决定了凹槽深度并且进一步决定了稍后外延生长SiGe和/或SiC源漏应力区的质量。
之后,再在sigma槽1C中外延SiGe和/或SiC。Sigma槽相对于普通的槽可以更加接近沟道,同时也会在后续的外延过程中产生较少的缺陷,最终这两点使MOSFET器件性能提升。
然而,在上述现有工艺中,由于距离a1较大,SiGe和/或SiC的应力源漏区向沟道区施加应力要经历较长距离,沟道区实际获得的应力提升有限。此外,如果单方面增长a1,则意味着在湿法腐蚀凹槽1B形成凹槽1C过程中要么增大腐蚀速率要么延长腐蚀时间,这均会使得距离b1不必要地增大,并且增大了凹槽1C底部的缺陷,降低了外延SiGe和/或SiC的质量。
发明内容
有鉴于此,本发明的目的在于提供一种创新性的半导体器件方法,通过干法刻蚀C型源漏凹槽并且进一步湿法腐蚀而形成∑型源漏凹槽,有效增大了沟道区应力并且精确控制了源漏凹槽深度、减小了缺陷,提高了器件性能。
实现本发明的上述目的,是通过提供一种半导体器件制造方法,包括:在衬底上形成栅极堆叠结构;刻蚀栅极堆叠结构两侧的衬底,形成C型源漏凹槽;湿法腐蚀C型源漏凹槽,形成∑型源漏凹槽。
其中,栅极堆叠结构包括栅极绝缘层和栅极导电层。
其中,栅极绝缘层是氧化硅、氮氧化硅、氮化硅、高k材料及其组合,其中高k材料可以选自以下材料之一或其组合构成的复合一层或多层:Al2O3,HfO2,包括HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、或HfLaSiOx至少之一在内的铪基高K介质材料,包括ZrO2、La2O3、LaAlO3、TiO2、或Y2O3至少之一在内的稀土基高K介质材料;栅极导电层是多晶硅、非晶硅、金属、金属氮化物及其组合,金属是Al、Cu、Ti、Ta、Mo、W,金属氮化物是TiN、TaN。
其中,形成C型源漏凹槽的刻蚀方法是各向同性刻蚀。
其中,形成C型源漏凹槽的刻蚀方法是先各向异性干法刻蚀后各向同性干法刻蚀。
其中,形成C型源漏凹槽的刻蚀方法是先离子注入形成非晶化区域后干法刻蚀。
其中,注入的离子是Cl、C、O、F、N。
其中,采用各向异性的湿法腐蚀液来腐蚀C型源漏凹槽。
其中,在形成∑型源漏凹槽之后还包括以下步骤:在∑型源漏凹槽中选择性外延生长SiGe和/或SiC,形成∑型应力源漏区;在应力源漏区中和/或上形成金属硅化物;完成互连。
其中,在形成栅极堆叠结构之后、或者在形成C型源漏凹槽之后、或者在形成∑型应力源漏区之后,在栅极堆叠结构两侧的衬底和/或源漏区中形成轻掺杂的源漏延伸区和/或晕状源漏掺杂区。
依照本发明的半导体器件制造方法,通过刻蚀C型源漏凹槽并且进一步湿法腐蚀而形成∑型源漏凹槽,有效增大了沟道区应力并且精确控制了源漏凹槽深度、减小了缺陷,降低凹槽的侧壁和底部的粗糙度,提高了器件性能。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1和图2为现有技术的半导体器件制造方法中源漏凹槽刻蚀步骤的剖面示意图;
图3和图4为根据本发明实施例的半导体器件制造方法中源漏凹槽刻蚀步骤的剖面示意图;以及
图5为依照本发明的半导体器件制造方法的流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
参照图5以及图3,干法刻蚀衬底形成C型源漏凹槽。
提供衬底1,提供衬底1,其可以是体Si、SOI、体Ge、GeOl、SiGe、GeSb,也可以是III-V族或者II-VI族化合物半导体衬底,例如GaAs、GaN、InP、InSb等等。为了与现有的CMOS工艺兼容以应用于大规模数字集成电路制造,衬底1优选地为体Si或者SOI-也即硅晶片或者SOI晶片。优选地,衬底1中刻蚀并且填充氧化物而形成浅沟槽隔离(STI)1A,STI1A包围了器件的有源区,在有源区中进行衬底掺杂形成轻掺杂的阱区(未示出),例如为p-或者n-阱区。
在衬底1上形成栅极堆叠结构2,其可以是前栅工艺中以后将保留的栅极堆叠结构,也可以是后栅工艺中稍后将去除的假栅极堆叠结构。具体地,在衬底1上通过LPCVD、PECVD、HDPCVD、MOCVD、热氧化等沉积方法形成较薄的栅绝缘层2A,在栅绝缘层2A上通过LPCVD、PECVD、HDPCVD、MOCVD、ALD、MBE、溅射、蒸发等方法沉积较厚的栅导电层2B。栅绝缘层2A用作前栅工艺中的栅氧化层时可以是氧化硅、氮氧化硅、氮化硅、高k材料及其组合,其中高k材料可以选自以下材料之一或其组合构成的复合一层或多层:Al2O3,HfO2,包括HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、或HfLaSiOx(其中以上各个x表示高k材料中O的含量,其依照相对介电常数k的需要而合理设定,例如是选自1~6的数且不限于整数)至少之一在内的铪基高K介质材料,包括ZrO2、La2O3、LaAlO3、TiO2、或Y2O3至少之一在内的稀土基高K介质材料。栅绝缘层2A用在后栅工艺中时,可以是氧化硅、氮氧化硅,用于刻蚀去除假栅极形成栅极凹槽时保护衬底沟道区表面,也称作垫氧化层。栅导电层2B可以是多晶硅、非晶硅、金属、金属氮化物,金属例如是Al、Cu、Ti、Ta、Mo、W,金属氮化物例如是TiN、TaN。刻蚀栅绝缘层2A与栅导电层2B形成栅极(或假栅极)堆叠结构2。
在衬底1有源区以及栅极堆叠结构2表面,通过LPCVD、PECVD、HDPCVD、溅射等常规方法,采用氮化硅、氮氧化硅、类金刚石无定形碳(DLC)等较硬并且与之前的其他结构的材料相比具有较大刻蚀选择性的材料,形成介质层并且刻蚀形成栅极侧墙3。
以栅极侧墙3为掩模,刻蚀栅极侧墙3两侧衬底1,在衬底1中形成了C型的源漏凹槽1B。形成C型源漏凹槽1B的方法,可以是直接采用各向同性的刻蚀(例如氧化剂加H F基酸性腐蚀液的湿法腐蚀,或者各向同性干法刻蚀),或者先采用等离子体刻蚀、反应离子刻蚀(RIE)等各向异性的干法刻蚀技术然后采用各向同性干法刻蚀,或者先通过包括Cl、C、O、F、N等的离子注入使得衬底1将要形成源漏区的区域非晶化(也即形成非晶化区域)然后进行干法刻蚀。
其中,与现有技术的图1、图2不同的是,C型源漏凹槽1B的侧壁与栅极侧墙3的侧壁相比,向沟道区凹进的深度更大,这是通过选择刻蚀气体、压力、流量等工艺参数来实现的。
现有技术的图1、图2所示的是各向异性的刻蚀。向异性刻蚀过程中通常主要应用氯气、溴化氢作为刻蚀气体,在刻蚀过程中通过在侧壁生成聚合物保护侧壁。
而本发明中形成C形凹槽的过程主要为各向同性刻蚀的过程,主要是通过化学反应的刻蚀方法来形成,从而避免了物理轰击过程中对底部的辅助刻蚀,降低了底部的刻蚀速率,最终形成C形凹槽。例如本发明的各向同性刻蚀主要是采用碳氟基气体(例如CF4、CH2F2、CH3F、CHF3等等)作为刻蚀气体。
此外,为了使凹槽更加向沟道区延伸以及避免各项同性刻蚀的不可控性,可以在源漏区先各向异性刻蚀,然后再进行各向同性刻蚀。本专利的核心是形成与sigma槽形状较类似的C形凹槽,这样在后续的湿法腐蚀形成sigma凹槽的时间就会较短,从而底部腐蚀的时间也较短,从而使sigma凹槽的槽深不至于过深。
具体地,所谓C型源漏凹槽,意味着源漏凹槽1B的侧壁(特别是靠近沟道区的侧壁)并非(基本)垂直侧壁而是基本为曲面,并且中部宽度要大于上部和/或下部宽度,也即栅极侧墙3以及栅极堆叠结构2至少部分地悬出源漏凹槽1B,进而使得源漏凹槽在靠近沟道区一侧具有朝向沟道区的凹进。值得注意的是,C型源漏凹槽不必完全如图3所示为半圆形,而是可以依照刻蚀条件选择而为各种曲面(例如圆面、椭圆面、双曲面、马鞍面等等,并且优选地向沟道区凹进的距离要大于等于源漏凹槽深度的1/4,并且更优选地要大于等于1/2),只要其朝向沟道区凹进即可。与图1、图2所示的现有技术类似,两个(111)晶面在点A2处交叉,C型源漏凹槽1B侧壁与交点A2之间的最大距离为a2。由于C型凹槽1B较之传统的垂直侧壁向沟道区凹进深度增大,使得距离a2将小于传统的距离a1,因此在后续腐蚀形成∑型源漏凹槽并且外延应力源漏区时,应力源漏区更贴近沟道区,从而可以为沟道区提供更高的应力。
此后,参照图5以及图4,湿法刻蚀C型源漏凹槽,形成∑型源漏凹槽。
优选地,采用四甲基氢氧化铵(TMAH)等各向异性的湿法腐蚀液,进一步腐蚀C型源漏凹槽1B,由于衬底1各晶面上腐蚀速率不一致,腐蚀将停止在{111}晶面及其交点A2处,由此而形成∑型源漏凹槽1C。所谓∑型源漏凹槽,意味着源漏凹槽1C的侧壁并非垂直侧壁而是基本由两段折线构成,并且中部宽度要大于上部和/或下部宽度,也即栅极侧墙3以及栅极堆叠结构2至少部分地悬出源漏凹槽1C,凹槽靠近沟道区的一侧具有朝向沟道区的凹进。由于在图3中形成的源漏凹槽1B中距离A2小于现有技术的距离A1,在同样的腐蚀条件下,依照本发明的湿法腐蚀步骤可以有足够的时间使得源漏凹槽1C表面更加光滑并且不至于使得源漏凹槽1C的底部低于源漏凹槽1B底部的距离b2太深,从而有利于∑型源漏凹槽形状的控制。此外,还可以制备粗糙度较低的sigma槽从而使后续的外延过程中产生较少的缺陷,最终对沟道提供更大的应力。
此后,与现有技术相同或者类似,执行后续工艺,完成MOSFET制造。例如,在∑型源漏凹槽1C中选择性外延生长SiGe和/或SiC而形成应力源漏区;在应力源漏区中和/或上形成金属硅化物以减小源漏电阻,其中金属硅化物例如是NiSi、PtSi、CoSi、PtNiSi、SnSi、TiSi等;在后栅工艺中,可以在整个器件上沉积层间介质层(ILD),随后刻蚀去除假栅极堆叠2形成栅极沟槽,在栅极沟槽中沉积高k材料的栅绝缘层以及金属材料的栅导电层,构成最终栅极堆叠结构;刻蚀ILD形成源漏接触孔,在接触孔中沉积W、Mo、Cu等金属形成接触塞,完成互连。优选地,在图3中形成栅极堆叠结构2之后、或者在形成C型源漏凹槽1B之后、或者在图4之后的外延生长应力源漏区之后,在栅极堆叠结构2两侧的衬底1中进行源漏轻掺杂注入,形成轻掺杂的源漏延伸区(LDD结构)和/或晕状源漏掺杂区(Halo结构)。
本专利的核心是形成与sigma槽形状较类似的C形凹槽,这样在后续的湿法腐蚀形成sigma凹槽的时间就会较短,从而底部腐蚀的时间也较短,从而使sigma凹槽的槽深不至于过深。同时在sigma凹槽深度相同的情况下,该专利的方法可以对侧壁(侧壁为{111}面,它的腐蚀速率最小,所以腐蚀时间越长,,它的表面将越光滑)进行更长时间的腐蚀,从而可以使侧壁更加光滑。另外一个核心就是刻蚀形成C型槽的时候凹槽会沿着侧墙下边缘向沟道方向延伸,从而导致后续形成的sigma凹槽向沟道延伸,从而能够对沟道提供更大的应力。
依照本发明的半导体器件制造方法,通过刻蚀C型源漏凹槽并且进一步湿法腐蚀而形成∑型源漏凹槽,有效增大了沟道区应力并且精确控制了源漏凹槽深度、降低凹槽的侧壁和底部的粗糙度,减小了缺陷,提高了器件性能。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (10)
1.一种半导体器件制造方法,包括:
在衬底上形成栅极堆叠结构;
刻蚀栅极堆叠结构两侧的衬底,形成C型源漏凹槽;
湿法腐蚀C型源漏凹槽,形成∑型源漏凹槽。
2.如权利要求1的半导体器件制造方法,其中,栅极堆叠结构包括栅极绝缘层和栅极导电层。
3.如权利要求2的半导体器件制造方法,其中,栅极绝缘层是氧化硅、氮氧化硅、氮化硅、高k材料及其组合,其中高k材料可以选自以下材料之一或其组合构成的复合一层或多层:Al2O3,HfO2,包括HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、或HfLaSiOx至少之一在内的铪基高K介质材料,包括ZrO2、La2O3、LaAlO3、TiO2、或Y2O3至少之一在内的稀土基高K介质材料;栅极导电层是多晶硅、非晶硅、金属、金属氮化物及其组合,金属是Al、Cu、Ti、Ta、Mo、W,金属氮化物是TiN、TaN。
4.如权利要求1的半导体器件制造方法,其中,形成C型源漏凹槽的刻蚀方法是各向同性刻蚀。
5.如权利要求1的半导体器件制造方法,其中,形成C型源漏凹槽的刻蚀方法是先各向异性干法刻蚀后各向同性干法刻蚀。
6.如权利要求1的半导体器件制造方法,其中,形成C型源漏凹槽的刻蚀方法是先离子注入形成非晶化区域后干法刻蚀。
7.如权利要求6的半导体器件制造方法,其中,注入的离子是Cl、C、O、F、N。
8.如权利要求1的半导体器件制造方法,其中,采用各向异性的湿法腐蚀液来腐蚀C型源漏凹槽。
9.如权利要求1的半导体器件制造方法,其中,在形成∑型源漏凹槽之后还包括以下步骤:在∑型源漏凹槽中选择性外延生长SiGe和/或SiC,形成∑型应力源漏区;在应力源漏区中和/或上形成金属硅化物;完成互连。
10.如权利要求1至9任一项的半导体器件制造方法,其中,在形成栅极堆叠结构之后、或者在形成C型源漏凹槽之后、或者在形成∑型应力源漏区之后,在栅极堆叠结构两侧的衬底和/或源漏区中形成轻掺杂的源漏延伸区和/或晕状源漏掺杂区。
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CN105097539A (zh) * | 2014-05-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 一种制作半导体器件的方法 |
CN105097539B (zh) * | 2014-05-21 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | 一种制作半导体器件的方法 |
CN106158647A (zh) * | 2015-04-13 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制备工艺 |
CN106856168A (zh) * | 2015-12-09 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
CN106856168B (zh) * | 2015-12-09 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
CN109037070A (zh) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法及半导体器件 |
CN107910259A (zh) * | 2017-11-08 | 2018-04-13 | 上海华力微电子有限公司 | 一种制备西格玛凹槽的方法 |
CN107910259B (zh) * | 2017-11-08 | 2021-03-12 | 上海华力微电子有限公司 | 一种制备西格玛凹槽的方法 |
CN113299809A (zh) * | 2021-05-24 | 2021-08-24 | 錼创显示科技股份有限公司 | 微型发光元件及其显示装置 |
Also Published As
Publication number | Publication date |
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CN103545212B (zh) | 2016-09-21 |
US9006057B2 (en) | 2015-04-14 |
WO2014012276A1 (zh) | 2014-01-23 |
US20140057404A1 (en) | 2014-02-27 |
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